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Electrical Computers And Digital Processing Systems: Virtual Machine Task Or Process Management Or Task Management/control > Task Management Or Control > Process Scheduling > Multitasking, Time Sharing > Context Switching Context SwitchingContext Switching patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070261058 - Method and means for context-based measurement of worked time The present invention relates to a method and an arrangement for a first individual to report worked time based on his context log containing information about contextual aspects, related to the first individual, as a function of time. From information from the context log, a context graph of the first ... 11/01/07 - 20070256079 - Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, ... 08/16/07 - 20070192767 - Reduced data transfer during processor context switching Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper ... 06/28/07 - 20070150900 - Data structure and management techniques for local user-level thread data Data structure creation, organization and management techniques for data local to user-level threads are provided. Other embodiments are also described and claimed. ... 06/14/07 - 20070136733 - Method, medium and apparatus storing and restoring register context for fast context switching between tasks A method, medium and apparatus for storing and restoring a register context for a fast context switching between tasks is disclosed. The method, medium and apparatus may improve overall operating speed of a system by increasing the speed of context switching. The method may include adding an update code for ... 06/07/07 - 20070130569 - Method, apparatus and program storage device for providing a no context switch attribute that allows a user mode thread to become a near interrupt disabled priority A method, apparatus and program storage device for providing a no context switch attribute that allows a user mode thread to become a near interrupt disabled priority is disclosed. A thread includes a no context switch attribute. Control of a thread based on the no context switch attribute is much ... 05/31/07 - 20070124736 - Acceleration threads on idle os-visible thread execution units Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or ... 03/29/07 - 20070074224 - Kernel based profiling systems and methods Profiling systems and methods. A profiling system comprises a processor that runs a kernel including a scheduler. The scheduler locates a context that to be switched to, records a time and an identification of the context, and switches to the context for execution. The context comprises a thread, a process, ... 03/29/07 - 20070074223 - Operating systems A method of enabling multiple different operating systems to run concurrently on the same RISC computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general ... 03/01/07 - 20070050779 - Task execution device and method A task execution method for executing a plurality of tasks while switching the tasks from one to another by time-sharing, wherein an allocated time is allocated for each of the plurality of tasks, and the plurality of tasks includes a plurality of first-type tasks and a single second-type task, and ... 02/22/07 - 20070044106 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions ... 02/22/07 - 20070044105 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), ... 02/22/07 - 20070044104 - Adaptive scheduling and management of work processing in a target context in resource contention A computing environment and techniques are provided for processing work out of order in one or more processing contexts. The processing techniques include: determining, for a processing context having an associated stack of waiting resources, whether a last-in listed resource in the stack of waiting resource is available, and if ... 02/08/07 - 20070033593 - System and method for wireless broadband context switching A method for switching between instruction contexts within a time interval in a multi-mode wireless broadband processing system. The method can include executing critical task operations that complete execution within a time interval, a critical task including a plurality of critical task operations, executing non-critical task operations that are able ... 02/01/07 - 20070028244 - Computer system para-virtualization using a hypervisor that is implemented in a partition of the host system A virtualization infrastructure that allows multiple guest partitions to run within a host hardware partition. The host system is divided into distinct logical or virtual partitions and special infrastructure partitions are implemented to control resource management and to control physical I/O device drivers that are, in turn, used by operating ... 01/25/07 - 20070022429 - Lock sequencing In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads ... 01/25/07 - 20070022428 - Context switching method, device, program, recording medium, and central processing unit In an application in which context switching often occurs such as in a real time OS, it is possible to significantly reduce the overhead caused by the context switching. The OS issues a Swap instruction and a context switch starts. The Swap instruction is issued together with a thread (i.e., ... 12/07/06 - 20060277552 - Facilitating handling of exceptions in a program implementing a m-on-n threading model A method for facilitating handling of exceptions in object code transformed from a 1-to-1 threading model to a M-to-N threading model comprises transforming object code having a 1-to-1 threading model to a M-to-N threading model, saving context of a Runnable section of the object code into a context object in ... 10/12/06 - 20060230409 - Multithreaded processor architecture with implicit granularity adaptation A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new threads and having a novel operational semantics. If a hardware ... 10/12/06 - 20060230408 - Multithreaded processor architecture with operational latency hiding A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency ... 09/28/06 - 20060218559 - Method and system for variable thread allocation and switching in a multithreaded processor Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, ... 09/14/06 - 20060206902 - Variable interleaved multithreaded processor method and system Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The ... 08/24/06 - 20060190946 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread context A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions ... 08/24/06 - 20060190945 - Symmetric multiprocessor operating system for execution on non-independent lightweight thread context A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), ... 07/06/06 - 20060150194 - Methods and apparatuses to maintain multiple execution contexts A method, apparatus, and system in which a two or more execution contexts of threads are maintained simultaneously using stack switching in an operating environment in which merely one thread can be executed at a given point in time. Execution of instructions in a callee thread is suspended and the ... 05/25/06 - 20060112394 - Computer system A general-purpose OS (operating system) is used as a host OS and a real-time OS operating as one or more tasks on the host OS is used as a guest OS. An interrupt handler and a task on the host OS and an interrupt handler and a task on the ... 01/19/06 - 20060015876 - Light weight context switching technique An apparatus, a method, and a computer program product are provided for more efficiently allowing context switching. Currently, context switching can be costly because of both memory requirements to store data from pre-empted applications, as well as the bus requirements to move the data at pre-emption. To alleviate at least ... 01/05/06 - 20060005200 - Systems and methods for running a legacy 32-bit x86 virtual machine on a 64-bit x86 processor The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i.e., REAL MODE and PROTECTED MODE (V86 SUB-MODE, RING-0 SUB-MODE, and RING-3 ... 01/05/06 - 20060005199 - Adaptive algorithm for selecting a virtualization algorithm in virtual machine environments Method for selecting a virtualization algorithm to virtualize a context change. An exit-enter time (EET) to exit and enter a context and a save-restore time (SRT) to save and restore a machine state are calculated. A selective algorithm that selectively saves and restores the machine state when there is a ... 10/06/05 - 20050223385 - Method and structure for explicit software control of execution of a thread including a helper subthread Software instructions in a single thread code sequence with a helper subthread are executed on a processor of a computer system. The execution causes the computer system, for example, to (i) determine whether information associated with a long latency instruction is available, and when the data is unavailable, to (ii) ... 08/18/05 - 20050183088 - Method for the direct call of a function by a software module by means of a processor with a memory-management unit (mmu) A method for the direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. In today's multitasking operating systems, the call of a function of a first task by a second ... 06/09/05 - 20050125802 - User-programmable low-overhead multithreading A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instructions that identify an asynchronous trigger condition. The asynchronous trigger condition may ... 06/09/05 - 20050125801 - Method and apparartus for context switching in computer operating systems The present invention provides for a method and apparatus for a computer implemented system including a processor and cache memory arranged to receive operating system instructions for context switching between processes, and including control means for writing back cache data to memory means during processor idle cycle at completion of ... ### FreshPatents.com Support |