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Data Processing: Software Development, Installation, And Management > Software Program Development Tool (e.g., Integrated Case Tool Or Stand-alone Development Tool) > Translation Of Code > Compiling Code > Analysis Of Code Form > Including Graph Or Tree Representation (e.g., Abstract Syntax Tree Or Ast) Including Graph Or Tree Representation (e.g., Abstract Syntax Tree Or Ast)Including Graph Or Tree Representation (e.g., Abstract Syntax Tree Or Ast) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/06/07 - 20070209033 - Source program processing method Comparison indices each for two components incorporated in a source program are used for easy and quantitative evaluation of functional redundancy in the program, effective and accurate extraction of redundant code segments from the program and also effective and accurate extraction of components to be modified simultaneously. A tree T ... 07/26/07 - 20070174827 - System for reducing the number of programs necessary to render an image Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. The combined filter emerging from the combination spares the processor time and the creation of an entire intermediary image. The system further provides ... 07/05/07 - 20070157184 - Statement shifting to increase parallelism of loops A method for statement shifting to increase the parallelism of loops includes constructing a data dependence graph (DDG) to represent dependences between statements in a loop, constructing a basic equations group from the DDG, constructing a dependence equations group derived in part from the basic equations group, and determining a ... 03/29/07 - 20070074190 - Use of different color sequences for variables of different sizes and different semantics Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments, in addition to the above-described grouping, ... 03/29/07 - 20070074189 - Summarizing application performance in a large system from a components perspective A process of analyzing performance of a computer program including a plurality of components, each component comprising a plurality of methods, the program being executable by carrying out a plurality of calling sequences, each calling sequence includes a plurality of invocations of the methods, the process includes steps of: receiving ... 03/08/07 - 20070055966 - Yet another transformation language (yatl) A practical language for writing analysis and transformation tools for C/C++ and other languages is provided. This language, YATL, is imperative in style and designed to be easy to use for someone familiar with the grammar of the target language. It allows the developer to describe transformations with reference to ... 01/18/07 - 20070016898 - Method and system for finding evolving regions in graphs without persistent node identity A system, method, and computer program for identifying evolving regions in a graph of interrelated nodes representing a computer system environment. The method includes generating a series of samples (302) of the environment. Each sample includes a plurality of interrelated nodes (502) and at least one edge (504) classified into ... 09/21/06 - 20060212860 - Method for performing information-preserving dtd schema embeddings Method for performing information-preserving DTD schema embeddings between a source schema when matching a source schema and a target schema. The preservation is realized by a matching process between the two schemas that finds a first string marking of the target schema, evaluates a legality of the first string marking, ... 09/14/06 - 20060206882 - Method and system for linear tasking among a plurality of processing units System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless interoperability between them. Computer program software and methods of and systems and devices for sharing of content, applications, resources and control across similar and dissimilar permanently or ... 09/07/06 - 20060200811 - Method of generating optimised stack code The present invention relates to a method for generating optimised stack code for a stack-based machine from a register-based representation of the original code. The method includes the steps of: creating a dependence graph from the representation; removing true dependencies from the dependence graph by matching portions of the dependence ... 03/30/06 - 20060070048 - Code-coverage guided prioritized test generation A method for generating test cases for a program is disclosed. The method combines features of path-oriented and goal-oriented software testing. The illustrative embodiment constructs a control-flow graph with nodes that correspond to invocations of subroutines, and constructs control-flow graphs for the source code of such nodes as well. A ... 03/30/06 - 20060070047 - System, method and apparatus for dependency chain processing Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is ... 03/02/06 - 20060048113 - Data flow graph processing method and processing apparatus provided with reconfigurable circuit A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order ... 03/02/06 - 20060048112 - Enhanced compiled representation of transformation formats Enhanced compiled representation of transformation formats to enable rapid application development and deployment is described. Techniques for partitioning data in a transformation include populating a table with a functoid associated with a functoid tree root, traversing the table and generating a page object corresponding to a page number found in ... 03/02/06 - 20060048111 - Method and apparatus for determining the profitability of expanding unpipelined instructions A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded. ... 02/09/06 - 20060031823 - Method and system for configuring a dependency graph for dynamic by-pass instruction scheduling There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to ... 12/29/05 - 20050289526 - Editing, creating, and verifying reorganization of flowchart, and transforming between flowchart and tree diagram Provides methods for transforming a flowchart to an equivalent tree diagram, methods for transforming an equivalent tree diagram to a flowchart, methods for verifying reorganization of a flowchart, methods for editing a flowchart, methods for creating a flowchart and a flowchart editor. A flowchart includes one or more logic structures ... 12/22/05 - 20050283768 - Data flow graph processing method, reconfigurable circuit and processing apparatus A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in ... 12/08/05 - 20050273776 - Assembler supporting pseudo registers to resolve return address ambiguity An assembler, which can form part of a development/debug system, supports pseudo instructions to enable the assembler to resolve return address ambiguities. ... 11/24/05 - 20050262489 - Knowledge representation language and knowledge processing environment Described is a knowledge representation language and knowledge processing environment. Embodiments described include an environment for storing, retrieving, transmitting, and reasoning over knowledge. Knowledge is represented using three basic elements: (1) there are concepts, which represent objects or ideas; (2) there are relations, which represent structures and describe the roles ... 11/24/05 - 20050262488 - System and method for managing cross project dependencies at development time A method for responding to a change in source code, said method comprising: interconnecting a plurality of nodes to form a graph data structure wherein the graph embodies at least one dependency between a plurality of software projects; traversing the graph to identify dependent code affected by the change; evaluating ... 10/27/05 - 20050240913 - Method for generating organizational structure and method for controlling authorization thereof A method of generating organizational structure and a method of controlling authorization thereof are provided. The method separates an organization into a plurality of nodes and links, and defines attributes for nodes and links, so as to describe the details of nodes and links, respectively. In case an attribute of ... 09/08/05 - 20050198623 - Managing topology changes in media applications Systems and methods for resolving a partial topology are disclosed. In one embodiment a media engine includes a topology loader module that receives a partial topology from another module associated with the media engine. The topology loader implements logic operations that convert a partial topology into a full topology, which ... 09/01/05 - 20050193381 - Methods and arrangements for automated change plan construction and impact analysis Methods and arrangements for operating distributed computing systems, and more particularly, to techniques for constructing and analyzing change plans are disclosed. Included are an arrangement for submitting a request for change to the system, an arrangement for specifying the order in which tasks execute in compliance with data and temporal ... 08/18/05 - 20050183075 - Method and apparatus for removal of asynchronous events in complex application performance analysis A method and apparatus for identifying a minimum call tree data structure from a plurality of call tree data structures are provided. With the apparatus and method, call tree data structures are generated for two or more executions of a build of a computer program. The apparatus and method perform ... 08/18/05 - 20050183074 - Method and apparatus for identifying differences in runs of a computer program due to code changes A method and apparatus for identifying differences in runs of a computer program that are due to changes in the code of the computer program. With the apparatus and method, call trees are generated for two or more builds of a computer program. The apparatus and method perform a “tree-subtract” ... 07/21/05 - 20050160411 - Apparatus and method for managing design of a software system using dependency structure A method and apparatus for managing, in a computer system, design of a software system. Various embodiments include receiving an input to the computer system specifying dependency relationships among subsystems of the software system and providing an output from the computer system responsive to the input. A rule is imposed ... 07/07/05 - 20050149917 - Vertical requirements development system and method A vertical requirements development method is provided for developing requirements for a system to be developed. The system to be developed includes top-level requirements and is representable by a program specification tree made up of multiple layers of individual system elements, with each lower layer of the multiple layers comprising ... 06/09/05 - 20050125781 - Method of compiling schema mapping A method for compiling a mapping between a source schema and a target schema is provided. The method comprises multiple passes, including determining source node dependencies, matching hierarchy, and generating code. The method may further comprise initializing node dependency memory prior to determining source node dependencies, and freeing node dependency ... ### FreshPatents.com Support |