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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Design Of Semiconductor Mask > Pattern Exposure Pattern ExposurePattern Exposure patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266365 - Integrated circuit design meethod, design assistance program and integrated circuit design system using such integrated circuit design method [SOLVING MEANS] A trial integrated circuit is produced based on pattern information for a trial production, without using a photomask, under a common design circumstance which can be utilized in both a photomaskless step of producing an integrated circuit based on pattern information without using a photomask and a photomask ... 10/25/07 - 20070250805 - System and method for examining mask pattern fidelity A method and system is disclosed for examining mask pattern fidelity. A mask picture is generated from a first mask with a first OPC model applied to a mask design. The mask picture is converted into a mask based simulation file. A first simulation is conducted under a first set ... 10/04/07 - 20070234269 - Light intensity distribution simulation method and computer program product A light intensity distribution simulation method for predicting an intensity distribution of light on a substrate when photomask including a pattern is irradiated with light in which a shape distribution of an effective light source is defined includes extracting plural point light sources from a shape distribution of the effective ... 09/27/07 - 20070226677 - Performance in model-based opc engine utilizing efficient polygon pinning method Methods, and a program storage device for executing such methods, for performing model-based optical proximity correction by providing a mask matrix having a region of interest (ROI) and locating a plurality of points of interest within the mask matrix. A first polygon having a number of vertices representative of the ... 09/27/07 - 20070226676 - Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge ... 09/06/07 - 20070209030 - System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the ... 08/23/07 - 20070198966 - Method for time-evolving rectilinear contours representing photo masks Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 08/23/07 - 20070198964 - Multi-dimensional analysis for predicting ret model accuracy A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the ... 08/09/07 - 20070186208 - Mask-pattern determination using topology types A method for determining a mask pattern is described. During the method, a first mask pattern that includes a plurality of second regions corresponding to the first regions of the photo-mask is provided. Then, a second mask pattern is determined based on the first mask pattern and differences between a ... 08/09/07 - 20070186207 - Method and apparatus for printing patterns with improved cd uniformity An aspect of the present invention includes a method to pattern a workpiece with improved CD uniformity using a partially coherent electromagnetic radiation source. Said method including the actions of: determining, for a plurality of layers in said workpiece, CD uniformity as a function of a number of exposure flashes, ... 07/26/07 - 20070174808 - Method and apparatus for determining a process model that uses feature detection One embodiment can provide a system for determining a process model that models an effect of one or more semiconductor manufacturing processes. During operation, the system can receive a test layout. Next, the system can receive empirical data which is obtained using a process that includes subjecting the test layout ... 07/26/07 - 20070174807 - Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system To provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each ... 07/12/07 - 20070162889 - Method and apparatus for providing optical proximity features to a reticle pattern for deep sub-wavelength optical lithography A method of generating a mask design having optical proximity correction features disposed therein. The methods includes the steps of obtaining a desired target pattern having features to be imaged on a substrate; determining an interference map based on the target pattern, the interference map defining areas of constructive interference ... 07/12/07 - 20070162888 - Method and apparatus to determine if a pattern is robustly manufacturable One embodiment provides a method to determine if a pattern is robustly manufacturable. During operation, the system may receive a first pattern and a design intent, wherein the first pattern is intended to generate the design intent. Next, the system may determine a second pattern using the design intent, wherein ... 07/12/07 - 20070162887 - Method of fabricating photo mask Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an ... 07/05/07 - 20070157153 - Yield-limiting design-rules-compliant pattern library generation and layout inspection A method and system is provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match ... 07/05/07 - 20070157152 - Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance ... 06/28/07 - 20070150850 - Photomask evaluation method, photomask evaluation apparatus, and semiconductor device manufacturing method According to an aspect of the invention, there is provided a photomask evaluation method including, acquiring a pattern image of a photomask, generating sidewall angle data on the sidewall angle of a pattern from the pattern image, extracting a pattern outline from the pattern image to generate outline data, and ... 05/10/07 - 20070106973 - Diffused aerial image model semiconductor device fabrication A lithography method has a simulation method for mathematically approximating a photoresist film pattern with a Diffused Aerial Image Model (“DAIM”) for semiconductor device fabrication. The DAIM is applied with at least two acids having heterogeneous diffusion characteristics. ... 05/10/07 - 20070106972 - Method for fabricating integrated circuit features The present invention is directed to a method for conversion of an integrated circuit design into a set of masks for fabrication of an integrated circuit that optimizes use of an edge based image transfer mask process. ... 05/03/07 - 20070101310 - Model of sensitivity of a simulated layout to a change in original layout, and use of model in proximity correction A memory is encoded with a model of sensitivity of a distorted layout generated by simulation of a wafer fabrication process, with respect to a change in an original layout that is input to the simulation. The sensitivity model comprises an expression of convolution of the original layout with spatial ... 04/26/07 - 20070094635 - Optical proximity correction system and methods thereof An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of ... 04/26/07 - 20070094634 - Method for checking printability of a lithography target A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A disclosed embodiment has application to a process for producing a photomask for use in the printing of a pattern on a wafer ... 04/12/07 - 20070083847 - Designer's intent tolerance bands for proximity correction and checking A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, ... 04/05/07 - 20070079278 - Method and apparatus for reducing opc model errors A method is provided of accessing model error in an optical proximity correction (OPC) model. The method begins by obtaining a preliminary mask using an OPC model, creating an etched wafer from the preliminary mask using lithography, and measuring a specified critical dimension (CD) on the wafer and a second ... 03/29/07 - 20070074146 - Method for designing mask pattern and method for manufacturing semiconductor device A semiconductor chip is manufactured using a cell library pattern obtained by performing OPC (optical proximity correction) process at the time of a cell single arrangement to a cell library pattern which forms a basic structure of a semiconductor circuit pattern in advance. A plurality of cell libraries are arranged ... 03/29/07 - 20070074145 - Mask pattern design method and manufacturing method of semiconductor device To a cell library pattern which makes the basic constitution of a semiconductor circuit pattern, OPC processing is performed beforehand, and a semiconductor chip is produced using this cell library pattern. Since it is influenced by the pattern of the cell arranged to the circumference and the pattern arranged around ... 03/29/07 - 20070074144 - Method and system for selective optical pattern compensation A method and system for making a photographic mask. The method includes determining a first contact area, processing information associated with the first contact area, and determining whether a first optical compensation should be applied to the first contact area based on at least information associated with the first contact ... 03/29/07 - 20070074143 - Dense opc A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared ... 03/29/07 - 20070074142 - Integrated circuit layout methods The present invention provides methods of post-layout processing, such as OPC post-processing, through partitioning of integrated circuit data files. Partitioning methods of the present invention comprise forming partitioned identical cell groups. Each partitioned identical cell group comprises identical cells such that the cells within a partitioned group include identical cell ... 03/22/07 - 20070067752 - Method for verifying optical proximity correction using layer versus layer comparison A method for verifying optical proximity correction (OPC) using a layer-versus-layer (LVL) comparison. The method includes performing optical proximity correction of an original design of a semiconductor device to prepare a revised design of the semiconductor device; comparing the revised design and the original design with each other; dividing deviation ... 03/15/07 - 20070061773 - Method for selecting and optimizing exposure tool using an individual mask error model Methods are disclosed for selecting and optimizing an exposure tool using an individual mask error model. In one embodiment, a method includes selecting a model of a lithography process including an optical model of an exposure tool and a resist model, creating an individual mask error model representing a mask ... 03/15/07 - 20070061772 - System and method for mask verification using an individual mask error model Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error ... 03/15/07 - 20070061771 - Method for reticle shapes analysis and correction A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the ... 02/15/07 - 20070038973 - Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout One embodiment of the present invention determines the effect of placing an assist feature at a location in a layout. During operation, the system receives a first value which was pre-computed by convolving a model with a layout at an evaluation point, wherein the model models semiconductor manufacturing processes. Next, ... 02/15/07 - 20070038972 - Method for optimizing a photolithographic mask The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients ... 02/01/07 - 20070028206 - Layout generation and optimization to improve photolithographic performance Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance ... 01/25/07 - 20070022402 - System and method for lithography simulation There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present ... 01/25/07 - 20070022401 - Method of correcting mask pattern and correcting apparatus thereof A method of correcting a mask pattern is provided. First, an original writer drawing data of a circuit layout pattern is inputted. Then, according to the original writer drawing data, a correcting writer rule is selected by searching from a look-up table. According to the correcting writer rule, the original ... 01/11/07 - 20070011648 - Fast systems and methods for calculating electromagnetic fields near photomasks Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 01/11/07 - 20070011647 - Optimized photomasks for photolithography Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 01/04/07 - 20070006118 - Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment ... 01/04/07 - 20070006117 - Method for optimally converting a circuit design into a semiconductor device A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design information, which represents a priority portion of the circuit design, is extracted from the first set of design information. The ... 01/04/07 - 20070006116 - Method for real time monitoring and verifying optical proximity correction model and method This invention relates to a method for real time monitoring and verifying optical proximity correction (OPC) models and methods in production. Prior to OPC is performed on the integrated circuit layout, a model describing the optical, physical and chemical processes involving lithography should be obtained accurately and precisely. In general, ... 12/14/06 - 20060282814 - Method for verifying and choosing lithography model A test mask with both verification structures and calibration structures is provided to enable the formation of an image of at least one verification structure and at least one calibration structure at a plurality of different test site locations under different dose and defocus conditions to allow the calibration structures ... 12/07/06 - 20060277522 - Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs Optical proximity effects (OPEs) are a well-known phenomenon in photolithography. OPEs result from the structural interaction between the main feature and neighboring features. It has been determined by the present inventors that such structural interactions not only affect the critical dimension of the main feature at the image plane, but ... 12/07/06 - 20060277521 - Method, program product and apparatus for performing double exposure lithography A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process. The method includes the steps of: defining an initial H-mask corresponding to the target pattern; defining an initial V-mask corresponding to the target ... 12/07/06 - 20060277520 - Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects Images such as mask layouts, signatures, and photographs are compared to identify similarities or dissimilarities in the images. Descriptions of the images use geometric shapes including lines, rectangles, and triangles to facilitate the comparisons and decrease comparison time and decrease stored data describing the shapes. Data for pixels in the ... 11/30/06 - 20060271907 - Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is ... 11/30/06 - 20060271906 - Centerline-based pinch/bridge detection A method for performing layout verification involves identifying feature centerlines in a mask layout, and then performing lithography simulation along the centerlines to generate a set of intensity distributions. At each local maxima or minima in the intensity distributions, further lithography simulation can be performed to determine an exposure pattern ... 11/30/06 - 20060271905 - Optical proximity correction using progressively smoothed mask shapes A method, program product and system is disclosed for performing optical proximity correction (OPC) wherein mask shapes are fragmented based on the effective image processing influence of neighboring shapes on the shape to be fragmented. Neighboring shapes are smoothed prior to determining their influence on the fragmentation of the shape ... 11/23/06 - 20060265686 - System for controlling an overlay, method for controlling overlay, and method for manufacturing a semiconductor device A system for controlling an overlay includes a processing data receiving module receiving a processing data string describing a name of an exposure process for a target layer and an original control set value of overlays between the target layer and underlying layers below the target layer; an inspection data ... 11/02/06 - 20060248499 - Apparatus and method for breaking up and merging polygons A method of modifying polygons in a data set mask-less or mask based optical projection lithography includes: 1) mapping the data set to a figure-of-demerit; 2) moving individual polygon edges to decrease the figure-of-demerit; and 3) disrupting the set of polygons to enable a further decrease in the figure-of-demerit, wherein ... 11/02/06 - 20060248498 - Apparatus and method for photomask design An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a ... 11/02/06 - 20060248497 - Apparatus and method for compensating a lithography projection tool An apparatus and method of compensating for lens imperfections in a projection lithography tool, includes extracting from a diffraction image created by the projection lithography tool a lens transmittance function, and then using the extracted lens transmittance function as a compensator in the lithography projection tool. Another preferred apparatus and ... 10/19/06 - 20060236299 - Mask creation with hierarchy management using cover cells A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to ... 10/19/06 - 20060236298 - Convergence technique for model-based optical and process correction Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping ... 10/19/06 - 20060236297 - Method and apparatus for assessing the quality of a process model One embodiment of the present invention provides a system that assesses the quality of a process model. During operation, the system receives a mask layout and additionally receives a process model that models the effects of one or more semiconductor manufacturing processes on the mask layout. Next, the system computes ... 09/21/06 - 20060212839 - Method and apparatus for modifying a layout to improve manufacturing robustness One embodiment of the present invention provides a system that modifies a layout to improve manufacturing robustness. During operation, the system receives a layout. The system then selects a segment in the layout. Next, the system determines a target location in the proximity of the segment where the value of ... 09/14/06 - 20060206854 - Assist feature placement using a process-sensitivity model One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial assist feature placement. An assist feature perturbation typically comprises a few simple ... 08/31/06 - 20060195815 - Exposure data generator and method thereof A plurality of patterns placed within an target region are classified by their placement positions, a pattern adjacent to each side of each pattern is searched for by using the classification results, and adjacent pattern information is obtained. Next, a back-scattering intensity at an evaluation point on a pattern is ... 08/24/06 - 20060190921 - Manufacturing method of semiconductor device A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second ... 08/24/06 - 20060190920 - Optical proximity correction performed with respect to limited area A method of performing optical proximity effect correction includes defining a partial area of an entire area of a mask pattern, the mask pattern including a real pattern and a dummy pattern, and performing optical proximity effect correction only with respect to the partial area. ... 08/24/06 - 20060190919 - Method of locating sub-resolution assist feature(s) A method of operating a computing system to determine reticle data. The reticle data is for completing a reticle for use in projecting an image to a semiconductor wafer. The method receives circuit design layer data comprising a desired circuit layer layout, and the layout comprises a plurality of lines. ... 08/24/06 - 20060190918 - System and process for manufacturing custom electronics by combining traditional electronics with printable electronics A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate is pre-provided with standard integrated circuits. The standard integrated circuits are pre-provided on the substrate in a conventional manner, such as by standard integrated circuit technologies, in many different packing technologies. The user designs ... 08/24/06 - 20060190917 - System and process for manufacturing application specific printable circuits (aspc's) and other custom electronic devices A system and process for manufacturing custom printed circuit boards on pre-provided substrates, wherein the substrate can be pre-provided with electronic devices. The electronic devices can be pre-provided on the substrate by direct printing, or in a more conventional manner, such as by standard integrated circuit technologies, in many different ... 08/24/06 - 20060190916 - Semiconductor substrate processing method and apparatus According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The method may include providing a semiconductor substrate having a surface and a plurality of features on the surface, each feature being positioned on the surface at a first ... 07/13/06 - 20060156270 - Method and apparatus for correcting 3d mask effects One embodiment of the present invention provides a system that improves lithography performance by correcting for 3D mask effects. During operation the system receives a mask layout that contains etched regions, called shifters, which can have a phase shift relative to other regions. Next, the system chooses a shifter in ... 06/22/06 - 20060136862 - Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product A pattern data verification method includes preparing exposure data related to a circuit pattern to be formed on a substrate, calculating a characteristic of an image of an exposure pattern on a resist film to be applied on the substrate, the exposure pattern corresponding to the exposure data, calculating a ... 06/22/06 - 20060136861 - Layout modification using multilayer-based constraints A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces ... 06/15/06 - 20060129968 - Effective proximity effect correction methodology Proximity effect correction has become a necessary step in the fabrication of integrated circuit in order to improve the pattern fidelity of current lithography processes. Current methodology is limited by data volume increase and correction inaccuracy due to extrapolation of the correction. The invention describes a methodology based on the ... 06/08/06 - 20060123381 - Data generating system, patterning data generating apparatus, method of generating patterning data and storage medium carrying patterning data In a data generating system, a basic pattern generating part (2331) generates patterning data having a basic pattern data block into which basic pattern CAD data is converted and a correct rule adding part (3332) adds a correct rule obtained from a database (3142) on the basis of a rule ... 06/08/06 - 20060123380 - Computer automated method for designing an integrated circuit, a computer automated system for designing an integrated circuit, and a method of manufacturing an integrated circuit A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one ... 05/18/06 - 20060107249 - Optimization of multiple feature lithography According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps each associated with a particular one of a plurality of circuit features. Each map maps an illumination field comprising a plurality of point sources and indicates, ... 05/04/06 - 20060095889 - Silicon tolerance specification using shapes as design intent markers Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping ... 04/13/06 - 20060080634 - Edge-based proximity correction One embodiment of the present invention provides a system that calculates an edge-based proximity correction which is applied to a region in the proximity of an evaluation point. During operation the system receives a layout. Next, the system decomposes polygons in the layout into edges. The system then computes the ... 04/06/06 - 20060075380 - Calculating etch proximity-correction using object-precision techniques One embodiment of the present invention provides a system that calculates etch proximity-correction during an OPC (Optical Proximity Correction) process. During operation, the system receives a layout for an integrated circuit. Next, the system selects a target point on an edge in the layout. The system then creates a list ... 04/06/06 - 20060075379 - Method and system for managing design corrections for optical and process effects based on feature tolerances A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects ... 03/30/06 - 20060070018 - Method for producing a mask layout avoiding imaging errors for a mask A final mask layout (20′) is produced by producing a provisional auxiliary mask layout in accordance with a predefined electrical circuit diagram and converting it into the final mask layout (20′) with the aid of an OPC method. Before carrying out the OPC method, with the provisional auxiliary mask layout ... 03/02/06 - 20060048091 - Method for correcting position-dependent distortions in patterning of integrated circuits A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the ... 03/02/06 - 20060048090 - Simulation of aerial images A method for generating a simulated aerial image of a mask projected by an optical system includes determining a coherence characteristic of the optical system. A coherent decomposition of the optical system is computed based on the coherence characteristic. The decomposition includes a series of expansion functions having angular and ... 03/02/06 - 20060048089 - System and method for simulating an aerial image A method for generating a simulated aerial image includes forming a reference aerial image of a first mask using an optical system, and capturing and processing the reference aerial image so as to generate a set of expansion functions representative of the optical system. The simulated aerial image of a ... 01/12/06 - 20060010417 - Apparatus, method and program product for suppressing waviness of features to be printed using photolithographic systems A method for minimizing rippling of features when imaged on a surface of a substrate using a mask. The method includes the steps of determining a deviation between a first representation of the design and a second representation of an image of the design at each of a plurality of ... 12/15/05 - 20050278686 - Fragmentation point and simulation site adjustment for resolution enhancement techniques A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image ... 12/08/05 - 20050273754 - Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a ... 12/08/05 - 20050273753 - Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes Computational models of a patterning process are described. Any one of these computational models can be implemented as computer-readable program code embodied in computer-readable media. The embodiments described herein explain techniques that can be used to adjust parameters of these models according to measurements, as well as how predictions made ... 11/17/05 - 20050257189 - Phase-shift lithography mapping method and apparatus For phase-shifting micro lithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first shifter polygon, identifying a set of target features that touch the first shifter polygon, and assigning ... 11/17/05 - 20050257188 - Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction ... 11/17/05 - 20050257187 - Fast and accurate optical proximity correction engine for incorporating long range flare effects A method is described for performing model-based optical proximity corrections on a mask layout used in an optical lithography process having a plurality of mask shapes. Model-based optical proximity correction is performed by computing the image intensity on selected evaluation points on the mask layout. The image intensity to be ... 10/20/05 - 20050235246 - Use of models in integrated circuit fabrication A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the ... 10/13/05 - 20050229148 - Model-based two-dimensional interpretation filtering Complex layout features, especially two-dimensional (2D) features such as jogs and corners, are more susceptible to photo-resist pinching and bridging, even with the use of optical proximity correction. These problems may arise due to unrealistic targets, e.g. square corners, thereby resulting in excessively aggressive correction in the vicinity of these ... 10/13/05 - 20050229147 - Test ket layout for precisely monitoring 3-foil lens aberration effects An H-shaped test key layout for exclusively monitoring 3-foil lens aberration effects during the fabrication of deep-trench capacitor memory devices is disclosed. The COMA lens aberration effect that used to occur along with the 3-foil lens aberration effect is now eliminated by this test key layout. ... 10/06/05 - 20050223350 - System for simplifying layout processing A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design ... 09/29/05 - 20050216878 - Long range corrections in integrated circuit layout designs A method and apparatus for compensating for flare intensity variations across an integrated circuit. A layout description for a physical layer of an integrated circuit or portion thereof is divided into a number of regions such as adjacent tiles. An estimate of the flare intensity in each region is determined. ... 09/22/05 - 20050210438 - Modification of an image of a pattern during an imaging process A method is provided for modifying an image of a pattern during a lithographic imaging process, where the pattern is arranged on a mask for imaging by a projection system on a surface, and the image is an image formed from the pattern by the projection system. In this method ... 09/15/05 - 20050204330 - Exposure pattern forming method and exposure pattern Disclosed is an exposure pattern forming method of forming an exposure pattern by correcting each pattern portion constituting a design pattern by a correction amount, which amount is previously prepared so as to correspond to both a line width of the pattern portion and a space width of a space ... 09/15/05 - 20050204329 - Methods and systems for designing electromagnetic wave filters and electromagnetic wave filters designed using same Methods and systems for designing electromagnetic wave filters and electromagnetic wave filters designed using the methods and systems are disclosed. In one method, functions are selected whose linear combination define the surface of a filter for producing a desired phase-encoded image. Free parameter values are selected for the function and ... 09/15/05 - 20050204328 - Method for verifying ret latent image sensitivity to mask manufacturing errors A method for verifying reticle enhancement technique latent image sensitivity to mask manufacturing errors. The method includes the steps of revising a polygon based on mask CD distributions to provide a virtual mask, imaging the virtual mask to obtain response function statistical parameters, and comparing the statistical parameters to design ... 09/08/05 - 20050198609 - Method and system for mask fabrication process control A mask fabrication system. The mask fabrication system contains a processing tool, a metrology tool, and a controller. The processing tool processes a mask. The metrology tool inspects the mask to obtain an inspection result. The controller generates a manufacturing model of the processing tool and calibrates the manufacturing model ... 09/01/05 - 20050193364 - Pattern forming method and semiconductor device manufactured by using said pattern forming method A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a ... 08/25/05 - 20050188342 - Method of determining the overlay accuracy of multiple patterns formed on a semiconductor wafer From a plurality of overlay targets formed with patterns on a test wafer, subsets are formed and for each overlay target contained in the subsets, the measurement results of overlay shifts are obtained. Mean shifts, residual data and ranges are calculated for each subset and compared with the 100% full ... 08/11/05 - 20050177811 - Method of setting process parameter and method of setting process parameter and/or design rule Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a ... 08/11/05 - 20050177810 - Lithographic process window optimization under complex constraints on edge placement A novel method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. ... 07/28/05 - 20050166176 - Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of ... 07/28/05 - 20050166175 - Alternating phase shift mask design for high performance circuitry A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of essentially parallel segments of critical width comprises creating essentially parallel alternating phase shifting regions aligned with the critical width segments and extending beyond ends of at least some ... 07/07/05 - 20050149902 - Eigen decomposition based opc model Model OPC is developed based on eigen decomposition of an aerial image expected to be produced by a mask pattern on a surface of a resist. With the eigen decomposition method the aerial image intensity distribution around a point (x, y) is accurately described in the model. A scalar approach ... 06/09/05 - 20050125765 - Method and apparatus for decomposing semiconductor device patterns into phase and chrome regions for chromeless phase lithography A method of generating a mask of use in printing a target pattern on a substrate. The method includes the steps of (a) determining a maximum width of features to be imaged on the substrate utilizing phase-structures formed in the mask; (b) identifying all features contained in the target pattern ... 06/09/05 - 20050125764 - Method for producing a mask layout avoiding imaging errors for a mask A method for producing a final mask layout avoids imaging errors. A provisional auxiliary mask layout that has been produced in accordance with a predetermined electrical circuit diagram is converted into the final mask layer with the aid of an OPC method. Before the OPC method is carried out, a ... 06/09/05 - 20050125763 - System and method for the online design of a reticle field layout Provided are a system and method for creating a reticle field layout (RFL). In one example, the method includes receiving information for a RFL design by a computer system directly from a user via a computer interface. The RFL design is automatically verified using predefined specification and design rules accessible ... 06/02/05 - 20050120328 - Method and system for increasing product yield by controlling lithography on the basis of electrical speed data The electrical performance of sub-devices is detected and the corresponding measurement data is used to control a lithography process so as to compensate for any type of process variations during a manufacturing sequence. ... ### FreshPatents.com Support |