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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Design Of Semiconductor Mask Design Of Semiconductor MaskDesign Of Semiconductor Mask patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070261016 - Masking techniques and templates for dense semiconductor fabrication A template comprising pitch multiplied and non-pitch multiplied features is configured for use in imprint lithography. On a first substrate, a first pattern is formed using pitch multiplication and a second pattern is formed using photolithography without pitch multiplication. The first pattern and the second pattern are transferred to a ... 10/25/07 - 20070250804 - Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one ... 10/18/07 - 20070245292 - Lithography simulation method, photomask manufacturing method, semiconductor device manufacturing method, and recording medium A lithography simulation method includes obtaining a mask transmission function from a mask layout, obtaining an optical image of the mask layout by using the mask transmission function, obtaining a function which is filtered by applying a predetermined function filter to the mask transmission function, and correcting the optical image ... 10/18/07 - 20070245291 - Incrementally resolved phase-shift conflicts in layouts for phase-shifted features Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to ... 10/18/07 - 20070245290 - Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to ... 09/27/07 - 20070226674 - System and method for semiconductor device fabrication using modeling System and Method for Semiconductor Device Fabrication Using Modeling System and method for using adjustment patterns as well as physical parameters as targets to control mask structure dimensions using optical proximity correction. A preferred embodiment includes defining targets based on definition rules and adjusting mask layer structures based on the ... 09/13/07 - 20070214448 - Orientation dependent shielding for use with dipole illumination techniques A method of printing a pattern having vertically oriented features and horizontally oriented features on a substrate utilizing dipole illumination, which includes the steps of: identifying background areas contained in the pattern; generating a vertical component mask comprising non-resolvable horizontally oriented features in the background areas; generating a horizontal component ... 09/06/07 - 20070209029 - Slm lithography: printing to below k1=.30 without previous opc processing Previously disclosed methods and devices are extended in this application by two-dimensional analysis of optical proximity interactions and by fashioning a computationally efficient kernel for rapid calculation of adjustments to be made. The computations can be made in realtime, whereby the use of OPC assist features can be reduced, with ... 08/23/07 - 20070198963 - Calculation system for inverse masks A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares ... 08/16/07 - 20070192756 - Method for time-evolving rectilinear contours representing photo masks Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 08/09/07 - 20070186206 - System, masks, and methods for photomasks optimized with approximate and accurate merit functions Photomask patterns are represented using contours defined by mask functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 07/19/07 - 20070168903 - Method for correcting a mask design layout A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction ... 06/21/07 - 20070143733 - Method of compensating photomask data for the effects of etch and lithography processes A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target ... 06/21/07 - 20070143732 - Pixelated masks for high resolution photolithography Some embodiments of the present invention include apparatuses and methods relating to pixelated masks for high resolution photolithography. ... 06/14/07 - 20070136716 - Method for time-evolving rectilinear contours representing photo masks Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 06/07/07 - 20070130560 - Method of determining photo mask, method of manufacturing semiconductor device, and computer program product A method of determining a photo mask, includes specifying a mask pattern for a photo mask for a first exposure apparatus, specifying a plurality of exposure conditions allowed to be set for a second exposure apparatus, predicting a projection image of the mask pattern to be projected on a substrate ... 06/07/07 - 20070130559 - Optical proximity correction on hardware or software platforms with graphical processing units Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute ... 06/07/07 - 20070130558 - Methods and systems for pattern generation based on multiple forms of design data In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write system. A pattern is generated based on fractured design data and the extracted properties. By preserving the design intent to the lithography write system, the ... 06/07/07 - 20070130557 - Approximating wafer intensity change to provide fast mask defect scoring To provide fast mask defect scoring, approximated wafer simulations (e.g. using one convolution) are performed on the defect inspection image and its corresponding reference inspection image. Using the approximated defect wafer image and the approximated reference wafer image generated by these approximated wafer simulations, a defect maximum intensity difference (MID) ... 05/31/07 - 20070124719 - Method of forming a mask pattern for a semiconductor device A method of forming a mask pattern from a design pattern. A method may effectively compensate for pattern distortion resulting from an optical proximity effect (OPE). A method may obtain a precise line width. A method includes a first mask design processing and a second mask design processing. ... 05/31/07 - 20070124718 - Mask manufacturing system, mask data creating method and manufacturing method of semiconductor device A mask manufacturing system and a mask data creating method reusing data for processing information and environment in the past to reduce a photomask developing period, and a manufacturing method of a semiconductor device are disclosed. According to one aspect of the present invention, it is provided a mask manufacturing ... 04/12/07 - 20070083846 - Optimized modules' proximity correction A method comprising dissecting a photomask pattern layout into a plurality of segments, each segment having at least one evaluation point, applying a rule-based MPC to the photomask pattern layout and generating a rule-based MPC result, and applying a model-based MPC to the plurality of segments of the photomask pattern ... 04/05/07 - 20070079277 - Method and system for analyzing the quality of an opc mask The present invention provides a method and system for analyzing the quality of an OPC mask. The method includes receiving a target layer from a target design, receiving an OPC mask layer from the OPC mask. The method also includes classifying each cell of at least one of the target ... 03/08/07 - 20070055953 - Distributed hierarchical partitioning framework for verifying a simulated wafer image A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell ... 03/01/07 - 20070050748 - Method and algorithm for random half pitched interconnect layout with constant spacing An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines ... 02/08/07 - 20070033566 - Storage management unit to configure zoning, lun masking, access controls, or other storage area network parameters Some of the embodiments disclosed are systems and methods of configuring an access masking structure which include, but are not limited to, selecting at least one computer to participate in an access restriction set, selecting at least one storage unit to participate in the access restriction set, disabling all non-selected ... 02/01/07 - 20070028205 - Data processing method in semiconductor device, program of the same, and manufacturing method of semiconductor device A design data processing method in a semiconductor device includes extracting, from design data, a graphic in which there exist a first wiring and a second wiring which is orthogonal to the first wiring, and changing a portion where the first wiring is orthogonal to the second wiring to make ... 01/11/07 - 20070011645 - Method for time-evolving rectilinear contours representing photo masks Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 01/11/07 - 20070011644 - Optimized photomasks for photolithography Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to ... 01/04/07 - 20070006115 - Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a ... 01/04/07 - 20070006114 - Method and system for incorporation of patterns and design rule checking Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successful, and “known bad” patterns, which chip fabricators know to be unsuccessful. ... 01/04/07 - 20070006113 - Determining an optimizaton for generating a pixelated photolithography mask with high resolution imaging capability A pixelated photolithography mask is optimized for high resolution microelectronic processing. In one embodiment, the invention includes synthesizing a pixelated photolithography mask, applying a pixel flipping function to the mask, comparing the resulting mask to a desired result, and synthesizing an optimized pixelated binary photolithography mask using the function. ... 12/21/06 - 20060288325 - Method and apparatus for measuring dimension of a pattern formed on a semiconductor wafer In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating ... 12/07/06 - 20060277519 - System and method for optical proximity correction A method of optical proximity correction is described. The method includes selecting all islands, increasing the size of each said island. The facing sides of each island is pulled back equally if island to island spacing is insufficient between two islands. A further step of pulling back equally the facing ... 11/16/06 - 20060259893 - Photomask, photomask set, photomask design method, and photomask set design method There is provided a photomask in which influences of line-end shortening and corner rounding of a gate pattern are suppressed. A block having a plurality of gate electrodes are formed in the photomask, all of the longitudinal directions of the plurality of gate electrodes in each block are equal to ... 11/09/06 - 20060253828 - Structure and methodology for fabrication and inspection of photomasks A photomask, method of designing, of fabricating, of designing, a method of inspecting and a system for designing the photomask. The photomask, includes: a cell region, the cell region comprising one or more chip regions, each chip region comprising a pattern of opaque and clear sub-regions corresponding to features of ... 11/02/06 - 20060248495 - Method and apparatus of model-based photomask synthesis An apparatus and method for improving image quality in a photolithographic process includes calculating a figure-of-demerit for a photolithographic mask function and then adjusting said photolithographic mask function to reduce the figure of demerit. ... 10/26/06 - 20060242619 - System and method for providing defect printability analysis of photolithographic masks with job-based automation Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a ... 10/26/06 - 20060242618 - Lithographic simulations using graphical processing units Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography ... 10/19/06 - 20060236295 - Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems Provided is a method and system for developing a lithographic mask layout. The lithographic mask layout is adapted for configuring an array of micro-mirrors in a maskless lithography system. The method includes generating an ideal mask layout representative of image characteristics associated with a desired image. Next, an equivalent mask ... 10/19/06 - 20060236294 - Computer-implemented methods for detecting defects in reticle design data Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The ... 10/05/06 - 20060225025 - Dual phase shift photolithography masks for logic patterning A pair of phase shift photolithography masks and a process for deriving them is described. In one embodiment, the invention includes deriving a complex electric field estimate for an intended pattern to be produced by phase shift photolithography masks, optimizing the complex electric field estimates, generating a first phase shift ... 10/05/06 - 20060225024 - Modification of pixelated photolithography masks based on electric fields Faster synthesis of photolithography mask modifications is described. In one embodiment, the invention includes synthesizing a first binary photolithography mask, developing perturbations to an estimated electric field generated by the first mask in use, and synthesizing a second binary photolithography mask by applying the perturbations to the first mask. ... 10/05/06 - 20060225023 - Method of adding fabrication monitors to integrated circuit chips An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions ... 09/28/06 - 20060218520 - Mask data preparation The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan ... 09/14/06 - 20060206853 - Method of producing mask inspection data, method of manufacturing a photo mask and method of manufacturing a semiconductor device There is disclosed a method of producing mask inspection data, including preparing design data of a semiconductor device preparing a lithography condition relevant to a lithography process for transferring a mask pattern formed on a photo mask onto a wafer, preparing a wafer processing condition relevant to wafer processing using ... 09/14/06 - 20060206852 - System and method for designing semiconductor photomasks A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor ... 09/14/06 - 20060206851 - Determning lithographic parameters to optimise a process window For determining best process variables (E, F, W) setting that provide optimum process window for a lithographic process for printing features having critical dimensions (CD) use is made of an overall performance characterizing parameter (Cpk) and of an analytical model, which describes CD data as a function of process parameters, ... 09/07/06 - 20060200790 - Model-based sraf insertion A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution assist features (SRAFs) is then defined to approximate ... 09/07/06 - 20060200789 - Connectivity verification of ic (integrated circuit) mask layout database versus ic schematic; lvs check, (lvs: ic layout versus ic schematic) via the internet method and computer software This paper describes an EDA (Electronic Data Automation) method and computer software invention for connectivity verification of IC mask Layout database versus IC Schematic; LVS Check (LVS: IC Layout versus IC Schematic) over the internet. The technique takes advantage of a unique algorithm to check the mask layout database connectivity, ... 08/31/06 - 20060195814 - System and method for using mpw integration service on demand A system for multi-project wafer service is provided. The system contains integrator and designer interfaces, an account managing device, a mask tooling information processor, a mask database checking device, and a mask tooling information convertor. The integrator and the designer interfaces provide first and second users with access to the ... 08/31/06 - 20060195813 - Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an integrated circuit. When the connectivity of elements of the functional block need to be changed later, the dummy stacks enable masks, which would otherwise need to be ... 08/24/06 - 20060190915 - Machine specific and machine group correction of masks based on machine subsystem performance parameters Determining corrections for a mask used in photolithography includes assembling characteristics of a mask design and an as-drawn specification into a virtual reticle. Assembling characteristics of machine subsystem parameters into a virtual wafer. Emulating machine performance on the virtual reticle and virtual wafer and accumulating the results in an updated ... 08/24/06 - 20060190914 - Method and apparatus for identifying a problem edge in a mask layout using an edge-detecting process-sensitivity model One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or ... 08/24/06 - 20060190913 - Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one ... 08/24/06 - 20060190912 - Method and apparatus for identifying a manufacturing problem area in a layout using a process-sensitivity model One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal (e.g., optimal) process conditions. The system also creates one ... 08/24/06 - 20060190911 - Translation generation for a mask pattern Generation of one or more translations is described. The generated translations may be applied to a mask pattern so that the pattern may be moved to cover one or more mask defects in part or in totality. ... 07/13/06 - 20060156269 - Selecting data to verify in hardware device model simulation test generation Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands ... 07/06/06 - 20060150139 - Circuit element function matching despite auto-generated dummy shapes Methods, systems, program products are disclosed that control placement of dummy shapes about sensitive circuit elements such that the dummy shapes are at least substantially similar for each circuit element even though the dummy shapes are auto-generated. In one embodiment, the invention includes providing dummy shape pattern pitch information to ... 06/29/06 - 20060143590 - Method and apparatus for determining a proximity correction using a visible area model One embodiment of the present invention provides a system that determines a proximity correction for an integrated circuit layout. During operation, the system receives a layout. Next, the system receives an evaluation point within the layout. The system then determines a visible area associated with the evaluation point. Next, the ... 06/29/06 - 20060143589 - Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based ... 06/15/06 - 20060129967 - System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects A system for generating mask data includes an extracting module extracting a block necessary to correct process proximity effects as a wide correction area from a plurality of blocks by comparing parameter, a wide correction data generator generating wide correction data to make the correction applied to the wide correction ... 06/15/06 - 20060129966 - Opc edge correction based on a smoothed mask design A method and system is provided for performing edge correction on a mask design. Aspects of the invention include initially fragmenting boundaries of the mask design for optical proximity correction, whereby edge segments of the boundaries are moved by a distance value; interpreting the moved edge segments by defining a ... 06/08/06 - 20060123379 - Correcting a mask pattern by selectively updating the positions of specific segments Correcting a mask pattern includes accessing the mask pattern segmented into segments. An attribute value is established for each segment, where the attribute value for a segment describes an attribute of the segment. The following is repeated for one or more of the attribute values to generate a corrected mask ... 06/01/06 - 20060117293 - Method for designing an overlay mark Precision in scatterometry measurements is improved by designing the reticle, or the target grating formed by the reticle, for greater overlay measurement sensitivity. Parameters of the structure and material of the substrate are first determined. These parameters may include the material composition, thickness, and sidewall angles of the sample substrate. ... 06/01/06 - 20060117292 - Automatic recognition of geometric points in a target ic design for opc mask quality calculation A method and system is provided for automatically recognizing geometric points of features in a target design for OPC mask quality calculation. For each feature in the target design, x, y points comprising the feature are traversed and each neighboring pair of points is connected to define respective segments, wherein ... 05/18/06 - 20060107248 - Generating mask patterns for alternating phase-shift mask lithography A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout ... 05/11/06 - 20060101370 - Method for improving optical proximity correction A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant process model term to form a ... 05/04/06 - 20060095887 - Process window-based correction for photolithography masks A correction for photolithography masks used in semiconductor and micro electromechanical systems is described. The correction is based on process windows. In one example, the invention includes evaluating a segment of an idealized photolithography mask at a plurality of different possible process variable values to estimate a corresponding plurality of ... 04/13/06 - 20060080633 - Method for performing full-chip manufacturing reliability checking and correction A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with ... 04/06/06 - 20060075377 - Method, program product and apparatus for model based scattering bar placement for enhanced depth of focus in quarter-wavelength lithography A method of generating a mask having optical proximity correction features. The method includes the steps of: (a) obtaining a desired target pattern having features to be imaged on a substrate; (b) determining a first focus setting to be utilized when imaging the mask; (c) determining a first interference map ... 04/06/06 - 20060075376 - System and method for phase shift assignment A semiconductor design is provided having at least one feature at one of a line end and a line junction, and phase regions. At least one cut line is added to at least one of such features at line ends and such features at line junctions. Phases are assigned to ... 02/09/06 - 20060031809 - Method for interlayer and yield based optical proximity correction An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. In comparing the edge points on the predicted layout pattern with ... 02/02/06 - 20060026550 - Mask for fabricating semiconductor devices and method for designing the same The present method for designing a mask includes calculating the maximum layout number of patterns on a mask substrate, calculating a first mask cost and a second mask cost, calculating the total cost for fabricating a predetermined number of wafers using the first mask and the second mask, and selecting ... 02/02/06 - 20060026549 - Method and system for conducting an online transaction of multi-project wafer service An online multi-project wafer method comprises providing, via an online interface, a template, receiving, via the online interface, at least two sets of completed templates each having information descriptive of an integrated circuit, checking the received at least two sets of completed templates, providing feedback for respective ones of the ... 01/12/06 - 20060010416 - System and method for searching for patterns of semiconductor wafer features in semiconductor wafer data A system for searching for patterns of semiconductor wafer features for use in silicon manufacturing and device fabrication processes, the system including: a data acquisition system 00 for acquiring scan data from differing types of semiconductor wafer scanning tools such as wafer dimensional tools 10, wafer inspection tools 12, and ... 12/29/05 - 20050289500 - Method for planning layout for lsi pattern, method for forming lsi pattern and method for generating mask data for lsi First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to ... 12/15/05 - 20050278685 - Matrix optical process correction A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more ... 12/01/05 - 20050268272 - Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (opc) purposes The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ... 11/24/05 - 20050262468 - Designing method and device for phase shift mask The work load spent on designing a trench-type, Levenson-type phase shift mask is lightened and the working time for the designing process is shortened. A pattern 11, having a plurality of apertures, is designed by means of a designing tool 10. In a database 30 are prepared optimal functions that ... 11/24/05 - 20050262467 - Method and system for utilizing an isofocal contour to perform optical and process corrections A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) mask design is disclosed. The system and method of the present invention includes identifying a first feature in the mask design, generating an isofocal contour for the identified feature, and utilizing the isofocal contour to ... 11/24/05 - 20050262466 - Method for modifying design data for the production of a component and corresponding units A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are ascertained and compared. Depending on the comparison result, ... 11/10/05 - 20050251781 - Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not ... 10/27/05 - 20050240895 - Method of emulation of lithographic projection tools Techniques for producing emulations of lithographic tools and processes using virtual wafers and lithographic libraries are described. Emulating a lithographic projection imaging machine includes determining characteristics of the imaging machine, of a reticle used in the imaging machine, and of layer specific processes. Then performing emulation on a virtual wafer ... 10/20/05 - 20050235245 - Design pattern correction method and mask pattern producing method There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to ... 10/13/05 - 20050229145 - Method and system for chrome cut-out regions on a reticle A method and system for chrome cut-out regions on a reticle is described. The method includes determining a location of one or more regions on a reticle that come in contact with a reticle handling, storage, or support surface and generating a pattern to be written on the reticle, where ... 10/13/05 - 20050229144 - Yield profile manipulator A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the ... 10/06/05 - 20050223349 - Photomask manufacturing support system A drawing data inputting/interpreting section of a data processing device reads in hierarchical structured drawing data from a first memory device and stores interpreted drawing data information extracted as graphic information in a second memory device. A data analysis section reads in the interpreted drawing data information, analyzes information necessary ... 09/29/05 - 20050216877 - Method and system for context-specific mask writing A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask. ... 09/22/05 - 20050210437 - Method of manufacturing reliability checking and verification for lithography process using a calibrated eigen decomposition model A method for modeling a photolithography process which includes the steps of generating a calibrated model of the photolithography process capable of estimating an image to be produced by the photolithography process when utilized to image a mask pattern containing a plurality features; and determining an operational window of the ... 09/22/05 - 20050210436 - Alternating phase-shift mask rule compliant ic design A system, method and program product that implement a design object that automatically provides compliance to alternating phase shifted mask (altPSM) rules are disclosed. The invention implements a design object that is used during layout to indicate a phase-shiftable design feature in the layout. Each design object includes a base ... 09/15/05 - 20050204327 - Layout data verification method, mask pattern verification method and circuit operation verification method In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image ... 09/01/05 - 20050193363 - Method of ic fabrication, ic mask fabrication and program product therefor A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected ... 09/01/05 - 20050193362 - Multi-layer overlay measurement and correction technique for ic manufacturing A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error ... 09/01/05 - 20050193361 - System and method for presentation of wireless application data using repetitive ui layouts A Repetitive Layout scheme is provided that operates on a collection of data objects, such that each data object accords to the same data object definition (data model) expressed in a structured definition language. The Repetitive Layout consists of one UI section repeated for every object in the collection. Each ... 08/25/05 - 20050188341 - Mask data correction method, photomask manufacturing method, computer program, optical image prediction method, resist pattern shape prediction method, and semiconductor device manufacturing method According to an aspect of the invention, there is provided a mask data correction method used when forming a photomask used in a photolithography process, comprising correcting mask data on the basis of simulation performed by using information including nonuniformity of an illumination luminance distribution in an exposure apparatus which ... 08/18/05 - 20050183056 - Simulator of lithography tool, simulation method, and computer program product for simulator A simulator of a lithography tool includes a correcting parameter memory storing a correcting scaling value to correct a focus error of a projection optical system in the lithography tool and a correcting bias to correct a critical dimension error gene rated in the lithography tool. A model simulation engine ... 08/11/05 - 20050177809 - Correcting 3d effects in phase shifting masks using sub-resolution features Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM ... 08/04/05 - 20050172255 - Pattern inspection apparatus A pattern inspection apparatus determines a difference of the measured dislocation of respective alignment marks of an opaque pattern and a phase shifting pattern (measurement difference), in addition to a difference between the both alignment mark positions in design (design difference). A difference between the measurement difference and the design ... 07/28/05 - 20050166173 - Design data format and hierarchy management for processing Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the ... 07/28/05 - 20050166172 - Critical pattern extracting method, critical pattern extracting program, and method of manufacturing semiconductor device According to a aspect of the present invention, there is provided a critical pattern extracting method which extracts critical patterns from mask data for manufacturing a photomask used in a lithography step, comprising at least: extracting mask data of a peripheral region within a predetermined range from an interested portion ... 07/28/05 - 20050166171 - Method and system for controlling the quality of a reticle A method and system are presented for use in controlling the quality of a reticle. The method includes processing and analyzing reference data and test data, and generating output data indicative of the current condition of the reticle. The reference data is indicative of at least a portion of a ... 07/21/05 - 20050160394 - Driven inspection or measurement Design driven inspection/metrology methods and apparatus are provided. A recipe is a set of instructions including wafer processing parameters, inspection parameters, or control parameters for telling an inspection/metrology system how to inspect/measure a wafer. Design data is imported into a recipe extraction system that recognizes instances of target structures and ... 07/21/05 - 20050160393 - Method of automatically correcting mask pattern data and program for the same A method of automatically correcting mask pattern data includes steps (a) to (d). Here, in this method, the mask pattern data are for producing photo masks used in manufacturing processes of a semiconductor integrated circuit where cells including dummy cells are placed on a semiconductor chip. The step (a) is ... 07/07/05 - 20050149900 - Feature optimization using enhanced interference mapping lithography Disclosed concepts include a method of, and program product for, optimizing an intensity profile of a pattern to be formed in a surface of a substrate relative to a given mask using an optical system. Steps include mathematically representing resolvable feature(s) from the given mask, generating a mathematical expression, an ... 07/07/05 - 20050149899 - System and method for multi-project wafer shuttle service A system and method for MPW shuttle service. The system includes at least a first MPW shuttle reserving for a first group of device designs, a second MPW shuttle reserving for a second group of device designs, and a checking unit. The checking unit determines whether mask data for the ... 06/23/05 - 20050138596 - Gradient method of mask edge correction The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function. ... 06/16/05 - 20050132322 - Mask evaluating method, mask evaluating system, method of manufacturing mask and computer program product A photomask evaluating method comprises calculating a killer defect rate function with respect to a simulative defect pattern including a pattern of photomask and a plurality of defects, the killer defect rate function representing a killer defect rate of the simulative defect pattern with respect to a desired density of ... 06/02/05 - 20050120326 - Method for producing for a mask a mask layout which avoids aberrations A method for producing for a mask a mask layout which avoids aberrations in which a provisional auxiliary mask layout produced, in particular in accordance with a prescribed electrical circuit diagram is converted into the mask layout with the aid of an OPC method. At least two different OPC variants ... 06/02/05 - 20050120325 - Method of verifying corrected photomask-pattern results and device for the same A method of verifying photomask-pattern-correction results includes steps of cutting away photomask patterns of a region to be subjected to correction, forming photoresist models used for execution of an optical-proximity-effect-correction operation, executing the optical-proximity-effect-correction operation of the photomask patterns with respect to the photoresist models, executing an exposure simulation for ... ### FreshPatents.com Support |