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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Logical Circuit Synthesizer Logical Circuit SynthesizerLogical Circuit Synthesizer patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070261015 - Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The ... 10/11/07 - 20070240094 - Partially gated mux-latch keeper Embodiments related to multiplexer latches (mux-latches) are presented herein. ... 10/04/07 - 20070234268 - Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, ... 09/20/07 - 20070220476 - Multilayer opc for design aware manufacturing A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper ... 09/13/07 - 20070214447 - Behavioral synthesis apparatus, behavioral synthesis method, method for manufacturing digital circuit, behavioral synthesis control program and computer-readable recording medium An A behavioral synthesis apparatus according to the present invention for performing a computer-automated synthesis of a circuit description of a register transfer level from a behavioral description describing a process operation of a circuit, wherein an output of a target computing unit is input to a plurality of subsequent ... 08/09/07 - 20070186204 - Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit ... 07/26/07 - 20070174806 - Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of ... 07/26/07 - 20070174805 - Debugging system for gate level ic designs A register transfer level (RTL) IC design describing a IC as comprising a plurality of logic blocks communicating via signals and using a high level language to describe the logic blocks according to the logical relationships between signals they receive and signals they generate. A computer-aided synthesizer processes an RTL ... 07/26/07 - 20070174804 - Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis The device for logic synthesis comprises: means to store node table 8 storing Binary Decision Diagram for Characteristic Function (BDD_for_CF) of the characteristic function χ(X, Y) of the multiple-output logic function f(X), means to store LUTs 16, means to reduce by shorting 11 partitioning BDD_for_CF into the subgraphs B0 and ... 06/21/07 - 20070143731 - Method and program for supporting register-transfer-level design of semiconductor integrated circuit A method for supporting the register-transfer-level (RTL) design of a semiconductor integrated circuit, includes reading an RTL description related to the semiconductor integrated circuit into a first memory, the RTL description including a description of a compound block containing a mixture of combinational and non-combinational circuits, analyzing the RTL description, ... 06/07/07 - 20070130556 - Method and apparatus for generating technology independent delays A method for generating an integrated circuit (IC) is provided wherein signal delays are transferable across two synthesis libraries where each library is associated with a different IC fabrication process. The method initiates with describing an IC design through a hardware description language (HDL). The method includes identifying logic signal ... 05/31/07 - 20070124717 - Method and program product for protecting information in eda tool design views Sensitive circuit design information in HDL Interface Logic Models such as module names and structures within certain EDA tool design views is eliminated by substituting selected instance and net names with unrelated unique identifiers prior to transferring the design views as part of a simulation model of a circuit design, ... 05/31/07 - 20070124716 - Method for generalizing design attributes in a design capture environment A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a ... 04/26/07 - 20070094633 - Method and system for mapping netlist of integrated circuit to design The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the ... 04/12/07 - 20070083845 - Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of asic and programmable logic device A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal ... 04/12/07 - 20070083844 - Logic circuit design support apparatus, and logic circuit design support method employing this apparatus A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and ... 04/12/07 - 20070083843 - Method, system and program product for providing a configuration specification language supporting error checking dials A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated. The configuration entities including an Error checking Dial (EDial) having a plurality of input latches within the digital design and a plurality ... 03/29/07 - 20070074141 - Simulation apparatus and simulation method According to an aspect of the invention, a simulation apparatus includes: a computer configured to execute a program which is formed as an operating description having no temporal restriction; and a programmable circuit configured to be on which a designing object circuit configured to perform a cycle operation is mounted. ... 03/01/07 - 20070050747 - Automatic power grid synthesis method and computer readable recording medium for storing program thereof An automatic power grid synthesis method and a computer readable recording medium for storing a program thereof for synthesizing power grid in a circuit area are provided. The circuit area has at least one power consuming module therein and at least one power pin disposed around the circuit area. The ... 02/01/07 - 20070028204 - Method and program for high-level synthesis, and method for verifying a gate network list using the high-level synthesis method A method for high-level synthesis includes extracting difference information of a first and a second behavioral description, generating a first register transfer level description from the first behavioral description while generating mapping information of the first behavioral description and the first register transfer level description, modifying the first register transfer ... 02/01/07 - 20070028203 - Apparatus and method for creating function verification description, and computer-readable recording medium in which program for creating function verification description is recorded To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the ... 01/18/07 - 20070016885 - Logic-synthesis method and logic synthesizer The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a ... 01/11/07 - 20070011643 - Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first ... 01/11/07 - 20070011642 - Application specific configurable logic ip An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, ... 01/04/07 - 20070006112 - Hierarchical presentation techniques for a design tool A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. ... 12/28/06 - 20060294491 - Methods for creating primitive constructed standard cells A high-level logic description is developed based on a non-primitive-based standard cell. library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic ... 12/14/06 - 20060282813 - Development system for an integrated circuit having standardized hardware objects Embodiments of the invention include a system for integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of ... 12/07/06 - 20060277518 - High order synthesizing method and high order synthesizing apparatus A signal in a hardware description corresponding to a variable or an expression in an operation description is identified so that a tracing description for hardware description for obtaining a transition history of a signal in the hardware description corresponding to a tracing object in the operation description is generated. ... 11/30/06 - 20060271904 - Method for abstraction of manufacturing test access and control ports to support automated rtl manufacturing test insertion flow for reusable modules A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the ... 11/23/06 - 20060265685 - Method and apparatus for automated synthesis of multi-channel circuits Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific ... 11/02/06 - 20060248494 - Method and system for parametric reduction of sequential designs A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut ... 10/26/06 - 20060242617 - Automatic generation of streaming processor architectures A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a ... 10/12/06 - 20060230377 - Computer-based tool and method for designing an electronic circuit and related system A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of ... 10/05/06 - 20060225022 - Method, apparatus and program for determining the relationship of correspondence between register transfer level description and behavioral description The relationship of correspondence between the RTL description and the behavioral description is extracted with ease. A behavioral synthesis device analyzes how the scheduling, preparation of a control data flow graph and the sharing of arithmetic processing units and registers are carried out. The behavioral synthesis device then formulates a ... 09/07/06 - 20060200788 - Method for describing and deploying design platform sets A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design platform descriptions provide design information ... 08/31/06 - 20060195812 - Designing system and method for designing a system lsi A method for designing a system LSI includes the steps of dividing an algorithmic description (D1) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior synthesis to create an RTL description ((D5) and a simulation description (D6), examining the circuit scale of the system ... 08/24/06 - 20060190910 - Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs A method is disclosed of associating a mapping function with a configuration construct of a digital design defined by one or more hardware description language (HDL) files. According to the method, in the HDL files, a configuration latch is specified within a design entity forming at least a portion of ... 08/24/06 - 20060190909 - Method for designing a system lsi A method for designing a system LSI includes the step of defining, for each of instructions of the processor, a behavior function description and an instruction description specifying the behavior function description, and the step of synthesizing the instructions by behavior synthesis to define the processor. The behavior function description ... 08/24/06 - 20060190908 - Coding of fpga and standard cell logic in a tiling structure A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, ... 08/24/06 - 20060190907 - Methods and apparatus for implementing parameterizable processors and peripherals Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically ... 08/24/06 - 20060190906 - Efficient method for mapping a logic design on field programmable gate arrays An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maximum value among the compensated square grids for reducing ... 08/24/06 - 20060190905 - System for designing re-programmable digital hardware platforms A digital design system and method are provided for re-programmable hardware platforms, such as field programmable gate arrays (FPGAs) and other re-programmable system designs. The design system and method bridge the gap between what has previously been a development and prototyping platform used during the design phase of an electronic ... 07/20/06 - 20060161877 - Device and method for data-processing A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions ... 07/13/06 - 20060156268 - Circuit design platform The circuit design platform of this invention comprises: a portal provided with a network platform to install functional modules and to allow users to utilize said functional modules after login; a circuit design tool module to connect at least one circuit design software and to generate a circuit design descriptive ... 06/29/06 - 20060143588 - Video processing architecture definition by function graph methodology A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource ... 06/29/06 - 20060143587 - Method and device for synthesising an electrical architecture The invention relates to a method of synthesising an electrical or electronic architecture of at least one part of a product comprising electrical wires and electrical and electronic components, such as sensors, actuators and computing devices. The inventive method comprises the following steps: the geometry of the product, which is ... 06/22/06 - 20060136860 - Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies Methods and apparatus are described that allow an integrated circuit designer to design integrated circuits for more than one process technology using a single master design environment. The master design environment is achieved, in part, by the creation of a centralized master database that comprises device models belonging to more ... 06/22/06 - 20060136859 - Method to unate a design for improved synthesizable domino logic flow A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of ... 06/08/06 - 20060123378 - Method, system, and software product for using synthesizable semiconductor intellectual property in self-documenting electronic extended package A method of synthesizing custom semiconductor circuits from an electronically editable datasheet of configurations and specifications for a functional component, by editing the parameters of the datasheet, checking for validity and consistency within said electronically editable datasheet, building a database of desired constraints and configurations, generating a plurality of files ... 04/20/06 - 20060085782 - Method for optimizing integrated circuit device design and service Improved analysis and refinement of integrated circuit device design and other programs is facilitated by methods in which an original program is partitioned into subprograms representing valid computational paths; each subprogram is refined when cyclic dependencies are found to exist between the variables; computational paths whose over-approximated reachable states are ... 04/06/06 - 20060075375 - Technology dependent transformations for cmos in digital design synthesis The present invention pertains to automated technology dependent transformations for CMOS digital design synthesis resulting in a combination of CMOS interconnected standard-cells from a target CMOS library being mapped and transistor-level representation for all or portion of the input design specification, the transistor level type and portion or portions to ... 03/30/06 - 20060070017 - Signal processing system A signal processing system comprises multiple signal processors, each having functional blocks. A control circuit selects one of the signal processors as a target processor, and configures an inspection circuit having equivalent functions to the target processor in a reconfigurable circuit, and retrieves input/output data from each functional block of ... 03/09/06 - 20060053405 - Integrated circuit design method A design method for designing an integrated circuit (IC) and a corresponding integrated circuit design tool are presented. An IC design having a plurality of building blocks (121-129) being interconnected by a plurality of interconnection wires (131-139) is represented by a two-dimensional representation (200) mimicking the positions of the building ... 02/09/06 - 20060031808 - System and method for creating timing constraint information A method of creating a timing constraint information which provides a timing constraint value of a cell, includes: (a) a processor setting a predetermined range including the timing constraint value as a scope; (b) the processor executing a simulation by using a preliminary timing constraint value within the scope to ... 02/02/06 - 20060026548 - Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, ... 12/29/05 - 20050289499 - High level synthesis method for semiconductor integrated circuit A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes ... 12/29/05 - 20050289498 - Processing and verifying retimed sequential elements in a circuit design Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis ... 12/15/05 - 20050278684 - Merging of infrastructure within a development environment A development environment includes a graphical design tool and a build agent. The graphical design tool allows a designer to design a primary logic component of a circuit. The graphical design tool generates modules using a hardware description language to represent the primary logic component of the circuit. The modules ... 12/15/05 - 20050278683 - Method, system and program product for specifying and using register entities to configure a simulated or physical digital system In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first ... 12/15/05 - 20050278682 - Determining hardware parameters specified when configurable ip is synthesized An attribute of a hardware feature to be customized in a soft core is parameterized so that a value received from a user can be used to generate a description of a circuit containing the customized hardware feature. The generated description also describes, in accordance with the invention, a register ... 12/08/05 - 20050273752 - Optimization of memory accesses in a circuit design Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and ... 12/08/05 - 20050273751 - Method of generating multiple hardware description language configurations for a phase locked loop from a single genetic model for integrated circuit design A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration ... 12/01/05 - 20050268271 - Loop manipulation in a behavioral synthesis tool Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent ... 11/24/05 - 20050262465 - Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a ... 11/17/05 - 20050257186 - Operation system for programmable hardware The proposed software-controlled FPGA system and method provides an operating system which controls partial reconfiguration of hardware logic blocks having equivalent properties as a standard software operating system. Said hardware control operating system enables to adjust compatible hardware logic blocks according to current running applications and attached hardware devices. The ... 11/10/05 - 20050251780 - Method for generating timing constraints of logic circuit In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these ... 11/10/05 - 20050251779 - Modeling metastability in circuit design A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise ... 10/20/05 - 20050235244 - Process and apparatus for characterizing intellectual property for integration into an ic platform environment A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are ... 10/13/05 - 20050229143 - System and method for implementing multiple instantiated configurable peripherals in a circuit design A method for structuring hardware description language code characterizes a peripheral design so as to facilitate multiple use of the code with different peripheral design configurations in a chip. The code provides one or more configuration options for the peripheral design in a configuration section of the hardware description language ... 09/08/05 - 20050198607 - Method for selecting and/or producing automation hardware A method for selecting and/or producing automation hardware which is appropriate or necessary for controlling and/or monitoring a technical process to be automated (10) according to an automation solution is provided. The method includes developing the description of the automation solution, analyzing this description with an analysis tool (20) and ... 09/08/05 - 20050198606 - Compilation of remote procedure calls between a timed hdl model on a reconfigurable hardware platform and an untimed model on a sequential computing platform A system is described for managing interaction between an untimed HAL portion and a timed HDL portion of the testbench, wherein the timed portion is embodied on an emulator and the un-timed portion executes on a workstation. Repeatability of verification results may be achieved even though the HAL portion and ... 09/01/05 - 20050193360 - Circuit design support system, circuit design support method, and program A computer program product, in a computer readable medium, including computer program instructions thereon which when executed by a computer display information on a circuit information described according to each design level in circuit design, the computer program instructions implementing a method comprising: acquiring behavior level description information in which ... 09/01/05 - 20050193359 - Method and apparatus for designing circuits using high-level synthesis A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase ... 07/21/05 - 20050160392 - System & method for asynchronous logic synthesis from high-level synchronous descriptions A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior. ... 07/07/05 - 20050149898 - Method and apparatus for managing the configuration and functionality of a semiconductor design A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use ... 07/07/05 - 20050149897 - Hardware/software co-verification method A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and ... 06/30/05 - 20050144585 - Method and system for hardware accelerated verification of digital circuit design and its testbench A system and method is presented for synthesizing both a design under test (DUT) and its test environment (i.e., the testbench for the DUT), into an equivalent structural model suitable for execution on a reconfigurable hardware platform. This may be achieved without any change in the existing verification methodology. Behavioral ... 06/23/05 - 20050138595 - System and method for mapping logical components to physical locations in an integrated circuit design environment A system and method for mapping IP components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is ... 06/23/05 - 20050138594 - Mask creation with hierarchy management using cover cells A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to ... 06/16/05 - 20050132321 - Method and apparatus for designing an integrated circuit using a mask-programmable fabric One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable ... 06/16/05 - 20050132320 - Framework for hierarchical vlsi design A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on ... 06/09/05 - 20050125762 - High level synthesis method and high level synthesis apparatus First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of ... 06/09/05 - 20050125761 - System and method for topology selection to minimize leakage power during synthesis A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology ... 06/02/05 - 20050120324 - Integrated circuit designing support apparatus and method for the same An integrated circuit designing support apparatus includes a storage unit and a processing unit. The storage unit stores an RTL (Register Transfer Level) description with description of structurization for structurizing an RTL description model for an integrated circuit into modules, and a correspondence table which shows correspondence relation of each ... 06/02/05 - 20050120323 - Method for modifying the behavior of a state machine A method and system for modifying the function of a state machine having a programmable logic device. The method including: (a) modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; (b) generating a programmable logic device netlist ... ### FreshPatents.com Support |