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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Programmable Integrated Circuit (e.g., Basic Cell, Standard Cell, Macrocell) Programmable Integrated Circuit (e.g., Basic Cell, Standard Cell, Macrocell)Programmable Integrated Circuit (e.g., Basic Cell, Standard Cell, Macrocell) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266361 - Logic verification method, logic verification apparatus and recording medium There is provided a logic verification method for performing logic verification of an integrated circuit by using device data defining functions of the integrated circuit. The logic verification method includes reading device data made up by a plurality of pieces of logic module data each including (i) first circuit data ... 11/01/07 - 20070256047 - Integrated circuit with signal skew adjusting cell selected from cell library An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and ... 10/11/07 - 20070240093 - Architecture and method for providing integrated circuits A customizable integrated circuit is programmed to provide both hardware task functions and interconnects. A plurality of execution units is executable concurrently to emulate hardware tasks. A plurality of programmable locations provides logical interconnect between the executable programs. ... 07/19/07 - 20070168901 - Library creating apparatus and method, and recording medium recording library creating program thereon In order to efficiently create a library of characteristic values of a low hierarchical circuit, which library is used in operation verification of circuitry including low hierarchical circuitry and high hierarchical circuitry, so that the time period necessary to create a library is considerably reduced, the present apparatus includes a ... 07/05/07 - 20070157151 - Engineering change order cell and method for arranging and routing the same There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at ... 06/28/07 - 20070150849 - Basic cell design method for reducing the resistance of connection wiring between logic gates The basic cell design method of the present invention is a method for carrying out: extended pattern formation for extending the patterns of input wiring and output wiring in the longitudinal direction, forming first extended patterns that extend with a prescribed dimensional width in a direction perpendicular to the longitudinal ... 06/14/07 - 20070136715 - Semiconductor device and designing support method for the same In a support method of designing a semiconductor device, a plurality of wiring lines are arranged in parallel in a wiring line layer to transfer a same signal. A wiring line inhibition area is set in the wiring line layer to cover a space between the plurality of wiring lines ... 05/17/07 - 20070113216 - Photolithographic mask correction An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with ... 04/26/07 - 20070094632 - Method in an integrated circuit (ic) manufacturing process for identifying and redirecting ics mis-processed during their manufacture A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on ... 04/19/07 - 20070089083 - Method and design system for semiconductor integrated circuit A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can ... 04/12/07 - 20070083842 - Standard cell library, method of designing semiconductor integrated circuit, semiconductor integrated circuit pattern, and semiconductor integrated circuit An exemplary cell library includes a first plurality of types of standard cells. Each of the first plurality of types of standard cells includes threshold voltage adjusting patterns. The upper and the lower boundaries of the threshold voltage adjusting patterns contact the upper and lower boundaries of the cell frame ... 03/01/07 - 20070050746 - Method and system product for implementing uncertainty in integrated circuit designs with programmable logic Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic ... 02/22/07 - 20070044065 - Reconfigurable integrated circuit device for automatic construction of initialization circuit A reconfigurable integrated circuit device, in which an arbitrary operating state is constructed based on configuration data, has a reconfigurable circuit unit, having a plurality of reconfigurable processor elements and a processor element network to connect the processor elements in an arbitrary state, and a reconfiguration control portion, which supplies ... 02/22/07 - 20070044064 - Processor network Processes are automatically allocated to processors in a processor array, and corresponding communications resources are assigned at compile time, using information provided by the programmer. The processing tasks in the array are therefore allocated in such a way that the resources required to communicate data between the different processors are ... 02/08/07 - 20070033565 - Basic cell of semiconductor integrated circuit and layout method thereof Basic cells each including, in addition to logic cells, one or a plurality of capacity cells between a power supply line and a ground line, and the like, are prepared in advance in the form of a logic synthesis cell library. The prepared basic cells are inserted at a logic ... 11/30/06 - 20060271903 - Method and apparatus for generating layout pattern A method includes: obtaining process technology definition data related to a process technology of each layer forming the basic cell, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition ... 11/30/06 - 20060271902 - Semiconductor integrated circuit designing method and library designing method A method for designing a semiconductor integrated circuit includes: a step (a) of setting basic patterns including a plurality of active region/gate patterns each including a gate and an active region and a dummy gate while taking account of patterns of gates on the respective sides of each gate; a ... 11/09/06 - 20060253827 - Hierarchial semiconductor design Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances ... 10/26/06 - 20060242616 - Methods and apparatus for design entry and synthesis of digital circuits Methods and apparatus are provided for design entry and synthesis of components, such as components implemented on a programmable chip. In one example, a design tool receives natural or intuitive parameters describing characteristics of a component in a design. Natural or intuitive parameters include input data rate, output latency, footprint, ... 10/19/06 - 20060236293 - Method and apparatus for comparing and synchronizing programmable logic device user configuration dataset versions A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user configuration dataset including old features as well as newly-added features) for the “origin” programmable logic device to the existing user configuration ... 10/12/06 - 20060230376 - Methods for creating and expanding libraries of structured asic logic and other functions Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ... 10/05/06 - 20060225021 - Automatic adjustment of optimization effort in configuring programmable devices User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of ... 10/05/06 - 20060225020 - Methods and apparatus for 3-d fpga design Methods, apparatus, and systems are directed to an FPGA that includes a three-dimensional architecture having a component coupled to at least five components across two or more strata. In one embodiment, a FPGA includes a three dimensional switch that can be coupled to at least the five switches, wherein switches ... 09/28/06 - 20060218519 - Layout design method for semiconductor integrated circuit, and semiconductor integrated circuit In a layout design method for a semiconductor integrated circuit, a cell layout library is provided which stores structure information of functional cells and a plurality of groups of filler cells, each filler cell acting to fill space between the functional cells. The functional cells are arranged on a layout ... 09/21/06 - 20060212838 - System and apparatus for in-system programming Embodiments of the present invention relate to machines that perform in-system programming of programmable devices that are attached to assembled printed circuit boards. In accordance with one aspect, multiple nonvolatile devices may be programmed in a single session at their normal maximum programming speeds. Different nonvolatile devices on a board ... 09/14/06 - 20060206850 - Automated system for designing and developing field programmable gate arrays An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined ... 08/31/06 - 20060195811 - System and method for reducing design cycle time for designing input/output cells I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell ... 08/24/06 - 20060190904 - Common interface framework for developing field programmable device based applications independent of a target circuit board A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). According to one embodiment, a field programmable device (FPD) comprises at least one hardware design language (HDL) ... 08/10/06 - 20060179417 - Alterable application specific integrated circuit (asic) A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises ... 07/20/06 - 20060161876 - Array-based architecture for molecular electronics An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array ... 06/22/06 - 20060136858 - Utilizing fuses to store control parameters for external system components Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused ... 05/11/06 - 20060101369 - Automated processor generation system for designing a configurable processor and method for the same A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that ... 05/04/06 - 20060095886 - Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer ... 04/20/06 - 20060085781 - Library for computer-based tool and related system and method A library includes one or more circuit templates and an interface template. The one or more circuit templates each define a respective circuit operable to execute a respective algorithm or portion thereof. And the interface template defines a hardware layer operable to interface one of the circuits to pins of ... 04/13/06 - 20060080632 - Integrated circuit layout having rectilinear structure of objects An integrated circuit layout pattern is formed from a plurality of objects placed within the layout pattern. Each object has a homogenous communications interface, which is a rectilinear donut structure formed of communications elements surrounding a central object logic area. The communications elements are adapted to route data between the ... 04/13/06 - 20060080631 - Asics having more features than generally usable at one time and methods of use More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different ... 04/06/06 - 20060075374 - Apparatus and method for licensing programmable hardware sub-designs using a host-identifier Methods and apparatuses for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design through the use of hardware technologies. According to one embodiment, a hardware sub-design includes a license verification sub-design that is protected from user modification by encryption. In one embodiment, ... 03/30/06 - 20060070016 - Data processing in digital systems A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can ... 03/23/06 - 20060064665 - Standard cell library having globally scalable transistor channel length A standard cell library having a globally scalable transistor channel length is provided. In this library, the channel length of every transistor within a cell can be globally scaled, within a predetermined range, without changing cell functionality, cell size, or cell terminal positions. Such a cell library advantageously addresses the ... 03/16/06 - 20060059451 - Method for creating and synthesizing multiple instances of a component from a single logical model Methods for creating and synthesizing multiple instances of a component from a single logical model are provided. In general, a flag is provided which designates a design methodology for use in instantiating the component. Depending on the value of the flag, a block of hardware design code defining an instance ... 02/16/06 - 20060036988 - Methods and apparatus for implementing parameterizable processors and peripherals Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically ... 02/09/06 - 20060031807 - Assertion checking An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire ... 12/15/05 - 20050278681 - Method for synthesizing domino logic circuits A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell ... 11/10/05 - 20050251778 - System and method for dynamically executing a function in a programmable logic array A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer ... 10/13/05 - 20050229142 - System and method for automated accurate pre-layout estimation of standard cell characteristics An automated computer-implemented method, storage medium, and system for obtaining a pre-layout estimation of a characteristic of a standard cell including receiving a pre-layout netlist of a standard cell, applying at least one transformation to the pre-layout netlist to obtain an estimated representation, and characterizing the estimated representation to obtain ... 10/13/05 - 20050229141 - Method and apparatus for creating a mask-programmable architecture from standard cells One embodiment of the invention provides a system for creating a mask-programmable module from standard cells. The system operates by first specifying characteristics of an end design and then selecting a plurality of standard cells from a standard cell library based on the characteristics of the end design. Next, the ... 10/13/05 - 20050229140 - Constraints-directed compilation for heterogeneous reconfigurable architectures Compilation of a design description for a heterogeneous reconfigurable architecture is influenced by user-specified constraints. ... 10/13/05 - 20050229139 - Block-based processing in a packet-based reconfigurable architecture A configurable circuit including a heterogeneous mix of processing elements is programmed. ... 09/01/05 - 20050193358 - Reconfiguration of a programmable logic device using internal control A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information ... 09/01/05 - 20050193357 - Allocation of combined or separate data and control planes A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication. ... 08/18/05 - 20050183055 - Method and apparatus for automating the design of programmable logic devices The design of programmable logic devices, such as FPGAs, may be automated to allow scripts, setup files, and other tool files to be created directly from hollowed and filled netlist, and data-path and design constraint files without extensive human intervention. This allows an FPGA design to be created directly from ... 07/14/05 - 20050155009 - Cell based integrated circuit and unit cell architecture therefor In a method for designing a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive ... 07/07/05 - 20050149896 - Integrated circuits with ram and rom fabrication options The present invention relates to electronic circuits that retain identical functionality and performance under RAM and hard-wire ROM fabrication options. An integrated circuit (IC) providing identical functionality and performance in two selectable fabrication options, wherein: a first selectable option comprises a user configurable circuit; and a second selectable option comprises ... ### FreshPatents.com Support |