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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Routing (e.g., Routing Map, Netlisting) > Pla, Pld, Fpga, Or Mcm Pla, Pld, Fpga, Or McmPla, Pld, Fpga, Or Mcm patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070261014 - System and method for design entry and synthesis in programmable logic devices A system and method facilitates the implementation of analog circuitry in electronic programmable devices. A user can specify user measurable parameters for analog features of the circuit, without requiring knowledge of the internal way in which those analog circuit are implemented in the programmable device to achieve desired properties of ... 11/01/07 - 20070256046 - Analysis and optimization of manufacturing yield improvements Techniques for improving the design of circuits, such as integrated microcircuits. A proposed circuit design is analyzed to identify design features associated with yield loss in manufactured circuits. Corrective design changes that will reduce the yield losses associated with the yield loss features then are designated. Once the corrective design ... 10/18/07 - 20070245289 - Memory re-implementation for field programmable gate arrays Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based ... 10/18/07 - 20070245288 - Operational cycle assignment in a configurable ic Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and ... 10/18/07 - 20070245287 - Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality ... 08/09/07 - 20070186203 - Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits. ... 08/02/07 - 20070180423 - Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different ... 07/12/07 - 20070162886 - Customizable development and demonstration platform for structured asics The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments. ... 07/05/07 - 20070157149 - Design configuration method for an automation system The invention relates to a projection method for an automation system, in addition to a device which is used to project an automation system. In order to simplify the projection of an automation system, projection data for at least one component (10, 10 12,14) of the automation system is combined ... 06/21/07 - 20070143729 - High speed camera bandwidth converter Image data from a CMOS sensor with 10 bit resolution is reformatted to allow the data to pass through communications equipment that is designed to transport data with 8 bit resolution. The incoming image data has 1280 columns and 1024 rows with 10 bit resolution. The communication equipment can transport ... 05/17/07 - 20070113215 - System and method for implementing package level ip preverification for system on chip devices A method for implementing package-level intellectual property (PLIP) preverification for system on chip (SOC) devices includes providing at least one externally connected intellectual property (IP) core with an SOC. A package generic unit is provided with the IP core and is configured for providing external interface functions with respect to ... 05/03/07 - 20070101309 - Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or ... 05/03/07 - 20070101308 - Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a nanowire crossbar comprises two or more layers of approximately parallel nanowires, and a number of configurable, tunneling resistor junctions that ... 04/19/07 - 20070089082 - Freeway routing system for a gate array A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable ... 03/29/07 - 20070074140 - Systems and methods for writing data with a fifo interface Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal ... 02/22/07 - 20070044063 - Method for estimating voltage droop on an asic A simulation circuit model for a region of interest in an integrated circuit chip design is constructed that has a number of tiled, substantially identical sub-region simulation circuit models, each representing the supply voltage (VDD) distribution network in one of a number of corresponding sub-regions of the region. This mosaic ... 02/15/07 - 20070038971 - Processing device with reconfigurable circuit, integrated circuit device and processing method using these devices In the processing device in accordance with the present invention, a plurality of divided circuits obtained by dividing one circuit are successively configured on a reconfigurable circuit, an operation is executed by the divided circuits by feeding back an output of one divided circuit to a next divided circuit, and ... 12/28/06 - 20060294490 - Apparatus for performing computational transformations as applied to in-memory processing of stateful, transaction oriented systems An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a ... 12/14/06 - 20060282812 - Communication network for multi-element integrated circuit system Embodiments of the invention include a system for communication within an integrated circuit. Hardware object nodes are connected to one another through a system of physical channels. Messages are sent from one node to another over the channels. The messages can be asynchronous in nature, as well as time-insensitive. Different ... 11/30/06 - 20060271901 - Mixed-signal functions using r-cells A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. ... 11/30/06 - 20060271900 - System and method to improve chip yield, reliability and performance Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. ... 11/02/06 - 20060248493 - Fpga with hybrid interconnect An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose ... 10/19/06 - 20060236292 - Base platforms with combined asic and fpga features and process of using the same A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory ... 08/24/06 - 20060190903 - Asics having programmable bypass of design faults A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to ... 08/17/06 - 20060184912 - Automatic design apparatus for semiconductor integrated circuits, method for automatically designing semiconductor integrated circuits, and computer program product for executing an application for an automatic design apparatus for semiconductor integrate An automatic design apparatus for semiconductor integrated circuits including a first acquisition module configured to acquire a first function description describing an arrangement of a plurality of data processors, and a second function description describing an arrangement of a plurality of connection selectors for switching the connection among the data ... 03/23/06 - 20060064664 - Reconfiguring a ram to a rom using upper layers of metallization The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core cell nodes and ... 03/16/06 - 20060059450 - Transparent re-mapping of parallel computational units An design architecture for an application specific integrated circuit (ASIC) is disclosed. The design architecture of the ASIC includes a pre-determined number of redundant computational units such that when defective computational units are found during testing, full functionality of the ASIC is maintained by re-mapping functionality from the defective units ... 03/09/06 - 20060053404 - Methods and apparatus for implementing parameterizable processors and peripherals Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically ... 02/02/06 - 20060026547 - Circuit layout structure Main-transistors M1 and M2 are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a layout configuration that is ... 12/15/05 - 20050278680 - Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid fpga networks An automatically reconfigurable high performance FPGA system that includes a hybrid FPGA network and an automated scheduling, partitioning and mapping software tool adapted to configure the hybrid FPGA network in order to implement a functional task. The hybrid FPGA network includes a plurality of field programmable gate arrays, at least ... 12/08/05 - 20050273750 - Turn architecture for routing resources in a field programmable gate array A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a ... 12/08/05 - 20050273749 - Structured asic device with configurable die size and selectable embedded functions One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present invention provides for a common set of base tooling from which the master/universal base is created as well as additional custom ... 09/15/05 - 20050204326 - Method of configuring information processing system and semiconductor integrated circuit A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing ... 09/15/05 - 20050204325 - Method for mapping logic design memory into physical memory devices of a programmable logic device A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping ... 08/11/05 - 20050177808 - System for delay reduction during technology mapping in fpga The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present ... 07/28/05 - 20050166170 - Field programmable platform array The present invention is directed to a field programmable platform array (FPPA). In an exemplary aspect of the present invention, a method for providing field programmable platform array units (PAUs) may include the following steps. First, N by M array of platform array units may be cut from a field ... 06/30/05 - 20050144584 - Programmable logic module and upgrade method thereof A programmable logic module. In the programmable logic module, a first printed circuit board has a socket and a downloading unit. A field programmable gate array (FPGA) is disposed on the first printed circuit board. A nonvolatile memory stores program codes for programming the field programmable gate array. The nonvolatile ... 06/09/05 - 20050125760 - Data processing in digital systems A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can ... ### FreshPatents.com Support |