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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Routing (e.g., Routing Map, Netlisting) > Detailed Routing (e.g., Channel Routing, Switch Box Routing) Detailed Routing (e.g., Channel Routing, Switch Box Routing)Detailed Routing (e.g., Channel Routing, Switch Box Routing) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/25/07 - 20070250802 - Switch with a pulsed serial link A method for routing signals comprising: supplying to an input of a routing block having multiple outputs an information signal comprising a first edge and a second edge on a single line, the first and second edges being separated by a time period which represents information conveyed by the signal, ... 09/27/07 - 20070226673 - Method of reducing correclated coupling between nets Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, ... 02/08/07 - 20070033564 - Analysis method and analysis apparatus An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into ... 01/11/07 - 20070011641 - Semiconductor integrated circuit device The semiconductor integrated circuit device includes a plurality of grid-like wiring structures 150 arranged as unit regions in an entire circuit area and having the same shape as a clock wiring structure, respectively; a first wiring structure in which the wiring paths from an clock input 110 to the respective ... 11/02/06 - 20060248492 - Block interstitching using local preferred direction architectures, tools, and apparatus Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by implementing a stitching region between the block and external routing structures. The stitching region is implemented using local preferred direction approaches. ... 08/31/06 - 20060195810 - Aligned logic cell grid and interconnect routing architecture A method (150) for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell (12) is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch (24) of the interconnect layout and a transistor ... 08/17/06 - 20060184910 - Reconfigurable interconnect for use in software-defined radio systems A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for each of the P possible configuration, determining a list of required interconnections ... 07/20/06 - 20060161875 - Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including ... 07/06/06 - 20060150138 - Method of creating optimized tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the same Provided are a method of creating an optimized tile-switch mapping architecture in an on-chip bus, and a computer readable recording medium for recording the method. The method of creating a tile-switch mapping architecture includes first, second and third calculating steps. The method of creating a tile-switch mapping architecture minimizes the ... 06/01/06 - 20060117291 - Layout of network using parallel and series elements Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing ... 12/29/05 - 20050289496 - Symmetric signal distribution through abutment connection The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros ... 12/08/05 - 20050273748 - Local preferred direction routing Some embodiments of the invention provide a method for defining routes in a design layout. The method defines at least one particular wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a detailed ... 10/27/05 - 20050240894 - Multidirectional wiring on a single metal layer An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is ... 06/09/05 - 20050125759 - Cell-based method for creating slotted metal in semiconductor designs A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design ... ### FreshPatents.com Support |