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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Routing (e.g., Routing Map, Netlisting) > Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination) Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination)Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070256044 - System and method to power route hierarchical designs that employ macro reuse A method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently. Once an RLM has been routed and timed it can be copied and reused in a physical design as is, and does not ... 10/11/07 - 20070240091 - Methods and systems for optimizing designs of integrated circuits Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within ... 10/04/07 - 20070234266 - Method of optimizing ic logic performance by static timing based parasitic budgeting Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable to meet timing and power goals is presented. ... 09/06/07 - 20070209028 - Resonant tree driven clock distribution grid An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution ... 08/30/07 - 20070204256 - Interconnection modeling for semiconductor fabrication process effects In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based on ... 08/30/07 - 20070204255 - Net routing A solution for routing a net based on a slew and/or delay for one or more critical sinks in the net is provided. To this extent, the solution can generate electrical connection information for a circuit by generating a routing tree for each net in the circuit. When the net ... 08/23/07 - 20070198962 - Semiconductor integrated circuit and method of designing layout of the same A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source wiring, a second pseudo power source wiring ... 08/02/07 - 20070180422 - Generating rules for nets that cross package boundaries In an embodiment, data models are stitched into a stitched data model, where each of the data models has nets and at least one of the nets crosses a package boundary. A subset of the nets from the stitched data model are selected based on a constraint, and the subset ... 07/19/07 - 20070168900 - Vlsi timing optimization with interleaved buffer insertion and wire sizing stages The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires ... 07/12/07 - 20070162885 - Semiconductor device layout method, a computer program, and a semiconductor device manufacture method A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value. ... 07/12/07 - 20070162884 - Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, ... 07/12/07 - 20070162882 - Design support system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, design support program of semiconductor integrated circuit and method of manufacturing semiconductor integrated circuit According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried ... 06/28/07 - 20070150847 - Integrated circuit layout device, method thereof and program thereof A layout device for an integrated circuit executes calculating a timing value with respect to each wiring path by a analysis based on connection information and delay information of wirings, determining a target value serving as an improvement target of the wiring path, detecting an error wiring path exhibiting the ... 06/14/07 - 20070136714 - A method for ic wiring yield optimization, including wire widening during and after routing Embodiments herein present a method, service, computer program product, etc. or performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, ... 05/24/07 - 20070118828 - Generation of metal holes by via mutation A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs ... 05/10/07 - 20070106971 - Apparatus for a routing system The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power; ... 04/26/07 - 20070094631 - Method and apparatus for controlling congestion during integrated circuit design resynthesis The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in ... 04/26/07 - 20070094630 - Power grid design in an integrated circuit An aspect of the present invention computationally determines the metal density of each metal layer supporting a power grid structure providing power to the elements of an integrated circuits. The metal densities are computed such that the power grid would support aggregate power and IR drop constraints. The metal densities ... 03/29/07 - 20070074139 - Method and apparatus for circuit design and retiming Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the ... 03/22/07 - 20070067751 - Computer program product, method, and system for hardware model conversion A hardware model conversion system includes a logic synthesis tool and a hardware model conversion program. The logic synthesis tool logically synthesizes an HDL-described circuit and then outputs intermediate data. One assign statement described in the intermediate data is associated with one assign cell. The hardware model conversion program creates ... 03/22/07 - 20070067750 - Method and system for modeling wiring routing in a circuit design The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring ... 03/15/07 - 20070061770 - Semiconductor integrated circuit and layout designing method of the same A semiconductor integrated circuit of the present invention comprises a hard macro and a plurality of wirings connected to the hard macro. The hard macro comprises a hard macro main body, and a plurality of pins with a minimum pin width based on a design rule of the semiconductor integrated ... 03/15/07 - 20070061769 - Layout method and layout program for semiconductor integrated circuit device A plurality of cells are disposed in a chip region and wires are disposed between the cells in order to connect the cells over a plurality of layout steps. The layout method comprises (1) a placement restricted region placement step for disposing, in the chip region, a placement restricted region ... 02/22/07 - 20070044061 - Semiconductor device, layout method and apparatus and program A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is provided in an interconnect layer different from the interconnect layer of the first conductor and which intersects ... 02/22/07 - 20070044060 - System and technique of pattern matching and pattern replacement A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. ... 01/25/07 - 20070022400 - Method, program, and apparatus for designing layout of semiconductor integrated circuit In a method for designing a layout for an LSI, library data, which is information on a standard cell with an assigned parameter or parameters each indicating the probability of occurrence of violations of design rules at a pin connection point, is read into a library information read section in ... 01/18/07 - 20070016884 - Apparatus, method, and medium for designing semiconductor integrated circuit A clock tree configuration is modified so that a branch point of a clock tree is arranged closer to a leaf of the tree, thereby restraining an increase in a clock skew due to variation. ... 01/11/07 - 20070011640 - Lsi circuit A power line for supplying a power supply voltage to a clock buffer and a power line for supplying a power supply voltage to another circuit are isolated from each other in both a semiconductor integrated circuit and a semiconductor package. Accordingly, even when power supply noise occurs in the ... 01/04/07 - 20070006111 - Circuit design device and circuit design program To reduce an influence on a customer circuit when a test circuit or the like is embedded into the customer circuit. Customer circuit design data 21 is the design data on the customer circuit targeted for design. A placement and routing processing unit 22 performs placement and routing processing on ... 12/28/06 - 20060294488 - Integrated circuit routing and compaction An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing ... 12/07/06 - 20060277517 - Wire spreading through geotopological layout The present invention provides a layout yield improvement tool that performs wire spreading to optimize integrated circuit (IC) designs in the physical design stage after detail routing. Preferably, the wire spreading is performed on a geotopological layout. Each modifiable wire thereof is processed to generate a geometric bottom-up shape (BUS) ... 11/30/06 - 20060271899 - Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The ... 10/19/06 - 20060236291 - Analytical placement method and apparatus In this equation, n represents a net, p(n) represents a unique pair of pins i and j of the net n, x and y represent the x-, and y-coordinates of a particular pin, and bi,j represents a weighting factor that biases the function based on the desired closeness of pins ... // - 2 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 1 - ... // - 1 - ... // - 2 - ... // - 2 - ... // - 2 - ... // - 1 - ... 10/05/06 - 20060225018 - Automatic trace determination method and computer program thereof An automatic trace determination apparatus comprises: first means that performs a first process sequentially for all intersections formed between tentative traces connecting between pads and corresponding vias, wherein the first process determines distances from an intersection formed between two tentative traces to the corresponding vias, respectively, and allows one of ... 08/24/06 - 20060190902 - Method, apparatus and program for automatically routing semiconductor integrated circuit Disclosed is an apparatus for performing automatic routing of a semiconductor integrated circuit, including an automatic routing and search processing unit for outputting post-routing layout data upon receiving inputs of post-routing layout data, circuit data and differential-signal information. The automatic routing and search processing unit includes: a differential-signal routing setting ... 08/24/06 - 20060190901 - Method of buffer insertion to achieve pin specific delays A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total ... 08/24/06 - 20060190900 - Method, system and computer program product for automatically estimating pin locations and interconnect parasitics of a circuit layout A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least ... 08/24/06 - 20060190899 - Method of clock tree distribution generation by determining allowed placement regions for clocked elements A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set ... 07/13/06 - 20060156267 - Recording medium recording a wiring method It is determined whether a short-run rule can be adapted into a position, where a via cell is parallel and adjacent to a portion of wiring or another via cell. The via cell and the portion of the wiring is arrayed at the smallest space in the wiring. When determined ... 07/13/06 - 20060156266 - Probabilistic congestion prediction with partial blockages A method of estimating routing congestion between pins in a net of an integrated circuit design, by establishing one or more potential routes between the pins which pass through buckets in the net, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in ... 06/29/06 - 20060143586 - Synthesis strategies based on the appropriate use of inductance effects A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the ... 06/15/06 - 20060129965 - Method and apparatus for characteristic impedance discontinuity reduction in high-speed flexible circuit applications A method and apparatus are provided for implementing characteristic impedance discontinuity reduction in customized high-speed flexible circuit applications. A curved artwork region is selected and selected cells are scanned. An area on opposite sides of a signal wire within each cell is determined. The identified areas are compared using a ... 06/01/06 - 20060117290 - Wiring method, program, and apparatus When one net is wired, by restricting a wiring area, the net is efficiently wired in a short time. A wiring area setting unit sets a maximum rectangle including a set of terminals constructing the net into a wiring area. A wiring deciding unit decides the wiring between the nets ... 06/01/06 - 20060117289 - Wiring method, program, and apparatus A problem is efficiently solved by giving a proper adjacent spacing condition only to nets having such a problem that a wiring delay and crosstalks are caused. A wiring processing unit executes a wiring process by giving a first adjacent spacing condition that does not become a wiring violation on ... 04/06/06 - 20060075373 - Method and device for the computer-aided design of a supply network A supply network is designed for a microelectronic circuit by a method for computer-aided design, in that an outline of the microelectronic circuit is detected and the supply network is generated with this outline. In the process, the supply network is designed with a structure in which a pattern is ... 03/09/06 - 20060053403 - System and method for routing clock signals from a clock trunk According to at least one embodiment, a system comprises a region generation engine operable to create a region automatically around a portion of a clock trunk in a block, wherein the region defines an area for placement of selected cells, an automatic cell placer operable to place the cells in ... 12/08/05 - 20050273747 - Local preferred direction routing Some embodiments of the invention provide a method for routing. The method defines at least one wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a global route on the wiring layer. The ... 12/08/05 - 20050273746 - Method and apparatus for generating layout regions with local preferred directions Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some ... 11/03/05 - 20050246676 - Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining ... 10/27/05 - 20050240893 - Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring Some embodiments provide an integrated circuit that includes several circuits. The integrated circuit further includes a first interconnect wiring layer that has a first preferred direction of interconnect wiring. The integrated circuit also includes a second interconnect wiring layer that has a second preferred direction of interconnect wiring, where the ... 10/13/05 - 20050229138 - Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are arranged in multiple rows, comprises: row identifying means ... 09/15/05 - 20050204324 - Interconnect structure of a chip and a configuration method thereof A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A ... 08/25/05 - 20050188340 - Method of designing semiconductor integrated circuit A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of ... 07/21/05 - 20050160391 - Semiconductor integrated circuit having multi-level interconnection, cad method and cad tool for designing the semiconductor integrated circuit A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected between subject first- and second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval ... 06/23/05 - 20050138593 - Semiconductor integrated circuit having diagonal wires, semiconductor integrated circuit layout method, and semiconductor integrated circuit layout design program A semiconductor integrated circuit includes a plurality of first wires running in a first direction of 0°, a 45° diagonal, a 90° angle and a 135° diagonal in a subject area disposed in a designated wiring layer in a multilevel interconnection; and a plurality of second wires running in a ... 06/16/05 - 20050132319 - Automatic method for routing and designing an lsi According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according ... 06/02/05 - 20050120322 - Method and apparatus for performing power routing on a voltage island within an integrated circuit chip A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N-1. Then, a second power grid is generated on metal levels N and above. A bounding region of ... ### FreshPatents.com Support |