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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Routing (e.g., Routing Map, Netlisting) Routing (e.g., Routing Map, Netlisting)Routing (e.g., Routing Map, Netlisting) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/11/07 - 20070240090 - Yield optimization in router for systematic defects Embodiments herein provide a method and computer program product for optimizing router settings to increase IC yield. A method begins by reviewing yield data in an IC manufacturing line to identify structure-specific mechanisms that impact IC yield. Next, the method establishes a structural identifier for each structure-specific mechanism, wherein the ... 10/04/07 - 20070234265 - Method, system, and article of manufacture for implementing metal-fill with power or ground connection Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and ... 09/13/07 - 20070214446 - Design stage mitigation of interconnect variability The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid ... 06/14/07 - 20070136713 - Method and apparatus for routing Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of route-segment ends) on a particular ... 04/12/07 - 20070083840 - Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of asic and programmable logic device A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal ... 04/05/07 - 20070079274 - Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function ... 02/01/07 - 20070028201 - Enhanced routing grid system and method Routing systems and methods are provided having various strategies for optimizing and evaluating possible routes for netlist connections. In one embodiment, a data structure or matrix provides cost related data weighted to evaluate the impact proposed a connection or segment will have upon an attribute of interest such as, for ... 01/04/07 - 20070006110 - Net list conversion method, net list conversion device, still-state leak current detection method, and still-state leak current detection device As shown in FIG. 1, a gate terminal of a MOS transistor or an input terminal of a logic gate, which are included in a through current detection target net list, are extracted, and a resistor is inserted between the gate terminal of the MOS transistor or the input terminal ... 12/28/06 - 20060294487 - Auto connection assignment system and method A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second ... 12/28/06 - 20060294486 - Manhattan routing with minimized distance to destination points For routing points to a center point, the points are grouped into a respective set disposed within each quadrant. Each point is Manhattan routed to any other point having a minimum Manhattan distance within a rectangle defined by each point and the center point, to result in at least one ... 12/21/06 - 20060288324 - Semiconductor device, and design method, inspection method, and design program therefor A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as ... 12/21/06 - 20060288323 - High-speed shape-based router A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be ... 12/14/06 - 20060282810 - Fullchip functional equivalency and physical verification A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity. ... 12/07/06 - 20060277516 - Digital lien service A process of digital electronic lien management is provided. Form data is stored in a first electronic database. A user adds lien input data in a second electronic database related to a specific construction lien project. A user then generates at least one lien form through insertion of the lien ... 11/30/06 - 20060271898 - Automatic trace determination apparatus and method Automatic trace determination apparatus comprises: means for setting candidate starting route and candidate ending routes that are tangent to an obstacle existing on a straight line connecting between a starting point and an end point of a trace; means for, when a plurality of obstacles exist on the straight line, ... 11/23/06 - 20060265684 - The use of redundant routes to increase the yield and reliability of a vlsi layout Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and ... 11/16/06 - 20060259892 - R-cells containing cdm clamps A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of ... 11/09/06 - 20060253826 - Method for manufacturing a power bus on a chip A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. ... 11/09/06 - 20060253825 - Relocatable mixed-signal functions An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused ... 10/26/06 - 20060242614 - Method and mechanism for implementing automated pcb routing A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path ... 10/19/06 - 20060236290 - Systems and methods for wiring circuit components Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to ... 10/05/06 - 20060225017 - Integrated circuit layout design system, and method thereof, and program There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing means provides wiring and outputs a layout in which short circuits are possibly left uncorrected. Short-circuit correcting means performs rewiring by using a newly defined tentative ... 09/07/06 - 20060200787 - Method for tracing paths within a circuit A method for tracing paths within a circuit includes receiving a transistor level netlist description. After receiving the transistor level netlist, convert the transistor level netlist to a transistor level data structure. Then, convert the transistor level data structure to a set of channel connect groups (CCG). A directed graph ... 08/24/06 - 20060190898 - Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal ... 08/24/06 - 20060190897 - Methods of routing an integrated circuit design An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing ... 08/24/06 - 20060190896 - Method for reducing the size and nanowire length used in nanowire crossbars without reducing the number of nanowire junctions Various embodiments of the present invention provide methods for designing multilayer nanowire crossbars that are functionally equivalent to two-layer nanowire-crossbar designs. Given a two-layer nanowire-crossbar design having two or more columns of microregions, in certain embodiments, the method conceptually folds the two-layer nanowire crossbar between columns of microregions. The folded ... 08/17/06 - 20060184909 - Semiconductor integrated circuit routing method and recording medium which stores routing software According to the present invention, there is provided a method of routing a semiconductor integrated circuit by using a routing apparatus having an input unit, a storage unit, and an arithmetic unit, comprising: receiving, by the input unit, for respective terminals of a plurality of elements contained in the semiconductor ... 07/27/06 - 20060168552 - Substrate mapping A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, ... 07/06/06 - 20060150137 - Three dimensional integrated circuits A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer. ... 07/06/06 - 20060150136 - Systems and methods for designing integrated circuits Systems and methods for designing integrated circuits (ICs) are provided. A representative method includes: providing a netlist; determining components required to implement test of at least a portion of the integrated circuit defined by the netlist; provide a revised netlist including the components determined; and performing a place and route ... 07/06/06 - 20060150135 - Circuit information generating apparatus and circuit information generating method Provided is an apparatus for generating circuit design information automatically clock gated, for the purpose of alleviating the burden of a designer in performing clock gating to a circuit. The apparatus having an obtaining unit operable to obtain functional structure information and execution sequence information from outside, the functional structure ... 06/15/06 - 20060129964 - Net list generating method and layout designing method of semiconductor integrated circuit A placement 103 of a macrocell is applied to a net list 102 formed by the logic synthesis by using the automatic layout tool, physical information of the macrocell is extracted in a physical information extracting step 104, and a net list 106 including the physical information is generated by ... 05/04/06 - 20060095885 - Systems and methods for storage area network design Systems and methods for designing storage area network fabric. Preferably included are an arrangement for collecting user requirements on data flows to be supported by the fabric, an arrangement for grouping the data flows into flow groups according to at least one physical location parameter, an arrangement for designing components ... 04/20/06 - 20060085780 - System and method for vlsi cad design A VLSI CAD system includes formulaic representations of grid lines to form grid boxes in a manner that enhances expressivity and reduces the amount of required processing resources. ... 03/09/06 - 20060053402 - Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device There is provided a method of correcting pattern data for a semiconductor device, including acquiring pattern data for a lower layer, pattern data for an upper layer, and pattern data for a connecting layer containing connecting patterns to connect patterns contained in the lower layer and patterns contained in the ... 03/02/06 - 20060048088 - Computer automated design method, program for executing an application on a computer automated design system, and semiconductor integrated circuit A computer automated design method includes defining rectangular areas serving as a starting point area and an ending point area of a wiring; accumulating wiring costs whenever an exploration of a wiring path from the starting point area to the ending point area advances one rectangular area, multiplying the wiring ... 02/16/06 - 20060036986 - Overlapping shape design rule error prevention A method, system and program product are disclosed that create new shapes at detected shape overlaps and includes those new shapes during routing and net checking when the new shapes require a larger space than any of the overlapping shapes. The invention thus detects and prevents spacing errors without the ... 02/09/06 - 20060031805 - Regular routing for deep submicron chip design A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore ... 12/15/05 - 20050278678 - Substrate contact analysis A method of analyzing substrate yield, where a substrate yield map and a substrate contact map are selected and overlaid to produce a composite map. First elements of the substrate yield map are compared to second elements of the substrate contact map to determine a degree of correlation between the ... 11/24/05 - 20050262464 - Integrated circuit routing resource optimization algorithm for random port ordering A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within ... 10/20/05 - 20050235242 - Semiconductor integraged circuit device and method of routing interconnections for semiconductor ic device A method of routing interconnections for a semiconductor integrated circuit device, which has a plurality of pads arranged in a first direction along a side of a chip and a plurality of slots arranged in an inner area of the plurality of pads, includes: (A) selecting such pads applicable to ... 10/13/05 - 20050229137 - Steiner tree handling device, steiner tree handling method, and steiner tree handling program A Steiner tree handling device handles a Steiner tree constituted by plural horizontal or vertical edges connecting plural nodes. The device has a Steiner tree obtaining unit which obtains a Steiner tree having one shape, and a Steiner tree deformation unit which deforms the obtained Steiner tree into a Steiner ... 09/29/05 - 20050216876 - Method and apparatus for routing differential signals across a semiconductor chip One embodiment of the present invention provides an arrangement of differential pairs of wires that carry differential signals across a semiconductor chip. In this arrangement, differential pairs of wires are organized within a set of parallel tracks on the semiconductor chip. Furthermore, differential pairs of wires are organized to be ... 09/22/05 - 20050210435 - Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated ... 09/22/05 - 20050210434 - Process for the production of an electrical wiring diagram This process allows for the automatic production of an electrical wiring diagram on which are located boxes, each representing a component used in an electrical device, connecting lines, each representing an interconnecting cable and connecting terminals corresponding to a possible connection point between a connecting line and a box, the ... 09/15/05 - 20050204323 - Interconnection routing method The present invention relates to a method of interconnection routing for preventing crosstalk. The method comprises the following steps. Providing an aggressor connection path as a first net. Providing a victim connection path according to the requirements of a second net. Determining a voltage ramp time of the aggressor connection ... 09/01/05 - 20050193356 - Nanoscale interconnection interface One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map ... 06/23/05 - 20050138592 - Apparatuses and methods to route line to line Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias in the printed circuit board may be ... 06/16/05 - 20050132318 - Layout quality analyzer In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and ... ### FreshPatents.com Support |