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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Floorplanning > Layout Editor (e.g., Updating) Layout Editor (e.g., Updating)Layout Editor (e.g., Updating) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070261013 - Designer's intent tolerance bands for proximity correction and checking A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, ... 11/01/07 - 20070256043 - Method and system for implementing a mass data change tool in a graphical user interface A method and system are provided for implementing a mass data change tool to update the column data for the selected rows in a table presented in the graphical user interface of a software application. The mass data change tool may include an additional row, a mass data change row, ... 10/25/07 - 20070250801 - Method and apparatus to visually assist legalized placement with non-uniform placement rules Embodiments of the present invention provide systems, methods and articles of manufacture for displaying semiconductor components in a graphical user interface and manipulating the position of semiconductor components. Embodiments of the present invention may check the placement of components against a plurality of placement rules and determine if a component ... 10/18/07 - 20070245286 - Wiring layout apparatus, wiring layout method, and wiring layout program for semiconductor integrated circuit A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose ... 10/04/07 - 20070234263 - Method and apparatus for describing and managing properties of a transformer coil A method and apparatus for describing and managing properties of a transformer coil. A metadata text file is generated which contains metadata describing objects of the transformer coil. The objects are arranged hierarchically and have one or more related properties attached therewith. One or more properties of one object refer ... 09/20/07 - 20070220472 - Computer aided wave-shaped circuit line drawing method and system A computer aided wave-shaped circuit line drawing method and system is proposed, which is designed for use with a computer platform for providing a user-operated wave-shaped circuit line drawing function, and which is characterized by the utilization of computer-aided graphic drawing technology to allow a user to define a set ... 08/30/07 - 20070204254 - Circuit diagram drafting system and method and computer program product A circuit diagram drafting system for drafting a circuit diagram comprised of a plurality of circuit components and connections connecting terminals of the circuit components, the circuit diagram drafting system provided with a display unit for displaying the circuit diagram and a managing unit for attaching and managing a line ... 08/23/07 - 20070198961 - Technology migration for integrated circuits with radical design restrictions A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to ... 08/09/07 - 20070186202 - Method and apparatus for insertion of filling forms within a design layout A method and apparatus for insertion of filling forms within a design layout are described. One or more jog areas are identified within a circuit design layout. Subsequently, multiple filling forms are inserted within the circuit design layout, each filling form being configured to eliminate a corresponding jog area within ... 08/02/07 - 20070180421 - Method and system for automatically generating schematics Method and system for automatically generating schematic diagrams of an assembly is provided. The method includes providing one or more identifiers for an assembly, the identifiers providing index to an assembly and component database. A plurality of components for the assembly is retrieved from the database based on the identifiers ... 07/05/07 - 20070157148 - Circuit layout system for automatically indicating items to wait for modification and method thereof A circuit layout system for automatically indicating items to wait for modified and method thereof are provided, wherein a set of items to wait for modified recorded on an amendment list is stored on the circuit layout software; the set of items to wait for modified is compared with the ... 07/05/07 - 20070157147 - Hardware component graph to hardware description language translation method An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components ... 06/21/07 - 20070143728 - Circuit layout methodology A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying ... 06/21/07 - 20070143727 - Method of designing layout of multipower integrated circuit In a layout design, there are executed a step 201 of defining a permitted connecting relationship of an interface signal to be transmitted across different power supplies, a step 202 of extracting the interface signal between the different power supplies based on information about each of the power regions and ... 06/21/07 - 20070143726 - Circuit design apparatus, circuit design program, and circuit design method A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines ... 06/21/07 - 20070143725 - Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating ... 06/14/07 - 20070136712 - Semiconductor design support apparatus The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of symmetry orthogonal to the first axis. The recognition pattern ... 06/07/07 - 20070130554 - Integrated circuit with dual electrical attachment pad configuration According to the present invention, an integrated circuit has a terminal pad configuration such that the integrated circuit may be wire bonded or flip chip bonded. The terminal pad configuration uses staggered rows of pads to allow the different bonding. ... 06/07/07 - 20070130553 - Analog layout module generator and method In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One ... 05/24/07 - 20070118827 - Method and apparatus for integrated circuit fault isolation and failure analysis using linked tools cockpit A microelectronic circuit debugging environment links development tools by correlating a selected element in a first tool with elements in the datasets of other tools. A signaling module instructs the other tools to display the correlated elements. ... 04/26/07 - 20070094629 - Methods and apparatus for making placement sensitive logic modifications Methods and apparatus are described for making a placement sensitive engineering change to meet design for test requirements. One of the methods includes placing a set of new flops in an already placed chip design to meet functional requirements of an engineering change. The already placed chip design is pruned ... 04/26/07 - 20070094628 - Methods of generating planar double gate transistor shapes and data processing system readable media to perform the methods A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity ... 04/19/07 - 20070089081 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to ... 04/19/07 - 20070089080 - Automatic layout method and automatic layout device An automatic layout method for performing an automatic layout of components on a diagram, the automatic layout method includes: generating a layout engine control object based on an operation of an application program; selecting at least one layout engine object from a plurality of layout engine objects for calculating coordinates ... 04/12/07 - 20070083839 - On-the-fly rtl instructor for advanced dft and design closure A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in ... 03/22/07 - 20070067749 - Method and system for embedding wire model objects in a circuit schematic design The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in ... 03/01/07 - 20070050745 - Timing violation debugging inside place and route tool A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include ... 02/22/07 - 20070044059 - Ip placement validation A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information for an intellectual property (IP) block to be placed on a platform application specific integrated circuit, (B) extracting device data for the platform ... 02/22/07 - 20070044058 - Enabling efficient design reuse in platform asics A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and ... 01/25/07 - 20070022399 - Rule-based schematic diagram generator A schematic diagram generator processes a netlist or similar circuit description to determine how to place and orient symbols representing devices forming the circuit based on a set of placement rules. Each rule corresponds to a separate characteristic pattern of interconnected devices, and specifies a constraint on relative positioning and/or ... 01/11/07 - 20070011639 - Placement methods for standard cell library Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncompliance are adapted to bring the layout within the design rules. In a preferred ... 01/04/07 - 20070006109 - Method and system for correcting signal integrity crosstalk violations A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay. ... 11/30/06 - 20060271897 - Semiconductor device An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low ... 11/30/06 - 20060271896 - Semiconductor device An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is located on a low ... 11/16/06 - 20060259891 - System and method of generating an auto-wiring script A system and method of generating an auto-wiring script, which can be utilized to generate a script used exclusively for the wiring software according to corresponding table specifying the relations between the net names and the electrical constraint sets and the files of other related attributes. The wiring software can ... 11/09/06 - 20060253824 - Software evaluation method and software evaluation system A portion of receiver software includes of a device information receiving section bound to an IP address corresponding to a virtual managed printer. The device information receiving section, as ported receiver software, receives distribution from an integrated management printer. As a result, one simulator agent PC can act as numerous ... 11/02/06 - 20060248491 - I /o planning with lock and insertion features A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the ... 11/02/06 - 20060248490 - System and method for text based placement engine for custom circuit design A system and method that uses a text-based script file to capture a circuit design and allows a circuit designer to manipulate the script file. The circuit designer can add, delete, or move components using various tags and commands that are stored in the script file. When the design is ... 10/19/06 - 20060236289 - Design support apparatus, design support method, and computer product An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link ... 10/19/06 - 20060236288 - Window operation interface for graphically revising electrical constraint set and method of using the same A window operation menu for graphically revising an electrical constraint set and a method of using the same. It may be used to graphically preview and revise the attribute contents of the electrical constraint set analyzed and exported by the wiring software, so that the batch revisions can be performed ... 10/19/06 - 20060236287 - Flexible shape identification for optical proximity correction in semiconductor fabrication Transient edges are used to define shapes in an integrated circuit layout for optical proximity correction. A first variation of the shape includes a first edge, a second edge satisfying an edge transition angle condition in relation to the first edge, and one or more first transition edges connected between ... 10/19/06 - 20060236286 - Cost-optimization method A method of controlling an optimal cost is proposed, which can be applied to a circuitry designing process for making electronic products, allowing a user in drawing a circuitry to choose elements of identical specification with different unit prices, thereby achieving the objective of cost-optimization. The cost-optimization method comprises the ... 10/19/06 - 20060236285 - Method for improving efficiency in laying out electronic components A method is proposed for improving the layout efficiency in laying out electronic components, which is applicable to information processing equipment, to accelerate the layout of electronic components. First, a first two-dimensional plan view including various electronic component members is preset using a drafting software platform. Subsequently, the two-dimensional plan ... 09/14/06 - 20060206849 - System, method and program for designing a semiconductor integrated circuit using standard cells A system for designing a semiconductor integrated circuit includes an extraction module for extracting through wiring tracks linearly passing through each of area priority cells and yield priority cells, a layout data generator for generating second layout data from first layout data by replacing the area priority cells with the ... 07/06/06 - 20060150134 - Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing is ended when the amount of noise is within a ... 06/22/06 - 20060136856 - Unit-based layout system for passive ic devices A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit, ... 06/22/06 - 20060136855 - Method of implementing an engineering change order in an integrated circuit design by windows A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated ... 06/15/06 - 20060129963 - Floorplan visualization method A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates ... 06/15/06 - 20060129962 - Cell builder for different layer stacks A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for ... 06/08/06 - 20060123377 - Interconnect integrity verification A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net ... 06/08/06 - 20060123376 - Power mesh for multiple frequency operation of semiconductor products The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be ... 05/25/06 - 20060112366 - Method and system for optimized automated ic package pin routing An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the ... 05/25/06 - 20060112365 - Design support apparatus, design support program and design support method for supporting design of semiconductor integrated circuit A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output ... 05/18/06 - 20060107247 - Memory generation and placement A memory generation and placement flow system that receives a customer memory design and places the customer memory design within a customizable standardized integrated circuit design. The memory generation and placement flow system includes a memory librarian tool, a memory estimator tool, and a memory placer tool. ... 05/11/06 - 20060101368 - Distributed electronic design automation environment PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each ... 05/04/06 - 20060095884 - Design analysis workstation for analyzing integrated circuits A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one ... 05/04/06 - 20060095883 - Method of automating place and route corrections for an integrated circuit design from physical design validation A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the ... 05/04/06 - 20060095882 - Distributed electronic design automation environment PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each ... 04/27/06 - 20060090153 - Method and apparatus for reducing power consumption in an integrated circuit chip A system that reduces power consumption in an integrated circuit. During operation the system receives a placement for the integrated circuit. The system then groups registers in the placement into clusters and builds a temporary clock tree for the registers within the placement. Next the system assigns net weights to ... 04/27/06 - 20060090152 - Schematic diagram generation and display system A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations ... 04/13/06 - 20060080630 - Power/ground wire routing correction and optimization A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration problems. If one or more problems are ... 04/06/06 - 20060075372 - Electronic device connectivity analysis methods and systems Techniques for determining and verifying connectivity in an electronic device from a representation of the electronic device are disclosed. Connectivity is determined by identifying electronic components and signals in the electronic device and providing an indication of the identified electronic components and signals. Based on identified components and signals, a ... 04/06/06 - 20060075371 - Method and system for semiconductor design hierarchy analysis and transformation A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed ... 04/06/06 - 20060075370 - Method and apparatus for automating post-tape release vlsi modifications A method and an apparatus for automatically making changes to one or more metal layers of an IC design after the IC design has been tape released. The apparatus includes an ECO tool configured to receive a directive or a list of directives and to automatically make modifications described by ... 03/30/06 - 20060070015 - Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon The design system, which is equipped with capability to analyze circuit board design data, comprises a storing section for recording design data, including structure data, circuit data, and element data; a selection section for selecting a pair of circuit elements subject to interference analysis among circuit elements placed on a ... 03/30/06 - 20060070014 - Real time monitoring system of semiconductor manufacturing information The present disclosure provides a system for monitoring semiconductor manufacturing in real time which includes an icon module with a database for storing a plurality of icons to provide stored icons that use vector data to represent respective pieces of equipment employed in semiconductor manufacture, a layout module which includes ... 03/16/06 - 20060059449 - Line layout structure of semiconductor memory devices A line layout structure of semiconductor memory device comprises first metal wire lines forming a bit line coupled to a memory cell, second metal wire lines disposed substantially orthogonal to the first metal wire lines and over the first metal wire lines, the second metal wire lines forming a section ... 03/09/06 - 20060053401 - Methods and apparatuses for designing integrated circuits Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netiist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description ... 03/09/06 - 20060053400 - Method for correcting layout errors A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout (10) is examined for the presence of layout errors (20, 30) ... 03/09/06 - 20060053399 - Semiconductor device, designing device, layout designing method, program and storage medium A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator ... 03/09/06 - 20060053398 - Methods, systems, and data models for describing an electrical device A method and system are described for creating a metadata text file corresponding to a geometry of a physical layout and/or a circuit layout of an electrical device. The layouts are defined in a user interface. A text file having metadata elements in a hierarchical format is produced that can ... 02/23/06 - 20060041853 - Cad apparatus, symbol creation device, cad program storage medium and symbol creation program storage medium The present invention provides a CAD apparatus having high plotting efficiency, a symbol creation device facilitating symbol creation, a CAD program storage medium storing a CAD program incorporated into a computer to enable the computer to operate as the CAD apparatus, and a symbol creation program storage medium storing a ... 02/02/06 - 20060026546 - Engineering change order scenario manager A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change orders implemented and (C) generating a ... 01/19/06 - 20060015837 - System and method for designing and manufacturing lsi An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of layout layers in the memory based on the layout layer definition file. The plurality of layout layers ... 12/29/05 - 20050289495 - Graphical interface to layout processing components and connections According to some embodiments, a graphical interface is provided to facilitate the layout of processing components and connections. ... 12/29/05 - 20050289494 - I/o circuit power routing system and method A method (400) of determining widths (W) and/or routes of I/O power routes (112) between one or more power distribution networks (108) and a plurality of I/O circuits (104) based on IR drop, electromigration, and electrostatic discharge electrical requirements. The method includes initially routing the I/O power routes and then ... 12/22/05 - 20050283750 - Method and apparatus for designing a layout, and computer product An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between ... 12/08/05 - 20050273745 - Determining feasibility of ic edits A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal ... 12/01/05 - 20050268270 - Layout data saving method, layout data converting device and graphic verifying device There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the ... 12/01/05 - 20050268269 - Methods and systems for cross-probing in integrated circuit design When designing integrated circuits, RTL source code is received and converted into objects. Objects may include a reference to relevant lines of source RTL code. A graphical user interface (“GUI”) displays the RTL code in an RTL window. The GUI also displays one or more representations of the objects in ... 11/10/05 - 20050251776 - Integrated circuit design system An integrated circuit design system has a second interface for displaying a plurality of description instructions corresponding to a specific integrated circuit according to a variety of display instructions, a first interface for inputting the display instructions and for updating a description instruction displayed on the second interface according to ... 10/27/05 - 20050240892 - Suite of tools to design integrated circuits A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; ... 10/20/05 - 20050235241 - Method and apparatus for designing layout, and computer product A layout designing apparatus includes an input unit that receives an input of a frame having a boundary scan register, a placing unit that places an I/O macro to be connected to a signal terminal for propagating other signal than a test signal in an arbitrary I/O macro placement area ... 10/20/05 - 20050235240 - Method for reducing layers revision in engineering change order An engineering change order (ECO) base cell module is disclosed along with some of its applications. The cell has an N well and P well, P+ implant and N+ implant regions, N well pick-up and P well pick-up regions, a first power supply line, and a second power supply line, ... 10/13/05 - 20050229136 - Design support system The design support system regarding the present invention comprises a node data storage means that stores node data to generate functional models which present a group of function nodes which are functions divided from performance function of apparatus which is an objective to be designed and a group of part ... 10/13/05 - 20050229135 - Apparatus and method for creating circuit diagram, program therefor and recording medium storing the program It is an object of the present invention to realize a circuit diagram creating method and circuit diagram creating apparatus capable of efficiently acquiring information on a lower layer, and a circuit diagram creating method for creating a layered electric circuit diagram from data indicating an electric circuit that includes ... 09/08/05 - 20050198605 - System for representing the logical and physical information of an integrated circuit A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data ... 08/25/05 - 20050188339 - System and method for navigating design information associated with an ic design A system and method for navigating through design information associated with an integrated circuit (IC) design. A graphical user interface is presented upon launching a connectivity browser, wherein the connectivity browser is operable to traverse a text-based connectivity database that includes a plurality of design objects provided for the IC ... 08/18/05 - 20050183054 - Modifying a design to reveal the data flow of the design in order to create a more favorable input for block placement A system is employed for modifying a hierarchical description of a design to reveal the data flow of the design. The modified design provides a more favorable input for block placement. In one embodiment, the modifications includes any one of or a combination of moving hard macros to a higher ... 08/04/05 - 20050172254 - Method and apparatus for supporting designing of lsi, and computer product A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded ... 07/14/05 - 20050155008 - Method and system for creating, viewing, editing, and sharing output from a design checking system Existing text output from a design rule checker is put in appropriate input format, and automatically displayed as text within a design tool using existing design tool capabilities, such as highlighting, zooming, and drawing box-regions. A graphical display of the output of the rule checker includes the informative text. Design ... 06/23/05 - 20050138591 - Layout device A layout device that reduces work. The layout device includes a storage unit for storing position information of patterns generated through layout designing. A display unit displays the patterns in accordance with a layout corresponding to the position information. An input unit enables a user to designate a pattern from ... 06/23/05 - 20050138590 - Generation of graphical congestion data during placement driven synthesis optimization The present invention provides a method and a computer-readable program for providing generation of graphical congestion images during placement driven synthesis optimization. These graphical congestion images enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, ... 06/16/05 - 20050132317 - Method and system for automatically extracting data from a textual bump map In at least some embodiments, a system may comprise a CPU, a graphical user interface coupled to the CPU, and a memory coupled to the CPU. The memory stores a bump map application and a data extraction application executed by the CPU, wherein the bump map application displays a plurality ... 06/16/05 - 20050132316 - Retiming circuits using a cut-based approach Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for one or more paths in the integrated circuit to obtain slack values, selecting one of the paths based on the slack values obtained, and determining a retimeable cut ... ### FreshPatents.com Support |