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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Floorplanning > Constraint-based Placement (e.g., Critical Block Assignment, Delay Limits, Wiring Capacitance) Constraint-based Placement (e.g., Critical Block Assignment, Delay Limits, Wiring Capacitance)Constraint-based Placement (e.g., Critical Block Assignment, Delay Limits, Wiring Capacitance) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266359 - Relative floorplanning for improved integrated circuit design A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a ... 10/18/07 - 20070245284 - Dummy filling technique for improved planarization of chip surface topography The use of smooth post-ECP topography (instead of final chip topography) as an objective during dummy filling enables a computationally efficient model-based dummy filling solution for copper while maintaining solution quality. A layout can be divided into tiles and the case, of each tile identified. Exemplary cases can include conformal ... 10/18/07 - 20070245283 - Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of ... 10/18/07 - 20070245282 - Systems, methods, and media for using relative positioning in structures with dynamic ranges Systems, methods, and media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments ... 10/04/07 - 20070234260 - Method for implementing overlay-based modification of vlsi design layout A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device ... 09/20/07 - 20070220470 - Automating optimal placement of macro-blocks in the design of an integrated circuit Automating optimal placement of macro-blocks in the design of an integrated circuit. A first set of placements is generated and corresponding measures of optimalness for each placement is computed. A new set of placements is generated, with each placement being generated from multiple (“chosen placements”) of the first set of ... 09/13/07 - 20070214445 - Element placement method and apparatus A method and a device for performing placement of a plurality of elements for circuit design. A potential location is assigned to each element and a placement engine is assigned to each potential location. Pairing operations are performed, in parallel, between placement engines to determine whether to perform exchange of ... 08/30/07 - 20070204252 - Methods and systems for placement Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a ... 08/30/07 - 20070204250 - Stress-managed revision of integrated circuit layouts Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features ... 08/30/07 - 20070204249 - A method, apparatus and computer program product for optimizing an integrated circuit layout A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is optimized according to the prioritized base ground rules ... 08/02/07 - 20070180420 - Designing a circuit apparatus with multiple propagation speeds of signals Designing a circuit apparatus involves determining locations and lengths of routing paths for signals, routing paths of a first length range being located in a first layer, and routing paths of a second length range being located in a second layer; determining propagation speeds for the signals to propagate through ... 07/19/07 - 20070168899 - Design method and architecture for power gate switch placement and interconnection using tapless libraries A method and a structure provide a space efficient integrated circuit using standard cells and power gating by switch cells. The standard cells may be tapless, i.e., not provided a substrate connection to a power supply or ground rail by a tap within the cell. The substrate connection for these ... 07/05/07 - 20070157145 - Method and end cell library for avoiding substrate noise in an integrated circuit A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input from an integrated circuit design at least a portion of a block for placement and routing on a substrate and an outer boundary of the block, selecting an end cell from a set of ... 07/05/07 - 20070157144 - Asic design using clock and power grid standard cell An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orientations in the different grid unit cells. ... 06/21/07 - 20070143724 - Method and apparatus for diffusion based cell placement migration A method, apparatus, and computer program product for cell placement in an integrated circuit design that use the principles of diffusion. ... 06/14/07 - 20070136711 - Layout design apparatus, layout design method, and computer product A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame ... 06/14/07 - 20070136710 - Layout design apparatus, layout design method, and computer product A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame ... 06/07/07 - 20070130552 - Layout method and computer program product A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the ... 05/31/07 - 20070124715 - Semiconductor integrated circuit and design method thereof In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is ... 05/31/07 - 20070124714 - Method for designing semiconductor integrated circuit layout According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none ... 05/24/07 - 20070118826 - Opc conflict identification and edge priority system An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments ... 05/24/07 - 20070118825 - Usage of a buildcode to specify layout characteristics A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells). Buildcode representations are then assigned for each of a plurality of circuit components and features thereof to realize customization of at least ... 05/17/07 - 20070113214 - Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data ... 05/17/07 - 20070113213 - Flip flop function device, semiconductor integrated-circuit, and method and apparatus for designing semiconductor integrated circuit A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library ... 05/17/07 - 20070113212 - Method and apparatus for mapping design memories to integrated circuit layout A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are ... 05/03/07 - 20070101307 - Design supporting system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, and computer readable medium for supporting design of semiconductor integrated circuit A design supporting system of a semiconductor integrated circuit includes a unit that converts a defective circuit pattern into computer detectable information when a layout of the chip is determined, and corrects the defective circuit pattern of layout of the chip based on the computer detectable information. ... 05/03/07 - 20070101306 - Methods, systems, and media to improve manufacturability of semiconductor devices Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to ... 04/26/07 - 20070094627 - Clock forming method for semiconductor integrated circuit and program product for the method Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of ... 04/12/07 - 20070083838 - Generating a base curve database to reduce storage cost An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in ... 04/05/07 - 20070079273 - Method and computer program for incremental placement and routing with nested shells A method of placing and routing an integrated circuit design includes steps of (a) generating an initial placement and routing for at least a portion of an integrated circuit design; (b) analyzing the initial placement and routing of the integrated circuit design to find a critical location; (c) partitioning the ... 03/15/07 - 20070061768 - Method of implementing polishing uniformity and modifying layout data A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional ... 03/01/07 - 20070050744 - Method of selecting cells in logic restructuring The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. ... 03/01/07 - 20070050743 - Vertical twist scheme for high density drams An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair of line conductors in first and second regions, the first pair of line conductors including a first true line conductor and a first associated complementary line conductor connected ... 02/08/07 - 20070033563 - Method of semiconductor device and design supporting system of semiconductor device A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval between adjacent two of interconnections, the interconnection intervals being discrete; and by specifying an interconnection relating an impermissible width and interconnections relating to an impermissible ... 02/08/07 - 20070033562 - Integrated circuit power distribution layout with sliding grids A method and integrated circuit (IC) configuration/design that provides efficient layout of power distribution wires within the IC. The power busses of each IC layers are configured as moveable segments capable of being shifted away from the normal propagation path of the remainder of the power bus. Circuit elements are ... 02/01/07 - 20070028200 - Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first ... 01/25/07 - 20070022398 - Via/bsm pattern optimization to reduce dc gradients and pin current density on single and multi-chip modules A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having ... 01/18/07 - 20070016883 - Clock gating circuit Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the ... 01/11/07 - 20070011638 - Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit A reticle set includes a first reticle including a first wiring pattern having a first termination pattern; a second reticle including a plurality of via patterns; and a third reticle including a second wiring pattern having a second termination pattern and a second line pattern connected to an end of ... 12/28/06 - 20060294485 - Method and apparatus for routing an integrated circuit A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit ... 12/07/06 - 20060277515 - Method, system and storage medium for determining circuit placement A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A ... 12/07/06 - 20060277514 - Method and system for distributing clock signals on non-manhattan semiconductor integrated circuits The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that ... 11/30/06 - 20060271895 - Non-uniform decoupling capacitor distribution for uniform noise reduction across chip An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead ... 11/30/06 - 20060271894 - Relative positioning of circuit elements in circuit design Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. ... 11/23/06 - 20060265683 - Circuit layout device, circuit layout method, and program for execution thereof A circuit layout device of a semiconductor integrated circuit having scan chains comprises a circuit layout section for performing the circuit layout of a semiconductor integrated circuit considering a weighting factor being set for a wire of the semiconductor integrated circuit and outputting the layout data, a wire length calculation ... 11/23/06 - 20060265682 - Manufacturing aware design and design aware manufacturing Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC ... 11/23/06 - 20060265681 - An automated and electrically robust method for placing power gating switches in voltage islands An efficient and automated algorithm for placing power gating switches within a voltage island of an integrated circuit, which ensures compliance with defined electrical specifications. A power gating switch is placed in every legal location on the integrated circuit and the minimum number of power gating switches is calculated based ... 11/16/06 - 20060259890 - Method and apparatus for power consumption reduction A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits ... 11/16/06 - 20060259889 - Method and apparatus for extending processing time in one pipeline stage A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input ... 11/16/06 - 20060259888 - Method of tiling analog circuits that include resistors and capacitors A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched ... 11/02/06 - 20060248489 - Memory efficient array transposition via multi pass tiling A schedule can be generated for physically transposing an array such that when the array is transferred from a first memory type to a second memory type, the number of block transfers performed is minimized. The array can be rearranged to ensure that most or all data elements in any ... 11/02/06 - 20060248488 - Method of generating wiring routes with matching delay in the presence of process variation A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first ... 10/19/06 - 20060236284 - Design method by estimating signal delay time with netlist created in light of terminal line in macro and program for creating the netlist A design method that implements automatic layout based on a first netlist created from a design circuit includes laying out a plurality of functional blocks of the design circuit based on the first netlist, creating a second netlist where information on line resistance and line capacitance of a line between ... 10/19/06 - 20060236283 - Method of designing layout of semiconductor integrated circuit and apparatus for doing the same A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a ... 10/19/06 - 20060236282 - Layout method of semiconductor integrated circuit and cell frame standardization program Cells with the same logic and similar driving capability among cells arranged on a substrate of a semiconductor integrated circuit are made into a format comprising terminals at the same position in the same-sized cell frame, and within cells in such a format, by arranging other cells in a redundant ... 10/19/06 - 20060236281 - Logic circuit design method, computer-readable recording medium having logic circuit design program stored therein, and logic circuit design device A logic circuit design method for use in a logic circuit having a hierarchical structure including an instance, a first block, and a second block is disclosed. The logic circuit design method includes the steps of reading information about the logic circuit, moving an instance which has a signal connection ... 10/05/06 - 20060225016 - Method and apparatus for laying out cells in a semiconductor device A method for generating layout data for macro cells in a core region of a semiconductor device. The method includes generating wiring margin-added macro cells, calculating the area of a maximum standard cell region by excluding the area of the wiring margin-added macro cells from the area of the core ... 09/28/06 - 20060218518 - Semiconductor integrated device and apparatus for designing the same The first circuit unit includes a first interface circuit unit 104, and the second circuit unit includes a second interface circuit unit 111 configured to perform inputting or outputting of a signal to and from the first interface circuit unit. The first ground wiring is coupled to the second ground ... 09/28/06 - 20060218517 - Method for designing integrated circuits comprising replacement logic gates In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for ... 09/28/06 - 20060218516 - Design rule report utility This invention provides a graphical tool by which a designer or engineer may quickly, accurately and efficiently check the relational information between elements of a computer model. By way of example, in one embodiment, the invention may be used to quickly validate the design rules, like minimum spacing requirements for ... 09/28/06 - 20060218515 - Method of identifying floorplan problems in an integrated circuit layout A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined ... 09/14/06 - 20060206848 - Method and apparatus for considering diagonal wiring in placement The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each ... 08/31/06 - 20060195809 - Circuit layout methodology A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying ... 08/24/06 - 20060190895 - Method and program for designing semiconductor device A method for designing a semiconductor device by using a computer, includes steps (a) to (b). The step (a) is the step of placing a power line and a ground line along a first direction. The step (b) is the step of placing a capacity cell which includes a bypass ... 08/24/06 - 20060190894 - Area-efficient distributed device structure for integrated voltage regulators An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas ... 08/24/06 - 20060190893 - Logic cell layout architecture with shared boundary Logic cell layout architecture having a shared boundary between at least two cells each forming logic functions, and a method (200) for designing a logic cell library having a shared boundary between at least two cells (12,32) is disclosed for increasing packing density and limiting the occurrence of stress between ... 08/24/06 - 20060190892 - System and method for automatic insertion of on-chip decoupling capacitors A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of ... 08/24/06 - 20060190891 - Method for placing probing pad and computer readable recording medium for storing program thereof A method for placing probing pad and a computer readable recording medium for storing a program thereof are provided. The method is suitable for placing the probing pads in an integrated circuit (IC). Wherein, appropriate grid spacing is determined and a plurality of grids with fixed grid spacing is generated. ... 08/17/06 - 20060184908 - Method and program for generating layout data of a semiconductor integrated circuit and method for manufacturing a semiconductor integrated circuit with optical proximity correction A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating ... 07/13/06 - 20060156265 - Method and system to redistribute white space for minimizing wire length Disclosed are a method and a system for redistributing white space on an integrated circuit. The method comprises the steps of providing a series of circuit blocks for the integrated circuit, and placing the blocks on the integrated circuit to obtain a predefined optimal wire length. In accordance with the ... 06/22/06 - 20060136854 - Method for placement of pipeline latches An integrated chip die comprises a data source connected to a data sink by way of a signal path wherein one or more pipeline latches are automatically inserted into the signal path at predetermined intervals when the length of the signal path is greater than a predetermined maximum signal propagation ... 06/08/06 - 20060123375 - Integrated circuit capable of locating failure process layers An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. ... 06/08/06 - 20060123374 - Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package A method, apparatus, and computer program product are disclosed for automatically enhancing a power distribution system (PDS) in a ceramic integrated circuit package. The package includes multiple layers. The entire package is divided into a three-dimensional grid that includes multiple different grid cells. Information is associated with each one of ... 05/25/06 - 20060112364 - Techniqes for super fast buffer insertion A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from ... 05/25/06 - 20060112363 - Multiple buffer insertion in global routing Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit ... 05/11/06 - 20060101367 - Design method of semiconductor device and semiconductor device In an error analysis step, analysis of an antenna effect error, a timing constraint violation and the like is performed for layout data in which redundant via conversion has been performed. Then, whether or not an error exists is judged and, among redundant vias located on a signal line in ... 05/11/06 - 20060101366 - Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines ... 05/04/06 - 20060095881 - Power pad synthesizer for an integrated circuit design A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of the ... 05/04/06 - 20060095880 - Process for designing base platforms for ic design to permit resource recovery and flexible macro placement, base platform for ics, and process of creating ics Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is ... 04/13/06 - 20060080629 - Method and system for generating an initial layout of an integrated circuit A system for generating a layout of an integrated circuit is disclosed. The system includes at least one processing unit for executing computer programs, a graphical-user-interface for viewing representations of the integrated circuit on a display and observing the layout of the integrated circuit, and a memory for storing databases ... 04/06/06 - 20060075369 - Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor ... 04/06/06 - 20060075368 - Method for placing electrostatic discharge clamps within integrated circuit devices A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is ... 03/23/06 - 20060064663 - Layout method for semiconductor integrated circuit, layout program for semiconductor integrated circuit and layout system for semiconductor integrated circuit When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal corresponding to a signal terminal designated for input level fixation by the circuit connectivity information on the basis of terminal correspondence ... 03/23/06 - 20060064662 - Method of floorplanning and cell placement for integrated circuit chip architecture with internal i/o ring A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an ... 03/16/06 - 20060059448 - Method for production of a standard cell arrangement, and apparatus for carrying out the method A standard cell arrangement can be produced by automatically determining a distance between at least two standard cells in at least one standard cell row. The method also automatically determines whether at least one of the determined distances is less than a predetermined minimum distance. If the distance is less ... 03/16/06 - 20060059447 - Integrated circuit design support apparatus, integrated circuit design support method, and integrated circuit design support program In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a ... 03/09/06 - 20060053397 - Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components. ... 03/02/06 - 20060048087 - Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position ... 02/23/06 - 20060041852 - Targeted optimization of buffer-tree logic Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays ... 02/09/06 - 20060031804 - Clustering techniques for faster and better placement of vlsi circuits A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects ... 02/09/06 - 20060031803 - Trial placement system with cloning In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated ... 02/09/06 - 20060031802 - Clustering-based multilevel quadratic placement A method of designing a layout of an integrated circuit, by grouping a plurality of logic cells in a region of the integrated circuit into at least two separate clusters, placing the clusters in the region of the integrated circuit to optimize total wire length between the clusters (e.g., using ... 01/19/06 - 20060015836 - Negative slack recoverability factor - a net weight to enhance timing closure behavior More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather ... 01/12/06 - 20060010415 - Method, system and storage medium for determining circuit placement A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A ... 01/12/06 - 20060010414 - Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given ... 01/05/06 - 20060005155 - Time separated signals One exemplary system includes a delay circuit configured to copy a signal and to introduce a timing delay into the copy. ... 12/29/05 - 20050289493 - Method and apparatus for designing a layout, and computer product An apparatus for designing a layout includes an arranging unit that arranges, on a large-scale-integrated chip, a cell in which a signal line segment that is not connected to a terminal is formed; a wiring unit that wires a signal line to an arbitrary wiring layer of the large-scale-integrated chip; ... 12/08/05 - 20050273744 - Ic tiling pattern method, ic so formed and analysis method The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. ... 12/08/05 - 20050273743 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to ... 11/24/05 - 20050262463 - Wiring optimizations for power An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no ... 11/10/05 - 20050251775 - Rotary clock synchronous fabric Methods for generating a design for logic circuitry using rotary traveling wave oscillators (RTWOs) are described. A plurality of RTWOs are is arranged into an array of rows and columns. Adjacent elements in the array are interconnected so that the clocks in adjacent element are phase synchronous. Clocked devices are ... 10/27/05 - 20050240891 - Method of switching a power supply of voltage domains of a semiconductor circuit, and corresponding semiconductor circuit A method of switching a power supply of at least one voltage domain of a semiconductor circuit uses at least one microswitch, which is designed in standard cell design, to switch the power supply, so that the standard cell design method can be automated. Multiple microswitches can be disposed, evenly ... 10/27/05 - 20050240890 - Circuit layout and semiconductor substrate for photosensitive chip A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed ... 10/20/05 - 20050235239 - Semiconductor integrated circuit and design method therefor In a master-slice-type semiconductor integrated circuit having a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed, and a plurality of wiring layers including variable wiring patterns of which wiring pattern is changeable by a user and fixed wiring layers of which wiring ... 10/20/05 - 20050235238 - Layout design apparatus, layout design method, and computer product A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame ... 10/13/05 - 20050229134 - Local preferred direction architecture, tools, and apparatus Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than ... 10/13/05 - 20050229133 - Method of designing a circuit of a semiconductor device In a method of designing a circuit layout of a semiconductor integrated circuit, a logic function of the integrated circuit is first designed. Then, a pattern layout of the integrated circuit is designed. The designed pattern layout includes a logic cell area and an open area. Next, a spare underground ... 10/13/05 - 20050229132 - Macro cell for integrated circuit physical layer interface A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots ... 09/15/05 - 20050204322 - Design layout preparing method There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect ... 09/08/05 - 20050198604 - Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each ... 08/18/05 - 20050183053 - Software product for and method of laying-out semiconductor device A software product for laying-out a semiconductor device includes the functions of: (A) locating a plurality of macros including a plurality of first macros of the same kind belonging to a first hierarchy; (B) arranging interconnections connecting between the plurality of macros; (C) extracting from the interconnections a plurality of ... 08/04/05 - 20050172253 - Automatic placement and routing device, method for placement and routing of semiconductor device, semiconductor device and manufacturing method of the same A method of placement and routing of a semiconductor device, includes steps (a) to (c). The step (a) is a procedure of executing placement of functional blocks and executing routing of interconnections in a placement and routing area of a semiconductor device based on circuit diagram data, functional block data ... 08/04/05 - 20050172252 - Elastic assembly floor plan design tool A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement ... 07/28/05 - 20050166169 - Method for legalizing the placement of cells in an integrated circuit layout A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts within the physical design automation area including global and detailed placement, physical synthesis, and ECO (Engineering Change Order) mode for timing/design ... 07/21/05 - 20050160390 - Cloned and original circuit shape merging A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point ... 07/14/05 - 20050155007 - Automatic layout method of semiconductor integrated circuit In a layout designing operation of LSI, while repetitions as to a timing improvement and a retry of layout designing are suppressed, a designing term is shortened. An automatic layout method of a semiconductor integrated circuit is comprised of: an initial arranging step for initially arranging a logic cell which ... 07/14/05 - 20050155006 - Constraint data management for electronic design automation In a method of determining the existence of one or more conflicts in the placement or configuration of circuit objects defining a circuit, a number of constraints is defined, each of which imposes at least one limitation on at least one circuit object. A number of constraint families is then ... 06/30/05 - 20050144583 - Method and data-processing system for rule-based optical proximity correction with simulataneous scatter bar insertion Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar is applied on a mask in addition to a main structure for the purpose of a subsequent imaging of the main structure from the mask onto a ... 06/30/05 - 20050144582 - Design techniques enabling storing of bit values which can change when the design changes Techniques which allow a bit value stored/generated by integrated circuits to be changed by changing potentially only one of several masks used to fabricate the circuits. For example, when a single mask is to be re-designed to implement a design change (e.g., to fix minor bugs) and a version identifier ... 06/23/05 - 20050138589 - Method and apparatus for performing density-biased buffer insertion in an integrated circuit design A method, apparatus, and computer program product for performing density biased buffer insertion in an integrated circuit design are provided. A tiled Steiner tree topology map is used in which density values are associated with each tile in the map. A directed acyclic graph (DAG) is created over an initial ... 06/09/05 - 20050125758 - Positioning of inverting buffers in a netlist A method, apparatus, system, and signal-bearing medium that, in an embodiment, position inverting buffers to improve placement of a logic circuit. An inverting buffer, within a netlist, is moved from a source region to a sink region, where the source region and the sink region are connected via inverting and ... ### FreshPatents.com Support |