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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Floorplanning > Detailed Placement (i.e., Iterative Improvement) Detailed Placement (i.e., Iterative Improvement)Detailed Placement (i.e., Iterative Improvement) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/18/07 - 20070245281 - Placement-driven physical-hierarchy generation A method and system for performing placement-driven physical hierarchy generation in the context of an integrated circuit layout generation system is provided. This generation optimizes the physical hierarchy to improve placement of the cells in the layout, and the associated interconnect routability and delay. A new pre-clustering phase is introduced ... 10/18/07 - 20070245280 - System and method for placement of soft macros An electronic design automation method of placing circuit components of an integrated circuit (“IC”) is provided. A synthesized circuit netlist including one or more soft macros is received and a rough global placement of this netlist is performed. A shaper function is determined. The shaper function evaluates a cost of ... 10/11/07 - 20070240088 - Vlsi artwork legalization for hierarchical designs with multiple grid constraints A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ... 10/04/07 - 20070234259 - Cell placement in circuit design A solution for managing a circuit design, which enables a cell to be incrementally placed in the circuit design based on a resulting wiring distance is provided. A cell to be placed in the circuit design is obtained along with a corresponding set of nets in the circuit design to ... 10/04/07 - 20070234258 - Method for post-routing redundant via insertion in integrated circuit layout The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for ... 08/09/07 - 20070186201 - Method for designing cell layout of semiconductor integrated circuit and computer readable medium in which a cell layout design program is recorded With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes ... 08/09/07 - 20070186200 - Method and apparatus for facilitating cell placement for an integrated circuit design One embodiment of the present invention provides a system that determines a feasible cell placement for an integrated circuit design. During operation, the system receives an input cell placement, which is typically determined using a quadratic placement technique. Next, the system receives a set of regions within the integrated circuit ... 08/02/07 - 20070180419 - Various methods and apparatuses to route multiple power rails to a cell Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A ... 07/19/07 - 20070168898 - Method and system for detailed placement of layout objects in a standard-cell layout design A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their ... 04/19/07 - 20070089079 - Method and tool for creating a layout for an electronic circuit The present invention relates to a method, a tool, and a computer program product for creating a layout of an electronic circuit from a netlist of interconnected components, wherein the components can be represented by planar geometric shapes in the layout. The advantages of the present invention are achieved by ... 04/12/07 - 20070083837 - Method and placement tool for designing the layout of an electronic circuit According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are based on relations between the geometrical shapes represented by the layouts for the ... 03/08/07 - 20070055952 - Method for physical placement of an integrated circuit based on timing constraints A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical placement technique. After the first pass of the physical placements of the blocks and the top level, the timing results of the top ... 01/11/07 - 20070011637 - Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device At least one cell pair graph is generated for cells of the layout. A partial inverse layout tree is determined from the cell pair graph. For the partial inverse layout tree, only branches of the complete inverse layout tree are considered that describe an interaction between shapes of different cells. ... 01/11/07 - 20070011636 - Method and system for performing non-local geometric operations for the layout design of a semiconductor device In one embodiment, an automatic check is performed to determine if the output of a parent region is compatible with the output of a current region of a cell. If the output of the parent region is compatible with the output of the current region of a cell, the output ... 12/21/06 - 20060288322 - Incremental geotopological layout for integrated circuit design Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout ... 12/14/06 - 20060282809 - Logic transformation and gate placement to avoid routing congestion A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. ... 11/23/06 - 20060265680 - Method and system for chip design using physically appropriate component models and extraction An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than ... 11/16/06 - 20060259887 - Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output ... 09/14/06 - 20060206847 - Layout optimizing method for a semiconductor device, manufacturing method of a photomask, a manufacturing method for a semiconductor device, and computer program product A layout optimizing method for a semiconductor includes preparing design rule of a semiconductor device, circuit connection information or layout data of the semiconductor device, and circuit characteristic information of the semiconductor device, and optimizing a layout of the semiconductor device using the design rule, the circuit connection information or ... 08/24/06 - 20060190890 - Cell instance generating method By a hierarchical structure developing process at Step S1, layout pattern data possessing hierarchical structure is developed to flat layout pattern data. An optimizing process at Step S2 generates optimized flat layout pattern data accompanying a new inserted cell. By a hierarchical structure cell instance allotting process at Step S3, ... 06/08/06 - 20060123373 - Density driven layout for rram configuration module A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place ... 05/25/06 - 20060112362 - Design method, design apparatus, and computer program for semiconductor integrated circuit The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information ... 05/25/06 - 20060112361 - Method of selecting cells in logic restructuring The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. ... 04/20/06 - 20060085779 - Representing device layout using tree structure Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a device. The tree structure may be generated by assigning root nodes, branch nodes and leaf nodes to portions of a tree ... 04/20/06 - 20060085778 - Automatic addition of power connections to chip power The present invention relates to a method for designing a hierarchical, multi-layer integrated circuit (IC) chip design in which a first stage design at a lower level of the hierarchical design provides details of circuit features that occupy areas of the design, and in a higher level stage of the ... 03/23/06 - 20060064661 - Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution ... 02/02/06 - 20060026545 - Integrated circuit macro placing system and method A method (300) of placing a to-be-placed integrated circuit macro (404) adjacent one or more already-placed macros (400) aboard an integrated circuit chip (100). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector (500, ... 01/12/06 - 20060010413 - Methods for placement which maintain optimized behavior, while improving wireability potential A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, ... 12/15/05 - 20050278677 - Novel test structure for automatic dynamic negative-bias temperature instability testing The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, ... 12/15/05 - 20050278676 - Method of physical planning voltage islands for asics and system-on-chip designs Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage ... 12/01/05 - 20050268268 - Methods and systems for structured asic electronic design automation Electronic design automation (“EDA) methods and systems for structured ASICs include accessing or receiving objects representative of source code for a structured ASIC. The objects are flattened to remove hierarchies associated with the source code, such as functional RTL hierarchies. The flattened objects are clustered to accommodate design constraints associated ... 12/01/05 - 20050268267 - Methods and systems for mixed-mode physical synthesis in electronic design automation Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clustering. The clusters, and any unclustered objects, are floorplanned. Floorplanning positions the clusters so as to reduce or minimize ... 11/24/05 - 20050262462 - Method and apparatus for designing multi-tier systems A system and method for selecting a preferred design for a multi-tiered architecture of components based on a set of established criteria is provided. The system and method receive a model describing different design constructions and a set of performance and availability requirements and produces a design or set of ... 10/27/05 - 20050240889 - Process and apparatus for placing cells in an ic floorplan Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in ... 09/29/05 - 20050216875 - System for integrated circuit layout partition and extraction for independent layout processing A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or ... 08/25/05 - 20050188338 - System for designing integrated circuits with enhanced manufacturability A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into ... 07/21/05 - 20050160389 - Method of protecting a semiconductor integrated circuit from plasma damage In the design of an integrated circuit having a semiconductor substrate and metal interconnecting lines, including a core ring with metal power and ground lines that supply power to a core area inside the core ring, one or more metal-oxide-semiconductor capacitor units are laid out below the core ring. Each ... 06/16/05 - 20050132315 - Extendable method for revising patterned microelectronic conductor layer layouts Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring ... 06/16/05 - 20050132314 - Circuits and methods for matching device characteristics for analog and mixed-signal designs Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit components by uniformly distributing circuit components in a manner that eliminates or significantly ... ### FreshPatents.com Support |