REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Floorplanning FloorplanningFloorplanning patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/25/07 - 20070250800 - Automated integrated circuit development Customization methodology for integrated circuit (e.g., clocks) design customization using a software tool that integrates multiple integrated circuit development operations. ... 08/02/07 - 20070180418 - Clock scheme for circuit arrangement The present invention provides a circuit arrangement comprising a clock conductor (230-3) coupled to a number of circuit components (210-c, 210-d, 210-e), each said circuit component being coupled to the clock conductor with a respective filter (240-1, 240-2), wherein at least one of the filters is arranged to pass a ... 08/02/07 - 20070180417 - System and method of spatial/tabular data presentation A system and method of spatial/tabular data presentation. Display data is identified for display. Relations for the display data are identified. The display data is displayed in a data display having a tabular column and a spatial column. Data identifiers are displayed in the tabular column and spatial identifiers connected ... 07/26/07 - 20070174801 - Programmable via modeling A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have ... 07/12/07 - 20070162880 - Single event transient immune antenna diode circuit An antenna diode circuit is described. The antenna diode circuit includes two diodes connected in series between a signal line and ground. Alternatively, the antenna diode circuit is connected in series between a signal line and a power supply. In addition to protecting the signal line from charge accumulation during ... 06/28/07 - 20070150846 - Methods and systems for placement Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a ... 06/14/07 - 20070136709 - Floorplanning a hierarchical physical design to improve placement and routing Methods for floorplanning a hierarchical physical design to improve placement and routing are provided and described. In one embodiment, a method of floorplanning a hierarchical physical design includes arranging a plurality of blocks in a top-level of the hierarchical physical design. Each block includes a plurality of linear edges. Additionally, ... 05/03/07 - 20070101305 - Methods and systems for implementing dummy fill for integrated circuits A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the ... 04/12/07 - 20070083836 - Method of wiring data transmission lines and printed circuit board assembly wired using the method A method of wiring data transmission lines between a CPU including CPU data pins identified by a set of pin numbers and a DRAM including DRAM data pins also identified by the set of pin numbers, the method including connecting the CPU data pins to the DRAM data pins with ... 02/22/07 - 20070044057 - Semiconductor device with multiple wiring layers and moisture-protective ring A semiconductor device with a space-saving design of common power lines shared by a plurality of function macros. An LSI chip has a plurality of wiring layers, a moisture-protective ring, and a plurality of function macros (e.g., I/O macros and I/O macro groups). Each function macro has a VSS power ... 02/22/07 - 20070044056 - Macro block placement by pin connectivity A design tool includes a first module, a second module, a third module and a fourth module. The first module may be configured to select a platform for implementing an integrated circuit design in response to input from a user. The second module may be configured to select a macro ... 01/11/07 - 20070011635 - Method of selling integrated circuit dies for multi-chip packages An integrated circuit has a plurality of bonding pads, at least one of which is adapted to be directly electrically connected to a bonding pad of another integrated circuit rather than to an external pin of a package that houses a semiconductor die on which the integrated circuit is fabricated. ... 01/04/07 - 20070006108 - Apparatus and method for implementing an integrated circuit ip core library architecture An integrated circuit (IC) architecture includes a library of intellectual property (IP) cores configured to provide a plurality of individual circuit functions. The IP cores arranged in a manner compatible with a customized, functional selection of individual ones of the IP cores, wherein individually selected cores are accessible through a ... 12/28/06 - 20060294484 - Method for auto enlarging bend portion width and computer readable recording medium forstoring program thereof A method for auto enlarging bend portion width and a computer readable recording medium for storing program thereof are provided. The method can enlarge the bend portion width from an original width to an intended width in layout. Wherein, the terminals of the center line of the bend is a ... 12/21/06 - 20060288321 - Method for computer aided design of semiconductor integrated circuits In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining ... 11/23/06 - 20060265679 - Manufacturing aware deisgn and design aware manufacturing Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines ... 11/16/06 - 20060259886 - Computer readable mask shrink control processor An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and ... 10/26/06 - 20060242613 - Automatic floorplanning approach for semiconductor integrated circuit In an automatic floorplanning approach, flexibility is given to the shape and area of a black-box block set in advance, so that the shape and area of the black-box block are made to reflect influences of line congestion and the like at the chip level, and also become less influential ... 10/12/06 - 20060230375 - Integrated circuit with relocatable processor hardmac An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf cells arranged in rows and columns. Each column of leaf cells has interface pins that are routed to a ... 10/05/06 - 20060225015 - Various methods and apparatuses for flexible hierarchy grouping Methods and apparatuses are described for incorporating floor planning information into a configuration process by generating a definition of a floor plan grouping of interconnect components during a front-end view design process for the interconnect. Further, a user is permitted to combine components from separate IP block representations of interconnects ... 08/31/06 - 20060195808 - Method for correcting the optical proximity effect A respectively separate optical proximity correction (OPC) process model and method is formed for selected structure classes or partial patterns of a layout is disclosed. For this purpose, the corresponding structure elements are treated separately as early as during the modeling. During the modeling and also for OPC correction, the ... 08/24/06 - 20060190889 - Circuit floorplanning and placement by look-ahead enabled recursive partitioning Placement or floorplanning of an integrated circuit is performed by constructing legal layouts at every level of a hierarchy of subsets of modules representing the integrated circuit, by scalably incorporating legalization into each level of the hierarchy, so that satisfiability of constraints is explicitly enforced at every level, in order ... 08/24/06 - 20060190888 - Apparatus and method for electronic device design A system and method is disclosed for computer-assisted transistor design. A new transistor design can be generated based on characteristics of an existing transistor. The system for transistor design receives a first set of parameters for an existing transistor design that are functions of a first geometry that is descriptive ... 08/24/06 - 20060190887 - Method for realizing circuit layout A method for realizing circuit layouts. Complex integrated circuit includes cells of basic functions, and layout designs for these cells can be recorded as a library. The claimed invention replaces common power strips with grid power contacts/vias in the layout of each cell. While realizing the layout of an integrated ... 07/20/06 - 20060161874 - Printed circuit wiring board designing support device, printed circuit board designing method, and its program A printed circuit wiring board designing support device includes a layout data receiving section receiving printed circuit board layout data through an input/output section, a section for extracting structures of power supply/ground planes, a via hole extracting section for extracting a via hole interconnecting the wirings extending over power supply/ground ... 06/01/06 - 20060117288 - Lsi physical designing method, program, and apparatus In addition to a rectangular shape, a non-rectangular shape is enabled to be handled as a physical design unit, thereby miniaturizing a chip and reducing the costs. A floor plan processing unit forms a floor plan for arranging a plurality of circuit blocks including a non-rectangular area into the chip. ... 04/27/06 - 20060090151 - Detailed placer for optimizing high density cell placement in a linear runtime A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two ... 04/20/06 - 20060085777 - Compact custom layout for rram column controller The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the ... 04/13/06 - 20060080628 - Semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus A semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus are provided that implement automatic placement that reflects constraints provided regarding parasitic elements and inter-element variation provided in a real-valued range. A netlist is prepared in advance, a permissible range setting process sets a permissible range relating to ... 03/23/06 - 20060064660 - Method and apparatus for depopulating peripheral input/output cells Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to ... 02/16/06 - 20060036985 - Compacting circuit responses Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to ... 02/09/06 - 20060031801 - Method and apparatus for generating a wafer map A system is provided to aid in the laying out of circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with the goal to maximize yield probability. The subject system accommodates different chip types and arrangements within ... 01/19/06 - 20060015835 - Placement method for decoupling capacitors A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid ... 01/12/06 - 20060010412 - Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each ... 12/15/05 - 20050278675 - General purpose delay logic A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of ... 12/15/05 - 20050278674 - Nested design approach A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has ... 12/15/05 - 20050278673 - Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and ... 11/24/05 - 20050262461 - Input/output circuits with programmable option and related method A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a plurality of sub-circuit cells with the same layout, and at least a connection layer having different layouts ... 11/03/05 - 20050246675 - Method and apparatus for designing integrated circuit layouts A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout ... 11/03/05 - 20050246674 - Method and apparatus for designing integrated circuit layouts A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that us calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of ... 10/20/05 - 20050235237 - Stability metrics for placement to quantify the stability of placement algorithms A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations ... 10/13/05 - 20050229131 - Intermediate layout for resolution enhancement in semiconductor fabrication Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments ... 10/13/05 - 20050229130 - Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements An automated design for manufacturability platform for integrated physical verification and manufacturing enhancement operations. Given original layouts and one or more associated resolution-enhanced layouts, intermediate resolution-enhancement state layouts are reconstructed, and selective localized resolution-enhancement reconfigurations, modifications, and/or perturbations are introduced on any existing enhancements in order to improve manufacturability and ... 09/08/05 - 20050198603 - Method for physical parameter extraction for transistor model A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's ... 09/08/05 - 20050198602 - Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies A method, computer program product and system for assessing the impact of anomalies in a physical device. An anomaly may be detected in an integrated circuit. Upon detecting an anomaly, an image of the anomaly may be captured. A design layout of the image may be obtained. The image coordinates ... 08/18/05 - 20050183052 - Computer-implemented design tool for synchronizing mechanical and electrical wire harness designs A computer-implemented design tool is provided for analyzing a wire harness design for an electrical systems. The design tool includes: a synchronizing rule set residing in a data store; and a synchronizer adapted to receive topographical data for at least one wire harness in the electrical system and wire layout ... 06/02/05 - 20050120321 - Integrated circuits, and design and manufacture thereof A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality ... ### FreshPatents.com Support |