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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Partitioning (e.g., Function Block, Ordering Constraint) Partitioning (e.g., Function Block, Ordering Constraint)Partitioning (e.g., Function Block, Ordering Constraint) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/04/07 - 20070234257 - Method and apparatus for circuit partitioning and trace assignment in circuit design Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved ... 09/20/07 - 20070220469 - Method and system for designing and electronic circuit A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin. ... 08/23/07 - 20070198960 - Methods for tiling integrated circuit designs Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are ... 08/09/07 - 20070186199 - Heuristic clustering of circuit elements in a circuit design An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the ... 03/15/07 - 20070061767 - Method and system for performing minimization of input count during structural netlist overapproximation A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of ... 12/28/06 - 20060294483 - Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level ... 11/16/06 - 20060259885 - System and method for analyzing a circuit A system and method for analyzing a circuit. In one embodiment, a tool generates path information based upon a netlist that describes the circuit. A synthesizer generates a nodal data structure responsive to the path information. A parser is operable to parse a nodal query to provide a tree structure ... 08/17/06 - 20060184907 - Extracting/reflecting method and hierarchical circuit information with physical information and circuit designing method using the same By reflecting physical information extracted from layout information on hierarchical circuit information while maintaining its hierarchical structure and creating the hierarchical circuit information with the physical information, to reflect the physical information with its accuracy kept on the hierarchical circuit information, thereby realizing high speed of circuit simulation and reduction ... 05/11/06 - 20060101365 - Method and apparatus for partitioning an integrated circuit chip A system that partitions an integrated circuit. First, the system receives a placement for an integrated circuit. The system then calculates a joint-utilization ratio for pairs of logic modules in the placement. Next, the system sorts the pairs of logic modules based on the joint-utilization ratio. The system then selects ... 05/11/06 - 20060101364 - Method and apparatus for data distribution in a high speed processing unit A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can ... 03/09/06 - 20060053396 - Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical ... 11/24/05 - 20050262460 - Method for creating a jtag tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP) ... 11/10/05 - 20050251774 - Circuit design property storage and manipulation One example embodiment of property data storage includes using row and column names to identify properties to a particular circuit design component. Each of a plurality of columns in a relational database table is named with a property name indicative of a respective one of a plurality of circuit design ... 10/20/05 - 20050235236 - Method for finding maximum volume and minimum cut in a network of interconnected nodes A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing ... 06/30/05 - 20050144581 - Scheduler, method and program for scheduling, and apparatus for high-level synthesis A scheduler includes: a schedule information acquisition section configured to acquire the number of first clock cycles and the number of second clock cycles as schedule information of a function belonging to a lower-hierarchy, the number of the first clock cycles being the number of clock cycles after an execution ... 06/09/05 - 20050125757 - Derivation of circuit block constraints A design tool for generating circuit block constraints from a design environment. The design tool derives a fan-in cone function for each block input of a circuit block of a design. The fan-in cone function may include fan-in cone variables and block input variables. The fan-in cone functions are conjoined ... 06/09/05 - 20050125756 - Autonomic graphical partitioning Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical ... 06/02/05 - 20050120320 - Evaluation device for control unit, simulator, and evaluation system An evaluation device, for evaluating a control unit (ECU) to which another control unit (ECU) is connected through a communication line and communicating with it, which can simulate even an unstable state such as when the other control unit does not start up right after power is turned on. The ... ### FreshPatents.com Support |