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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Testing Or Evaluating > Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width) > Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing) Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing)Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266357 - Timing analysis method and timing analysis apparatus A signal timing analysis method for analyzing timing of a signal propagated along a path including instances. The method includes performing a delay calculation, generating files storing delay information, input slew rate, and output capacitance, performing static timing analysis (STA) based on the delay information, and generating an analysis result. ... 11/01/07 - 20070256041 - Method and apparatus of core timing prediction A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused ... 10/18/07 - 20070245279 - Method and system for verifying performance of an array by simulating operation of edge cells in a full array model A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation ... 10/04/07 - 20070234256 - System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving ... 10/04/07 - 20070234255 - Ramptime propagation on designs with cycles A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a ... 10/04/07 - 20070234253 - Multiple mode approach to building static timing models for digital transistor circuits A method and a system for building static models for transistor circuit design is described. This method includes performing an automatic timing model construction several times on certain problem CCCs, with different, typically incompatible sets of user-selected local information for each call. Each of the sets of local information is ... 10/04/07 - 20070234252 - Method, system, and program product for computing a yield gradient from statistical timing The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a ... 10/04/07 - 20070234251 - Data output clock selection circuit for quad-data rate interface A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have ... 09/27/07 - 20070226670 - Variable delay circuit, recording medium, logic verification method and electronic device There is provided a variable delay circuit to be implemented in an integrated circuit, the variable delay circuit including: a variable delay assigning section that assigns a variable time delay to an input signal in an actual operation of the integrated circuit, the variable time delay being varied within a ... 09/27/07 - 20070226668 - Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a ... 09/27/07 - 20070226667 - Static timing slacks analysis and modification A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint ... 09/20/07 - 20070220468 - Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack ... 09/20/07 - 20070220466 - Methods and apparatus for reducing timing skew Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are ... 08/09/07 - 20070186198 - Generation of an extracted timing model file A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. ... 08/02/07 - 20070180416 - System and method for design development This invention relates to a system and methods for developing designs. In one embodiment, a method includes electronically distributing a specification for a design to a distributed community of designers, receiving designs from each of a subset of the community of designers in response to the distributed design specification, screening ... 08/02/07 - 20070180415 - Method of leakage optimization in integrated circuit design This invention reduces leakage power in an integrated circuit design formed of a plurality of design cells selected from a library of cells. The method of this invention considers all design cells, identifies corresponding candidate cells having the same function and swaps a candidate design cell having a least leakage ... 07/19/07 - 20070168897 - Hierarchical signal integrity analysis using interface logic models Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information ... 07/05/07 - 20070157143 - System for avoiding false path pessimism in estimating net delay for an integrated circuit design A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function ... 06/21/07 - 20070143723 - Method of timing verification and layout optimization In timing verification considering process variations in the fabrication of semiconductor integrated circuits, parasitic element extraction results are obtained with high accuracy by considering variations in interconnect configuration occurring randomly inside LSI to perform timing verification of worst-case or best-case simulation. For example, a plurality of capacitance libraries are prepared ... 06/21/07 - 20070143722 - System and method of criticality prediction in statistical timing analysis A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the ... 06/14/07 - 20070136708 - Clock skew compensation A clock distribution approach includes distributing a clock signal from a clock tree to a first set of circuit elements characterized by a first circuit characteristic; and distributing a clock signal from a sub-tree of the clock tree to a second set of circuit elements characterized by a second circuit ... 06/14/07 - 20070136707 - Method and system for distributing clock signals on non-manhattan semiconductor integrated circuits The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that ... 06/14/07 - 20070136706 - Exploration of the method of the interconnect effort in nano-technologies Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert ... 06/14/07 - 20070136705 - Timing analysis method and device A timing analysis device for preventing the amount of data and the number of analysis operations from increasing in a statistical analysis, while improving the timing convergence in a path included in a net under relatively strict timing conditions. The timing analysis device performs a static timing analysis to extract ... 06/14/07 - 20070136704 - Method and apparatus for generating memory models and timing database A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are ... 06/14/07 - 20070136703 - Method and apparatus for performing temporal checking An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of ... 05/17/07 - 20070113211 - Efficient statistical timing analysis of circuits Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each ... 05/10/07 - 20070106970 - Method and apparatus for supporting integrated circuit design An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a part of elements of same ... 05/10/07 - 20070106969 - Method of automatically routing nets according to parasitic constraint rules A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements. ... 05/10/07 - 20070106968 - Opc trimming for performance An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form ... 05/03/07 - 20070101304 - Fast/slow state machine latch A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed ... 04/26/07 - 20070094626 - Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through ... 04/19/07 - 20070089078 - Variable sigma adjust methodology for static timing The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage ... 04/19/07 - 20070089077 - System and method for integrated circuit timing analysis An integrated circuit timing analysis system includes: a first storage section for storing a layout of an integrated circuit including a plurality of transistors; and a processing section for processing the layout stored in the first storage section. The processing section includes a layout dividing section for dividing the layout ... 04/19/07 - 20070089076 - Application of consistent cycle context for related setup and hold tests for static timing analysis A technique for performing static timing analysis of an integrated circuit design provides a relationship between reference events of a setup test and a hold test for a particular signal path of an integrated circuit design. The relationship between the reference events of the setup and hold tests is used ... 04/12/07 - 20070083835 - Method for the computer-aided ascertainment of a clock tree structure, and integrated semiconductor circuit A method for the computer-aided ascertainment of a clock tree structure which couples a clock generation unit to a multiplicity of switching elements ascertains first switching elements from the multiplicity of switching elements, the first switching elements infringing a prescribed, first time-based switching criterion. In further method steps, the first ... 04/05/07 - 20070079272 - Design support system and design method for circuit board, and noise analysis program A design support system for circuit board includes: a noise source extracting unit for extracting a source of unwanted radiation noise which is generated from a circuit board mounted on an electronic equipment; a noise characteristics input unit for inputting noise characteristics of the unwanted radiation noise which is emitted ... 04/05/07 - 20070079271 - Design tool, design method, and program for semiconductor device A design tool, which is capable of designing an IC in which no malfunctions occur during a normal operation and a test, by limiting the amount of noise produced by the operation of an SRAM during the normal operation of the IC itself and during the test of the IC, ... 03/29/07 - 20070074138 - Delay analysis device, delay analysis method, and computer product A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based ... 03/22/07 - 20070067748 - Method and system for enhancing circuit design process A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after ... 03/01/07 - 20070050742 - Timing verification method for semiconductor integrated circuit Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial ... 02/22/07 - 20070044055 - Clock signal driver and clock signal supplying circuit having the same A clock signal driver and a clock signal supplying circuit having the same are provided. An embodiment of the clock signal driver includes an internal clock driver for receiving a clock signal and a complementary clock signal, buffering the clock signal and inverting the complementary clock signal, and combining phases ... 02/22/07 - 20070044054 - Buffering technique using structured delay skewing A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to implement the buffers based on design constraints. In an exemplary embodiment, the line buffers may be arranged in any buffer topology arrangement meeting ... 02/22/07 - 20070044053 - Multimode delay analyzer A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning ... 02/08/07 - 20070033561 - Speeding up timing analysis by reusing delays computed for isomorphic subcircuits One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block ... 02/08/07 - 20070033560 - Clock tree adjustable buffer An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The ... 02/01/07 - 20070028199 - Delay computation speed up and incrementality A method of computing output delay in a mathematical model of an integrated circuit original design by sorting cells of the original design in a topological order. The original output delays for the cells in the original design are computed in the sorted order, to produce original output ramp times. ... 01/25/07 - 20070022397 - Apparatus and method for performing static timing analysis of an integrated circuit design using dummy edge modeling An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by creating a dummy clock edge that is on the same edge as ... 01/18/07 - 20070016882 - Sliding window scheme (sws) for determining clock timing in a mesh-based clock architecture In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for ... 01/18/07 - 20070016881 - Automation method and system for assessing timing based on gaussian slack An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values ... 01/11/07 - 20070011634 - Semiconductor testing apparatus Intends to provide semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal to be extracted from data or a time required in adjustment. It includes a timing comparator 154 for receiving data outputted from a DUT 200; a clock generating circuit 120 for generating ... 01/04/07 - 20070006107 - Differential clock ganging Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock ... 01/04/07 - 20070006106 - Method and system for desensitization of chip designs from perturbations affecting timing and manufacturability The system and method disclosed here are directed to desensitization of paths to perturbations resulting from manufacturing faults. A threshold value for signal slew filters out some near-critical paths, and a mathematical formula is applied to determine the appropriate upsize for the cell driving the net along the near-critical path. ... 01/04/07 - 20070006105 - Method and system for synthesis of flip-flops The method of the present disclosure permits the synthesis of any virtual cell by means of an abstraction, including that of an enable flop, full adder, half adder, or multi-stage multiplexer, based on the ability to extract timing information and add a timing margin to account for clock latency. Specifically, ... 12/28/06 - 20060294482 - Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net ... 12/21/06 - 20060288320 - Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The ... 12/21/06 - 20060288319 - Method and system for designing a timing closure of an integrated circuit Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspects further include instantiating one or more smallest repeaters between ... 12/14/06 - 20060282808 - Automatic generation of correct minimal clocking constraints for a semiconductor product A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing ... 12/07/06 - 20060277513 - System and method for incremental statistical timing analysis of digital circuits The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered efficiently, constituting a mode of timing ... 12/07/06 - 20060277512 - Engineering change order process optimization A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff ... 12/07/06 - 20060277511 - System and method for memory element characterization A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed ... 11/30/06 - 20060271893 - Method for isolating problem networks within an integrated circuit design A method of modifying an integrated circuit design. A noise threshold is determined. A threshold, noisy wire length for a particular integrated circuit design is selected. An integrated circuit design is examined for problem networks or wires and all branches that cumulatively equal or exceed the designated threshold noisy wire ... 11/23/06 - 20060265678 - Layout design program, layout design device and layout design method for semiconductor integrated circuit A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step ... 11/09/06 - 20060253823 - Semiconductor integrated circuit and method for designing same The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even ... 11/09/06 - 20060253822 - Semiconductor integrated circuit and method for designing same The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even ... 11/09/06 - 20060253821 - Clock design apparatus and clock design method A clock design apparatus includes a delay time adjusting section, a prohibition specifying section and a clock tree synthesis section. The delay time adjusting section is configured to adjust signal delay time of signal propagation paths on a semiconductor integrated circuit to be designed. The prohibition specifying section is configured ... 11/09/06 - 20060253820 - Methods and apparatus for determining location-based on-chip variation factor Techniques for determining a location-based on-chip variation factor for an integrated circuit device are provided. A first on-chip variation factor is computed for at least one of two or more signal paths of the integrated circuit device. The first on-chip variation factor is a function of a timing delay. A ... 11/02/06 - 20060248487 - A method of optimization of clock gating in integrated circuit designs A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the ... 11/02/06 - 20060248486 - Manufacturing a clock distribution network in an integrated circuit A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the ... 11/02/06 - 20060248485 - Priortizing of nets for coupled noise analysis A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but ... 10/19/06 - 20060236280 - Method and apparatus for analyzing clock-delay, and computer product An input unit receives circuit information on a circuit. A first calculating unit calculates delay-distribution information of a data path and delay-distribution information of a clock path, based on the circuit information. A second calculating unit calculates delay-difference-distribution information between the data path and the clock path by using the ... 10/19/06 - 20060236279 - Design supporting apparatus, design supporting method, and computer product A design supporting apparatus includes a detecting unit that detects a path constituting a circuit from circuit information of the circuit; a sensitivity-equation producing unit that produces a calculating equation for a sensitivity indicating a change rate of a parameter regarding a delay of a circuit element constituting the path, ... 10/19/06 - 20060236278 - Method of automatic generation of micro clock gating for reducing power consumption A method and apparatus for reducing transitions thereby reducing power consumption for a clocked output state-holding element having inputs that are respective logic functions of one or more clocked input state-holding elements. A respective valid line is associated with each of the clocked input state-holding elements whose value indicates whether ... 10/12/06 - 20060230374 - System and method for analyzing crosstalk occurring in a semiconductor integrated circuit A system for analyzing crosstalk occurring in a semiconductor integrated circuit, includes calculating timing windows of first and second wires under a first and second analysis conditions, a sequence determination module determining whether a sequence of the timing windows of the first and second wires interchanges, and an analysis module ... 10/12/06 - 20060230373 - Intelligent timing analysis and constraint generation gui A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The ... 10/05/06 - 20060225014 - Timing analysis method, timing analysis program, and timing analysis tool This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two ... 09/14/06 - 20060206846 - Apparatus and method for verification support, and computer product A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit description information on the object; a specifying unit that specifies at least two ... 09/14/06 - 20060206845 - Hybrid linear wire model approach to tuning transistor widths of circuits with rc interconnect A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes ... 09/07/06 - 20060200786 - Static timing analysis and dynamic simulation for custom and asic designs A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient ... 09/07/06 - 20060200785 - Method and apparatus for the design and analysis of digital circuits with time division multiplexing Methods and apparatuses to design and analyze digital circuits with time division multiplexing. At least one embodiment of the present invention efficiently models subsystems connected by a TDM channel by introducing equivalent delays in the connections for the subsystems, where the delays are determined according to the upper bounds of ... 09/07/06 - 20060200784 - Determining equivalent waveforms for distorted waveforms An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted waveform. The transition quantity is the amount of transition of the first ... 08/31/06 - 20060195807 - Method and system for evaluating timing in an integated circuit Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the ... 08/31/06 - 20060195806 - Method and apparatus for quantifying the timing error induced by an impedance variation of a signal path In one embodiment, a plurality of signals are sequentially driven onto a signal path. Each of the signals has a pulsewidth defined by a trigger edge and a sensor edge, and at least some of the signals having different pulsewidths. After driving each signal, the signal is sampled at or ... 08/31/06 - 20060195805 - Method and apparatus for quantifying the timing error induced by crosstalk between signal paths In one embodiment, each of a plurality of stimulus signals is sequentially driven onto a number of stimulus signal paths. Each of the plurality of stimulus signals has a trigger edge. As each stimulus signal is driven onto the number of stimulus signal paths, a victim signal having a sensor ... 08/24/06 - 20060190886 - Optimizing ic clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting ... 08/24/06 - 20060190885 - Method of displaying delay There is provided a method of displaying calculated delay which can easily grasp the state of the entire logical block and acquire the detailed information on delay violation paths. A display screen has a first window displaying a path delay list of a combination of a source and a sink ... 08/24/06 - 20060190884 - Apparatus and method for analyzing post-layout timing critical paths A critical path detecting unit for detecting critical paths for a design in which cells are placed on an integrated circuit and information concerning timing constraints. A representative-critical-path extracting unit extracts a representative critical path by having one critical path represent critical paths which share more intervals than a certain ... 08/24/06 - 20060190883 - System and method for unfolding/replicating logic paths to facilitate propagation delay modeling A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. ... 08/24/06 - 20060190882 - System and method for generating assertions using waveforms Systems and methods for generating a Hardware Design Language (HDL) assertion from a waveform diagram are disclosed. One method comprises: identifying a timing relationship between first and second signals in the diagram; and generating an HDL assertion corresponding to the relationship. The relationship comprises a portion of the first signal, ... 08/24/06 - 20060190881 - Method for estimating propagation noise based on effective capacitance in an integrated circuit chip A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring ... 08/24/06 - 20060190880 - Output buffer with slew rate control utilizing an inverse process dependent current reference An output driver circuit that provides more constant slew rates in the presence of process, voltage, or temperature variations that affect performance. An open ended (no feedback) solution is utilized that provides more constant slew rates in spite of PVT variations. A first performance dependent current and a reference current ... 08/24/06 - 20060190879 - Frequency dependent timing margin A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference ... 08/24/06 - 20060190878 - Method and circuit arrangement for determining power supply noise The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used ... 08/17/06 - 20060184906 - Method and device for designing semiconductor integrated circuit A method for designing a semiconductor integrated circuit includes steps of (a) to (e). The step (a) is a step of placing a plurality of elements based on circuit data including data of the plurality of elements to be placed on a semiconductor integrated circuit. The step (b) is a ... 07/06/06 - 20060150133 - Integrated circuit (ic) chip design method, program product and system A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the ... 06/22/06 - 20060136853 - Timing skew measurement system An improved timing skew measurement system includes a selector receiving a plurality of input signals whose relative skew is to be measured, a selection controller connected to the select inputs of the selector for selecting one of the input signals and a sequential logic element having a first input connected ... 06/22/06 - 20060136852 - Method and apparatus for mixing static logic with domino logic An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino ... 06/15/06 - 20060129961 - Skew reduction for generated clocks There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets and other related nets. A transformed circuit design may be produced from an initial circuit design and having a reduced number of secondary clocks ... 06/15/06 - 20060129960 - Layout-driven, area-constrained design optimization In one embodiment, a method for layout-driven, area-constrained design optimization includes accessing a design and a layout of the design. The design includes one or more gates and one or more nets coupling the gates to each other. The layout includes blocks that partition a chip area of the design. ... 06/08/06 - 20060123372 - Semiconductor integrated circuit device having clock signal transmission line and wiring method thereof A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal ... 06/08/06 - 20060123371 - Conductor trace design to reduce common mode cross-talk and timing skew A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. ... 06/08/06 - 20060123370 - Method for specification and integration of reusable ip constraints A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode and defining a plurality of hardware-block constraint commands. Each of the plurality of hardware-block constraint commands is categorized into one of the plurality of ... 06/08/06 - 20060123369 - Ramptime propagation on designs with cycles A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set ... 06/08/06 - 20060123368 - Real-time adaptive control for best ic performance The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of ... 06/01/06 - 20060117287 - Method and device for checking a circuit for adherence to set-up and hold times A method and a device for checking a circuit path of a circuit for adherence to set-up and hold times are provided. A timing behavior of the circuit path is designated as being correct if at least one pair of set-up and hold times from predefined set-up and hold times ... 06/01/06 - 20060117286 - Method for correcting timing error when designing semiconductor integrated circuit A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching the tolerance for when a timing error occurs for a cell in each layout block with a worst condition of ... 06/01/06 - 20060117285 - Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same In lower hierarchy design in which a plurality of circuit blocks are independently designed, a reset adjustment circuit propagating deactivation transition of a reset signal to flip-flops in synchronization with a clock signal is inserted immediately after a reset input pin in each circuit block, and timing adjustment using the ... 06/01/06 - 20060117284 - Rram memory timing learning tool A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. ... 05/25/06 - 20060112360 - Layout design method for semiconductor integrated circuits A method of designing a semiconductor integrated circuit creates a net list with cells from a low-threshold-voltage cell library, then arbitrarily replaces some or all of the cells with cells from a high-threshold-voltage cell library. A timing analysis is performed, and if necessary, the net list is further modified by ... 05/25/06 - 20060112359 - Pessimism reduction in crosstalk noise aware static timing analysis Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing ... 05/11/06 - 20060101363 - Method of associating timing violations with critical structures in an integrated circuit design A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing ... 05/11/06 - 20060101362 - Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack ... 05/11/06 - 20060101361 - Slack sensitivity to parameter variation based timing analysis A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, ... 05/04/06 - 20060095879 - Method and apparatus to estimate delay for logic circuit optimization Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first placement information and first delay information to ... 04/27/06 - 20060090150 - Method and apparatus for reducing timing pessimism during static timing analysis One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies ... 04/27/06 - 20060090149 - Simulation testing of digital logic circuit designs A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified ... 04/20/06 - 20060085776 - Method for circuit sensitivity driven parasitic extraction The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive ... 04/20/06 - 20060085775 - System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one ... 04/13/06 - 20060080627 - Crosstalk-aware timing analysis In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, ... 04/13/06 - 20060080626 - Visualization method and apparatus for logic verification and behavioral analysis A logic verification tool detects and flags a logic operation with high probability to cause a fault in an electronic system. An efficient logic debug method utilizes a partial sequence of signal outputs and state transitions to extrapolate a verification result with equivalent robustness to full regression testing. ... 04/06/06 - 20060075367 - Racecheck: a race logic ana,yzer program for digital integrated circuits This invention describes a race logic audit program, RaceCheck, which is unique from the prior arts. Specifically, RaceCheck can perform both static and dynamic race logic analysis, and it works with a plurality of hardware description languages (HDL), which include but not limited to: VHDL, Verilog, SystemVerilog, and SystemC. Furthermore, ... 03/23/06 - 20060064659 - Timing analysis apparatus, timing analysis method, and computer product A timing analysis apparatus includes an data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis from layout data indicating circuits on a large-scale-integration chip; a time calculating unit that calculates a delay time of the objective circuit based on ... 03/23/06 - 20060064658 - Creating a useful skew for an electronic circuit A method of determining a useful skew for a circuit design includes computing a slack value for each sequential cell in the circuit design, identifying modifiable sequential cells in the circuit design, and computing a target delay for each modifiable sequential cell. One or more sequential cells are discarded based ... 03/16/06 - 20060059446 - Sensitivity based statistical timing analysis One disclosed embodiment may comprise a system that includes design data that describes at least a portion of a circuit design. An analysis system determines timing information for a node associated with a first component of the circuit design relative to variations in a parameter associated with at least one ... 03/09/06 - 20060053395 - Clock tree synthesis for low power consumption and low clock skew A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given ... 03/02/06 - 20060048086 - Integrated circuit analysis method and program product A method for analyzing integrated circuits (IC's) has steps of dividing the circuit into a plurality of individual blocks that are linked together. Each block is comprised of a plurality of latches and paths connecting the latches. The blocks are compressed by removing all detail not required for performing global ... 03/02/06 - 20060048085 - Method and system for performing timing analysis on a circuit A method and apparatus for analyzing a circuit are described herein. The circuit may comprise at least two nodes, wherein each of the nodes has timing requirements associated therewith. An embodiment of the method comprises receiving a failure time of first node, wherein the failure time represents the time within ... 03/02/06 - 20060048084 - System and method for repairing timing violations One disclosed method for repairing min-time timing violations comprises receiving a circuit design to analyze, analyzing the circuit design to determine if a min-time timing violation is present in the circuit design, and fixing a determined min-time timing violation by replacing an appropriate element of the circuit design with a ... 02/09/06 - 20060031800 - Design method for semiconductor integrated circuit device A design method for a semiconductor integrated circuit device. For a path having a signal arrival time exceeding a desired value, among paths in the semiconductor integrated circuit device, a path separation is performed so that the number of other components to be connected to the output of a component ... 02/09/06 - 20060031799 - Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing ... 02/09/06 - 20060031798 - Special engineering change order cells A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second ... 02/09/06 - 20060031797 - Method of timing model abstraction for circuits containing simultaneously switching internal signals The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is ... 02/09/06 - 20060031796 - Method for swapping circuits in a metal-only engineering change A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running placement and routing with the new books, and timing the resulting logic. If there are timing ... 02/02/06 - 20060026544 - Variable sigma adjust methodology for static timing The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage ... 02/02/06 - 20060026543 - Accurate timing analysis of integrated circuits when combinatorial logic offers a load The accuracy of timing analysis of an integrated circuit is enhanced based on an observation that the capacitive load offered by a combinatorial element (e.g., logic gate) is more when the value on the output path switches, compared to in a scenario when the output path does not switch. In ... 01/12/06 - 20060010411 - Method for netlist path characteristics extraction A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to ... 01/12/06 - 20060010410 - Genie: a method for classification and graphical display of negative slack timing test failures Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of ... 01/12/06 - 20060010409 - Semiconductor integrated circuit design method, design support system for the same, and delay library In a semiconductor integrated circuit design method for simulating a delay of a logic circuit based on delay values which are calculated for each kind of a plurality of cells composing the logic circuit or for each signal path of the logic circuit and which are stored in a delay ... 01/12/06 - 20060010408 - Placement of a clock signal supply network during design of integrated circuits A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying ... 12/29/05 - 20050289492 - Method of lsi designing and a computer program for designing lsis An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more ... 12/29/05 - 20050289491 - Method and computer program for estimating cell delay from a table with added voltage swing A method and computer program for estimating a cell delay for an integrated circuit design include steps of: (a) selecting a range of values for cell ramptime and load; (b) selecting a range of values for an additional cell parameter; (c) arranging the values for cell ramptime, load, and the ... 12/22/05 - 20050283749 - Dynamic slew rate controlling method and device for reducing variance in simultaneous switching output A dynamic slew rate controlling method and a device is provided to reduce SSO variance generated from voltage noises, which is as a result of a plurality of data bits switching to the same state simultaneously while the I/O bus transmits these data bits. The device and method at first ... 12/22/05 - 20050283748 - Slack value setting method, slack value setting device, and recording medium recording a computer-readable slack value setting program A slack value setting device comprises a worst path selecting section, a first slack value calculating section for calculating slack value set up to each of the transit pins on the worst path, a first slack value setting section for setting up the slack value to each of the transit ... 12/15/05 - 20050278672 - Lsi design method An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design ... 12/15/05 - 20050278671 - Method and system for modeling variation of circuit parameters in delay calculation for timing analysis A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit ... 12/08/05 - 20050273742 - Integrated circuit with dynamically controlled voltage supply An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path ... 12/08/05 - 20050273741 - Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path ... 12/01/05 - 20050268266 - Method and apparatus for analyzing post-layout timing violations A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report ... 12/01/05 - 20050268265 - Metastability effects simulation for a circuit description A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned ... 12/01/05 - 20050268264 - Apparatus and method for calculating crosstalk In a crosstalk calculating method, a basic noise amplitude signal applied to a victim net is determined in a basic noise generation period specified based on a voltage signal transferred on an aggressor net in a semiconductor circuit. First and second signal portions applied to the victim net in first ... 12/01/05 - 20050268263 - Method and apparatus for fixing hold time violations in a circuit design To fix hold time violations, timing analysis is initially performed on a circuit design for each set of timing constraints to determine a setup slack and a hold slack for each signal path for that set of timing constraints. The slack for a signal path indicates the amount of timing ... 11/24/05 - 20050262459 - Automatic tuning of signal timing A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an ... 11/17/05 - 20050257185 - Methods and apparatuses for validating ac i/o loopback tests using delay modeling in rtl simulation Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed ... 11/10/05 - 20050251773 - Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at ... 11/10/05 - 20050251772 - Assuring correct data entry to generate shells for a semiconductor platform A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated circuit. Given a definition of a platform, in part a partially manufactured semiconductor product having some diffused and some configurable ... 11/03/05 - 20050246673 - Method and system for performing static timing analysis on digital electronic circuits A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file ... 10/27/05 - 20050240888 - Multiple propagation speeds of signals in layered circuit apparatus A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed. ... 10/13/05 - 20050229129 - System and method for verifying signal propagation delays of circuit traces of a pcb layout A system for verifying signal propagation delays of circuit traces of a printed circuit board (PCB) layout includes a computer (1). The computer includes: a setting module (10) for setting a minimum propagation delay and a maximum propagation delay for a trace to be verified, and making a selection regarding ... 10/13/05 - 20050229128 - Hierarchical signal integrity analysis using interface logic models Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information ... 10/13/05 - 20050229127 - Method for verifying adequate synchronisation of signals that cross clock environments and system The present invention is directed to methods for verifying adequate synchronisation of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to ... 09/08/05 - 20050198601 - Method for analyzing and validating clock integration properties in circuit systems A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is ... 09/01/05 - 20050193355 - Source synchronous timing extraction, cyclization and sampling A translator tool for translating simulation test data generated to test clock recovery circuitry of a device from an event-based format to a cycle-based format readable by integrated circuit testers is presented. The simulation test data includes test timing irregularities intentionally injected into a serial data signal that will be ... 08/25/05 - 20050188337 - Incremental, assertion-based design verification A design verification system includes a first verification engine to model the operation of a first design of an integrated circuit to obtain verification results including the model's adherence to a property during N time steps of its operation, proofs that one or more verification targets can be reached, and ... 08/18/05 - 20050183051 - Apparatus and method for performing static timing analysis of an integrated circuit design An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by allowing the designer to identify common logic blocks, to compute the difference ... 08/18/05 - 20050183050 - Apparatus and method for performing static timing analysis of an integrated circuit design using dummy edge modeling An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by creating a dummy clock edge that is on the same edge as ... 08/04/05 - 20050172251 - Delta-geometry timing prediction in integrated circuit fabrication Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing ... 08/04/05 - 20050172250 - System and method for providing distributed static timing analysis with merged results Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different ... 07/28/05 - 20050166168 - Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than ... 07/07/05 - 20050149895 - Delay library generation method and delay library generation device A delay library of high accuracy is efficiently generated within a short time period. To this end, a set-up time is calculated by static analysis with no consideration of a delay caused by a wire; the initial value of the search range for the next binary search cycle is set ... 06/30/05 - 20050144580 - Method and system for testing a logic design A method of testing a logic design in one disclosed embodiment includes identifying a plurality of clocked logic elements of a first logic design. The plurality of logic elements is subdivided into M individual groups of elements. A distinct pseudo-clock is assigned to each of the M groups such that ... 06/23/05 - 20050138588 - Current scheduling system and method for optimizing multi-threshold cmos designs This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that ... 06/16/05 - 20050132313 - Optimization of the design of a synchronous digital circuit The design of a synchronous digital circuit (1) can be modified. The circuit comprises a number of clocked storage devices (2, 3, 4, 5,) and a number of combinational logic elements defining combinational paths (6, 7, 8, 9,) between at least some of said clocked storage devices. Each combinational path ... 06/09/05 - 20050125755 - Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and ... 06/02/05 - 20050120319 - Timing closure methodology An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated ... 06/02/05 - 20050120318 - Apparatus and method for designing semiconductor integrated circuit The present invention provides an apparatus for designing a semiconductor integrated circuit, which is capable of satisfying timing constraints without providing BFBs, and improving a convergent property at optimization, and a design method therefor. An LSI automatic design simulator (10) determines the number of clocks employed in a clock generating ... ### FreshPatents.com Support |