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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Testing Or Evaluating > Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width) Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width)Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266354 - Enhanced structural redundancy detection A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a ... 11/01/07 - 20070256040 - Critical area computation of composite fault mechanisms using voronoi diagrams Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes ... 10/25/07 - 20070250799 - Test case generation algorithm for a model checker A method is provided for generating test cases automatically using an abstract system description in combination with a model-checking tool. The abstract system description can be used to design hardware/software systems and the generated test cases can be reused to verify the correctness of the implementation. ... 10/18/07 - 20070245276 - System, method and computer program product for designing connecting terminals of semiconductor device A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O ... 10/04/07 - 20070234250 - Method and apparatus for supporting verification, and computer product A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list; ... 09/27/07 - 20070226663 - Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and ... 09/27/07 - 20070226662 - Method and apparatus of rapid determination of problematic areas in vlsi layout by oriented sliver sampling A method and system for identifying problematic areas in a very large scale integrated (VLSI) layout. The method and system includes defining one or more sample area and overlaying the one or more sample area onto at least a portion of a layout having a plurality of structures. The method ... 09/20/07 - 20070220464 - Method for dynamically adjusting parameter values of part heights to verify distances between parts A method for dynamically adjusting parameter values of part heights to verify the distances between parts is provided. The method comprises, inputting multiple sets of limiting conditions for part heights through a setting interface; and verifying whether the parts are appropriately positioned in a circuit diagram according to the limiting ... 09/20/07 - 20070220463 - Inspection system An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for creating PCB totems for a multi-layer PCB, the display unit is used to display an user interface provided ... 09/20/07 - 20070220462 - Verification of an extracted timing model file A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell ... 09/20/07 - 20070220461 - Method and system for sequential equivalence checking with multiple initial states A method, system and computer program product for performing equivalence checking of a circuit design are disclosed. The method includes importing a first design comprising a first register set and a different second design comprising a second register set and importing a mapping between corresponding initial states of the first ... 09/20/07 - 20070220460 - Method for verifying line information in a layout and system thereof A method for verifying line information in a layout and system thereof are provided. The verification method comprises obtaining and arranging a line data to classify the types of the line data; generating a corresponding line information record file after the line data is classified; sending a message appended with ... 09/20/07 - 20070220459 - Capacitance extraction of intergrated circuits with floating fill The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level ... 09/20/07 - 20070220458 - Method for detecting semiconductor manufacturing conditions A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a ... 09/13/07 - 20070214443 - Circuit verification apparatus, circuit verification method, and signal distribution method for the same A circuit to be verified is divided into a plurality of circuit parts. A plurality of programmable devices are provided for implementing functional operation of the divided circuit parts through a simulation. Wiring used in the circuit to be verified for supplying a signal SX to be given at the ... 09/13/07 - 20070214442 - A method for predicting inductance and self-resonant frequency of a spiral inductor In this invention, a closed-form integral model for on-chip freely suspended rectangular spiral inductor is presented. The model of this invention bases on the Kramers-Kronig relations, field theory, and solid state physics to characterize a spiral inductor which RFIC designers could easily have the optimal design utilizing this analytical method. ... 09/13/07 - 20070214441 - Isolated pwell tank verification using node breakers A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are ... 09/13/07 - 20070214440 - Method for indicating differential signal lines in a layout A method for indicating differential signal lines in a layout is provided, which comprises searching line groups having similar line names at first; dividing the line groups into a first line and a second line; confirming that the first and second lines are connected to a same circuit element; highlighting ... 08/30/07 - 20070204246 - Method and system for logic verification using mirror interface Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost ... 08/30/07 - 20070204244 - Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof A method and a system for validating initial conditions (ICs) generally provided by a user when simulating a VLSI circuit are described. Inconsistent ICs sets are detected and replaced by consistent subsets thereof. The method selects the resistance and source values in a Norton or Thevenin circuit used to enforce ... 08/16/07 - 20070192755 - Apparatus and method to facilitate hierarchical netlist checking An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical ... 08/16/07 - 20070192754 - Method for treating design errors of a layout of an integrated circuit Embodiments of the invention provide a method for treating errors during the checking of a design of an integrated circuit. In one embodiment, the method includes checking the design of the integrated circuit for errors using predetermined design rules, wherein the design includes a plurality of cells, detecting a design ... 08/16/07 - 20070192753 - Technique for generating input stimulus to cover properties not covered in random simulation A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where wherein a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property ... 08/09/07 - 20070186197 - Design verification using formal techniques Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance ... 08/02/07 - 20070180414 - Facilitating structural coverage of a design during design verification One embodiment of the present invention provides a method and a system that facilitates structural coverage of a design during a design verification process. During operation, the system receives a hardware description of the design, which contains one or more module instances and a set of structural coverage targets for ... 08/02/07 - 20070180413 - Chip design verification apparatus and method Chip design verification apparatus and method. The method of verifying the chip design includes a software side operation step of transmitting output data generated by the operation of the software block to the interface means, determining whether the output data of the hardware block received via the interface means is ... 07/26/07 - 20070174799 - Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a ... 07/26/07 - 20070174798 - Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability ... 07/05/07 - 20070157142 - Method for classifying errors in the layout of a semiconductor circuit A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of ... 07/05/07 - 20070157140 - Method and computer program product for trimming the analysis of physical layout versus schematic design comparison A method, a computer program product, and an apparatus for performing a trimmed verification analysis comprising selecting layers of interest for a trimmed analysis, eliminating layer definitions for unselected layers to create a trimmed rundeck, and performing a layout versus schematic verification comparison to generate a trimmed error report for ... 06/21/07 - 20070143721 - System and method for plasma induced modification and improvement of critical dimension uniformity Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved ... 06/21/07 - 20070143720 - A method , apparatus and computer program product for semiconductor yield estimation A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens. ... 06/14/07 - 20070136702 - Semiconductor device layout inspection method An object of the invention is to discover at the chip level a portion of a high density of contact holes in wires of a large area that becomes a portion where wire defects will occur. In order to achieve this, the area ratio of the total area of wires ... 06/14/07 - 20070136701 - Extending incremental verification of circuit design to encompass verification restraints An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint ... 06/07/07 - 20070130551 - Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line ... 06/07/07 - 20070130550 - Semiconductor integrated circuit and design method thereof A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is constituted by a first logic circuit and a second logic circuit. Such semiconductor integrated circuit is designed in ... 05/31/07 - 20070124713 - Logical cad navigation for device characteristics evaluation system A navigation system for easily determining defective positions is provided. In the case of CAD navigation to defective positions, logical information for indicating defective positions is created in a CAD format, instead of CAD data of physical information indicating circuit design. Specifically, by attaching marks such as rectangles, characters, or ... 05/31/07 - 20070124712 - Auxiliary method for circuit design For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification ... 05/31/07 - 20070124711 - Multithreaded reachability In one embodiment, a method for multithreaded reachability analysis includes partitioning a state space of a circuit under analysis into a plurality of partitions and assigning each partition to a thread to carry out a reachability analysis on the partition assigned to the thread. The threads carry out the reachability ... 05/31/07 - 20070124710 - Timing analyzer apparatus and timing analysis program recording medium By multiplying a square root of a sum of squares of a standard deviation of cells constituting a target circuit by a weight, or by calculating a square root of a sum of squares of a weighted standard deviation of the cells, the standard deviation of delay of the target ... 05/31/07 - 20070124709 - Method and system for design rule checking for an sip device A method for checking design rules in an SiP (system in a package) design environment is provided. The method uses a commercial computer aided design tool to design and layout out an SiP, that is, to create a design database for the SiP. In the database, characteristics may be assigned ... 05/24/07 - 20070118824 - Methods, systems, and computer program products for improving yield in integrated circuit device fabrication and related devices A method of improving yield in integrated circuit device fabrication includes calculating a fault rate for a design rule based on a plurality failure rates for a corresponding plurality of Design Of Experiment (DOE) rule values and based on numbers of features in a layout of interest corresponding to ones ... 05/24/07 - 20070118823 - Method and system for automatically checking traces in segments A method and system for automatically checking traces of a differential pair in segments in a printed circuit board (PCB) layout is proposed. A setting module sets a tolerance of length difference. A checking module segments the differential pair into a plurality of segments at places where the slopes thereof ... 05/17/07 - 20070113210 - Method and apparatus for supporting verification, and computer product In gates, a gate length is same as that of an isolated Poly on a layout, however, is different from that of the isolated Poly on an actual silicon wafer. When the distance between the gates that is spacing between the gate becomes larger to some degree, the proximity effect ... 05/03/07 - 20070101303 - Method and apparatus for integrated circuit layout optimization A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries include i) to ensure the design intent is faithfully transferred onto silicon; ii) to ensure the design is manufacturable, or with acceptable yield subject ... 04/26/07 - 20070094625 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to ... 04/26/07 - 20070094624 - Semiconductor device and method for providing a reduced surface area electrode An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach ... 04/12/07 - 20070083834 - Method for sram bitmap verification A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is intentionally created in the physical layout. Then, the ... 04/12/07 - 20070083833 - Method to implement metal fill during integrated circuit design and layout Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a ... 04/05/07 - 20070079270 - Circuit design method, circuit design system, and program for causing computer to perform circuit design In a circuit design method, a computer verifies an occurrence of a noise error, specifies a noise allowable value with respect to a cell at which it is determined that the noise error occurs, and determines a parameter value used in a process step. The parameter value satisfies the noise ... 04/05/07 - 20070079269 - Method for performing design rule check of integrated circuit The present invention provides a method for performing design rule check (DRC) of an integrated circuit. A design layout of the integrated circuit is provided. The integrated circuit includes a complex circuit. A DRC tool is used to compare a portion of the design layout with a reference layout containing ... 04/05/07 - 20070079268 - Mixed mode verifier A method and system for formally verifying designs having elements from more than a single design domain is described. For example, an example system allows formal verification of a design containing mixed analog and digital design. ... 04/05/07 - 20070079267 - Multi-format consistency checking tool A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule ... 04/05/07 - 20070079266 - Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving ... 04/05/07 - 20070079265 - Accurate noise modeling in digital designs A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters ... 04/05/07 - 20070079264 - Reducing time to design integrated circuits including performing electro-migration check The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path ... 03/29/07 - 20070074137 - Database and method of verifying function of lsi using the same Provided is a method of verifying the function of the LSI including: a first signal database generating step of registering a first signal data set for associating a first verification target signal of which the operation is defined as the specification of the LSI with a first depended signal group ... 03/29/07 - 20070074136 - Using constraints in design verification A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which ... 03/29/07 - 20070074135 - Circuit design verification using checkpointing A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed splits, and N non-checkpointed splits; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, . ... 03/22/07 - 20070067747 - Substrate noise tool System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, ... 03/22/07 - 20070067746 - Method and system for performing heuristic constraint simplification A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state ... 03/15/07 - 20070061766 - Method and system for performing target enlargement in the presence of constraints A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers ... 03/15/07 - 20070061765 - Method and system for case-splitting on nodes in a symbolic simulation framework A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the ... 03/15/07 - 20070061764 - Keyword-based connectivity verification Keyword-based verification of proper connectivity of a circuit design including a plurality of cells is disclosed. In one embodiment, a method includes assigning a keyword to each relevant pin of the circuit design, the keyword indicates a verification rule for a domain starting at the relevant pin; tracing the domain ... 03/01/07 - 20070050741 - Pattern verification method, program thereof, and manufacturing method of semiconductor device A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit ... 03/01/07 - 20070050740 - Method and system for performing functional formal verification of logic circuits The present invention relates to a method, a computer program product and a system for performing functional formal verification. Error detection logic is verified by injecting errors in a hardware design description without any changes to the original design description. With the present invention both permanent and transient faults can ... 03/01/07 - 20070050739 - Method and system for performing verification of logic circuits The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional ... 03/01/07 - 20070050738 - Customer designed interposer A method and system that provides a customer with the ability to design an electrical connector (interposer) that is individualized to the customer's particular application requirements. An interface to a design program providing a plurality of design options is provided to the customer to aid in designing an interposer. A ... 02/22/07 - 20070044052 - Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect A method of verifying the power off effect of a design entity of a digital system includes a device model, a test input signal model, and a test output signal model specified in a hardware design language, at a register transfer level (RTL). The device model describes function blocks for ... 02/22/07 - 20070044051 - Method and system for validating a hierarchical simulation database System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit ... 02/08/07 - 20070033559 - Method for using layout regions to predict single-event effects A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having ... 02/08/07 - 20070033558 - Method and system for reshaping metal wires in vlsi design A method and system for representing metal wires in Very Large Scale Integration (VLSI) circuit design in a simplified form. A pair of metal wires is considered at a time. A plurality of Piece Wise Linear (PWL) equations is created to represent sides each of the pair of metal wires. ... 02/08/07 - 20070033557 - Method for creating constraints for integrated circuit design closure A method for creating constraints for integrated circuit design closure is provided. Design specifications are captured before a design flow is started. The design specifications are checked for compatibility with the design flow. The design specifications are stored in a database. Output transforms are applied to the design specifications to ... 02/08/07 - 20070033556 - Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. ... 02/08/07 - 20070033555 - Reliability analysis of integrated circuits Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, ... 01/25/07 - 20070022396 - Method and apparatus for expanded data rate control indices in a wire less communication system In one embodiment, the patent application comprises an apparatus, method and means for expanding DRC indices comprising assigning multiple DRC covers to at least one sector. In another embodiment, the apparatus, method and means for expanding DRC indices further comprises creating an expanded DRC indices list, sending a mapping of ... 01/25/07 - 20070022395 - Power estimation employing cycle-accurate functional descriptions A method for estimating the power consumption of an electronic circuit under design that employs a Cycle-Accurate Functional Description (CAFD) which advantageously provides the accuracy achieved by RTL power estimation with the speed and speed of higher-level approaches. ... 01/25/07 - 20070022394 - Estimating the difficulty level of a formal verification problem Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for each property on the design. A property verifiability metric value is established for each property in accordance with the verification processes, where ... 01/18/07 - 20070016880 - Apparatus and method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test ... 01/11/07 - 20070011633 - Method and system for performing functional verification of logic circuits A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a ... 01/11/07 - 20070011632 - System and method for comparing two circuit designs A method for comparing a new circuit design with a corresponding old circuit design is disclosed. The method includes the steps of: creating two components attributes documentations according to a new circuit design and a corresponding old circuit design; receiving the two components attributes documentations; comparing the two components attributes ... 01/11/07 - 20070011631 - Harnessing machine learning to improve the success rate of stimuli generation Test generation is improved by learning the relationship between an initial state vector for a stimuli generator and generation success. A stimuli generator for a design-under-verification is provided with information about the success probabilities of potential assignments to an initial state bit vector. Selection of initial states according to the ... 01/11/07 - 20070011630 - Methods for computing miller-factor using coupled peak noise A method for computing a Miller-factor compensated for peak noise is provided. The method includes mapping at least two delays as a function of at least two Miller-factors; determining an equation of the function; computing a peak noise; computing a peak delay resulting from the peak noise; and computing the ... 12/28/06 - 20060294481 - Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the ... 12/21/06 - 20060288318 - Method and apparatus for associating an error in a layout with a cell One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target feature with an intended shape. Next, the system determines an error in a critical dimension of the ... 12/21/06 - 20060288317 - Element arrangement check device and printed circuit board design system An element placement check system for checking element placement on a printed wiring board having wiring by which a power supply terminal of an integrated circuit and a power supply decoupling element for the power supply terminal are connected on a mounting surface on which the integrated circuit is mounted, ... 12/14/06 - 20060282807 - Software verification A system and method is disclosed for formal verification of software programs that advantageously improves performance of an abstraction-refinement loop in the verification system. ... 12/14/06 - 20060282806 - Software verification using range analysis A system and method is disclosed for formal verification of software programs that advantageously bounds the ranges of values that a variable in the software can take during runtime. ... 12/14/06 - 20060282805 - Method for verifying a circuit design by assigning numerical values to inputs of the circuit design A method for verifying a circuit design comprises a step of assigning numerical values 1/ai to input ports of the circuit design according to a function ai+1=(ai−1)2+1, wherein represents the number of the input port and the numerical value a1 is not equal to 2 or 1. Preferably, a1 is ... 12/07/06 - 20060277510 - Verification support device, verification support method, and computer product A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design object in a chronological order. A diagram extracting unit extracts the modified sequence diagrams. A modified process detecting unit detects modified processes by comparing ... 12/07/06 - 20060277509 - System and method for analyzing power consumption of electronic design undergoing emulation or hardware based simulation acceleration The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the ... 12/07/06 - 20060277508 - Method and system for enhanced verification through binary decision diagram-based target decomposition A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is ... 12/07/06 - 20060277507 - Method and system for enhanced verification through structural target decomposition A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more ... 11/30/06 - 20060271892 - System and method for automated electronic device design A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher quality of results. Such a system as analysis methods, techniques, and tools, a knowledge database, a design database a controller and ... 11/30/06 - 20060271891 - Method and apparatus for rapid electromagnetic analysis A method and apparatus for performing an electromagnetic analysis of an electrical circuit. One or more super-sections are each defined as electromagnetically isolated portions of an electrical circuit that can be analyzed and processed in parallel. Optionally and preferably, at least some of the super-sections are defined to overlap each ... 11/30/06 - 20060271890 - Systems, methods, and media for block-based assertion generation, qualification and analysis Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session preferences including a selection of one or more assertion schemas for use in generating the assertions, ... 11/30/06 - 20060271889 - Method of finding driving strength and computer accessible record medium to store program thereof A method of finding a driving strength and a record medium accessible by a computer to store a program thereof are provided. The method is adapted to find the driving strength of an output pin of a target cell. Wherein, the driving strength of the output pin of the target ... 11/23/06 - 20060265677 - Method and system for increased accuracy for extraction of electrical parameters An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate ... 11/23/06 - 20060265676 - Method and apparatus for verifying specification, and computer product An apparatus for verifying a specification includes a use-case extracting unit, a first setting unit, an operation extracting unit, a second setting unit, and a determining unit. The use-case extracting unit extracts an unprocessed use case from specification data. The first setting unit sets a condition based on a precondition, ... 11/23/06 - 20060265675 - Verifying an ic layout in individual regions and combining results When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across ... 11/16/06 - 20060259884 - Merging a hardware design language source file with a separate assertion file A method is provided for merging assertions in one input file with hardware description language (HDL) code in another input file to produce an HDL output file. One embodiment, among others, comprises the steps of: copying an assertion identified by an assertion identifier from the first input file; locating a ... 11/16/06 - 20060259883 - Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator ... 11/16/06 - 20060259882 - System and method for manipulating an integrated circuit layout A system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating ... 11/09/06 - 20060253819 - Design checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first ... 11/09/06 - 20060253818 - Design checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first ... 11/09/06 - 20060253817 - Checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first ... 11/09/06 - 20060253816 - Apparatus and method for memory efficient, programmable, pattern matching finite state machine hardware A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored ... 11/09/06 - 20060253815 - Phase abstraction for formal verification A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create ... 11/09/06 - 20060253814 - Method and apparatus for fixing hold time violations in a hierarchical integrated circuit design A method and apparatus is presented for introducing delay compensation elements into a circuit design at the top level of the circuit design. In one embodiment, failing circuit paths are identified and grouped based on buffers that can be used to compensate for the failure in the circuit path. The ... 11/09/06 - 20060253813 - Design rule violations check (drc) of ic's (integrated circuits) mask layout database, via the internet method and computer software This paper describes method and EDA (Electronic Data Automation) computer software invention for design rule violations check of mask layout database (integrated circuits layout) via the internet. The technique takes advantage of a unique algorithm to analyze the mask layout database to find mask layout polygons that are less than ... 10/26/06 - 20060242612 - A crosstalk checking method using paralled line length extraction In a parallel line length extracting procedure, a layout and a reference value per pitch describing a restriction value of a parallel line length different according to a line pitch are input, thereby extracting the parallel line length between adjacent lines. In a parallel line length checking procedure per pitch, ... 10/19/06 - 20060236277 - Method, apparatus, and computer program product for implementing vertically coupled noise control through a mesh plane in an electronic package design A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically ... 10/19/06 - 20060236276 - System and method for evaluating signal coupling between differential traces in a package design A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the ... 10/12/06 - 20060230372 - Device and method for testing an electric circuit A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein ... 10/12/06 - 20060230371 - Alternative methodology for defect simulation and system A system for defect simulation is provided. A defect layout generator generates a defect layout comprising a given number of spot defects of a given size. A processor first compares the defect layout and a provided circuit layout comprising a plurality of conductive regions. The processor further determines whether the ... 10/12/06 - 20060230370 - System and method for engine-controlled case splitting within a multiple-engine based verification framework A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of verification engines divides the verification problem into a set of partitions and passes at least one of the ... 10/05/06 - 20060225013 - Method of designing semiconductor integrated circuit and apparatus for designing the same A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether ... 10/05/06 - 20060225012 - Layout verification method and layout design unit By providing plural layers in which circuit components of an integrated circuit using plural voltages are arranged in accordance with used voltages, separately arranging the circuit component to which a high voltage is applied in a specific layer among the plural layers, recognizing the used voltage for each layer, and ... 10/05/06 - 20060225011 - Method of tiling analog circuits The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in ... 09/28/06 - 20060218514 - Power supply analysis method and program product for executing the same A method of power supply analysis includes the steps of dividing a package substrate to which a semiconductor device is mounted into a plurality of first area, specifying virtual flat plate conductors to correspond to the plurality of the first areas, calculating a plurality of electrical properties including inductance characteristics ... 09/28/06 - 20060218513 - Dynamically interleaving randomly generated test-cases for functional verification The input for a test generator is a plurality of test templates, each of which typically aims at covering a specific verification task. Test templates direct the production of distinct transactions, which are the atomic functional building blocks of the design-under-verification. Test templates directed to different hardware functions of the ... 09/21/06 - 20060212837 - System and method for verifying a digital design using dynamic abstraction A method for verifying a digital system design is provided. A first abstraction of a digital system design is performed to obtain an abstract model of the digital system design. One or more first steps of a multiple-step model checking process are performed using the abstract model, the multiple-step model ... 09/14/06 - 20060206844 - Crosstalk error control apparatus, method, and program A crosstalk error controller includes a crosstalk analyzer for detecting a crosstalk error net in which a crosstalk error has occurred, a noise source detector for detecting noise source nets being noise sources to the crosstalk error net, and a reducing unit for lowering a signal level of a noise ... 09/14/06 - 20060206843 - Probabilistic noise analysis A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design ... 09/14/06 - 20060206842 - Method for retiming in the presence of verification constraints A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming ... 09/14/06 - 20060206841 - Method and apparatus for computing equivalent capacitance One embodiment of the present invention provides a system that estimates the equivalent capacitances for a set of conductors within an electrical structure. During operation, the system constructs a Gaussian surface that encloses a first conductor, but does not contain any other conductor. The system then computes the equivalent capacitance ... 09/14/06 - 20060206840 - Systems and methods for design verification using selectively enabled checkers Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the identified characteristics are used to selectively enable checker modules needed to verify the characteristics implicated by the test cases, ... 09/07/06 - 20060200783 - Decoupling capacitance analysis method This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable ... 08/24/06 - 20060190877 - Decoupling capacitance analysis method This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable ... 08/24/06 - 20060190876 - Semiconductor device design system and method, and software product for the same A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured ... 08/24/06 - 20060190875 - Pattern extracting system, method for extracting measuring points, method for extracting patterns, and computer program product for extracting patterns A pattern extracting system includes a sampler configured to sample test candidate patterns from a circuit pattern, based on a lithographic process tolerance, a space classification module configured to classify the test candidate patterns into space distance groups depending on a space distance to an adjacent pattern, a density classification ... 08/24/06 - 20060190874 - Method and system for formal unidirectional bus verification A method, system and computer program product for performing verification is disclosed. A high-level description of a design is created and constrained drivers are synthesized from the high-level description of the design. A testbench is generated from the high-level description of the design and the constrained drivers and a formal ... 08/24/06 - 20060190873 - Exploiting suspected redundancy for enhanced design verification A verification method foe an integrated circuit includes identifying an equivalence class including a set of candidate gates suspected of exhibiting equivalent behavior and identifying one of the candidate gates as a representative gate for the equivalence class. Equivalence gates of an XOR gate are sourced by the representative gate ... 08/24/06 - 20060190872 - System and method for signal integrity testing of electronic circuits A system and method are disclosed for measuring signal crosstalk in an electronic circuit device or Integrated Circuit (IC) device, correlating the results with modeled information, and accurately identifying one or more levels of coupling noise in the device. For example, a system is disclosed that provides data on levels ... 08/24/06 - 20060190871 - Methods, systems and media for managing functional verification of a parameterizable design Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the ... 08/24/06 - 20060190870 - Latch modeling technique for formal verification A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using ... 08/24/06 - 20060190869 - Design verification using sequential and combinational transformations System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded ... 08/24/06 - 20060190868 - Method and system for optimized handling of constraints during symbolic simulation A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more ... 08/24/06 - 20060190867 - Method for reconfiguration of random biases in a synthesized design without recompilation A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion ... 08/24/06 - 20060190866 - Resistance extraction for hierarchical circuit artwork In one embodiment, a method is disclosed for extracting resistance from hierarchical circuit artwork having parent and child circuit blocks. In accordance with the method, and for each child block, at least one portion of signal trace artwork to which a parent circuit block may connect is identified; the identified ... 08/24/06 - 20060190865 - Quantified boolean formula (qbf) solver Quantified Boolean formula (QBF) techniques are used in determining QBF satisfiability. A QBF is broken into component parts that are analyzable by a satisfiability (SAT) solver. Each component is then independently, and perhaps in parallel, analyzed for satisfiability. If a component is unsatisfiable, then it is determined that the QBF ... 08/24/06 - 20060190864 - Efficient modeling of embedded memories in bounded memory checking A computer-implemented method for augmenting SAT-based BMC to handle embedded memory designs without explicitly modeling memory bits. As is known, verifying designs having large embedded memories is typically handled by abstracting out (over-approximating) the memories. Such abstraction is not useful for finding real bugs. SAT-based BMC, as of now, is ... 08/17/06 - 20060184905 - Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal ... 07/27/06 - 20060168551 - Integrated circuit having a multi-layer structure and design method thereof An integrated circuit has a multi-layer wiring structure formed on a substrate. The integrated circuit comprises wiring patterns provided to multiple wiring layers so as to extend as signal paths in generally the same direction in a manner in which the images of the wiring patterns projected onto the substrate ... 07/13/06 - 20060156264 - Method and apparatus for supporting verification of system, and computer product In a verification support apparatus, an input unit accepts input of an unverified specification description representing an unverified design object constituted by unverified model elements. A searching unit searches, from verified specification descriptions representing verified design objects constituted by verified model elements, a verified specification description identical or similar to ... 07/13/06 - 20060156263 - Method for designing semiconductor device and method for evaluating reliability thereof A semiconductor device 100 has a configuration having a via 124 formed on a first interconnect 112. A method for designing the semiconductor device 100 includes: calculating an anticipated value xopen of a dimension of a growing region of a void 150 expanding in a stress induced voiding (SIV)-ensured time ... 07/13/06 - 20060156262 - Method and apparatus for supporting verification, and computer product A verification supporting apparatus includes an acquiring unit that acquires a first verification-item list for a verification target, a functional specification of the verification target, and a sequential specification of the verification target; a keyword extracting unit that extracts a keyword about the verification target from the first verification-item list; ... 07/13/06 - 20060156261 - Design verification technique A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in impact checker to determine the impact of portions of the design on the operation of the design. ... 07/06/06 - 20060150132 - Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit The present invention provides a method and a system for designing an integrated circuit comprising a plurality of elements. The method includes obtaining a lithography-simulated layout corresponding to at least one element. The lithography-simulated layout accounts for lithography effects on the element. The method further includes determination of an equivalent ... 07/06/06 - 20060150131 - Method for generating design rules for a lithographic mask design that includes long range flare effects A method is described for computing distance based and pattern density based design rules for the mask layout design of a VLSI chip so that the design satisfying the above design rules when manufactured on a wafer do not violate the specified tolerance on the critical dimensions (CD). The design ... 07/06/06 - 20060150130 - Integrated circuit yield enhancement using voronoi diagrams A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said ... 06/29/06 - 20060143585 - Method of designing a semiconductor integrated circuit In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power ... 06/29/06 - 20060143584 - Method and device of analyzing crosstalk effects in an electronic device For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an output of the victim net with respect to ... 06/22/06 - 20060136851 - Method for the generation of static noise check data In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and DA, when a plurality of cores, comprising the same sub-chips, are present, the static noise check data for the whole chip is ... 06/22/06 - 20060136850 - Method of parasitic extraction from a previously calculated capacitance solution A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated ... 06/15/06 - 20060129959 - Abstraction refinement using controllability and cooperativeness analysis One embodiment of the present invention provides a system that refines an abstract model. Note that abstraction refinement is commonly used in formal property verification. During operation, the system receives an abstract model which is a subset of a logic design which can be represented using a set of variables ... 06/15/06 - 20060129958 - Method for verification using reachability overapproximation A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is ... 06/08/06 - 20060123367 - Semiconductor integrated device, method of designing semiconductor integrated device, device for designing the same, and program A semiconductor integrated device has a wire layout structure such that SL1≦SL2<SL3 wherein a minimum wiring space in a location where both of neighboring wires are fine wires is SL1, a minimum wiring space in a location where at least one of neighboring wires is a wide wire and the ... 06/08/06 - 20060123366 - Method and program for designing semiconductor device It is an object of the present invention to provide a semiconductor device design method and program that can rapidly improve power supply noise characteristics and reduce the noise sufficiently without being restricted in design and noise solution. A step of performing frequency analysis on a power supply distribution network ... 06/01/06 - 20060117283 - Integrated circuit verification method, verification apparatus, and verification program A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical information on routing of the input/output buffer into a library of the input/output buffer and verifies a placement of the input/output buffer ... 06/01/06 - 20060117282 - Method that allows flexible evaluation of power-gated circuits A method and a design automation tool are provided for use in conjunction with designing logic circuits that implement virtual power signals. The method includes providing in a model for each virtual power signal an attribute that distinguishes the virtual power signal from both a logic signal and a power ... 06/01/06 - 20060117281 - Verification of rram tiling netlist The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground ... 05/18/06 - 20060107246 - Designing method for high-frequency transistor and high-frequency transistor having multi-finger gate The present invention provides a designing method for a high-frequency transistor, which includes a transistor section, a drain region, and a gate electrode, a source wiring line, a drain wiring line, and a gate wiring line, for optimizing wiring lines and contacts from voltage supplying nodes to electrode lead nodes. ... 05/18/06 - 20060107245 - System and method for suppressing crosstalk glitch in digital circuits A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net ... 05/11/06 - 20060101360 - Systems and methods of simulating signal coupling Systems and methods for simulating signal coupling in electronic devices are disclosed. In an exemplary implementation a computer program product executes a computer process to simulate a victim signal having a toggling bit pattern relative to a quiet culprit signal. The process also simulates a culprit signal having a toggling ... 05/11/06 - 20060101359 - Method and device for verifying digital circuits For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of ... 05/04/06 - 20060095878 - Method and system for design verification of video processing systems with unbalanced data flow In a video system, a method and system for design verification of video processing systems with unbalanced data flow are provided. Efficient design verification may be provided for multi-field video processors with separate control data flow and video data flow. A design verification architecture may utilize a reference model to ... 05/04/06 - 20060095877 - Fast evaluation of average critical area for ic layouts Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of ... 04/27/06 - 20060090148 - Wide geometry recognition by using circle-tangent variable spacing model Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A ... 04/20/06 - 20060085774 - Method and apparatus for evaluating and debugging assertions Roughly described, assertion expressions are evaluated against the binary signal values of a circuit simulation in such a way as to be able to report status information at intermediate levels of assertion subexpressions. In one embodiment, the status information reported for an intermediate subexpressions contains the final status of that ... 04/13/06 - 20060080625 - Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test ... 03/23/06 - 20060064657 - Layout verification method and device There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the ... 03/23/06 - 20060064656 - Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks ... 03/16/06 - 20060059445 - Method of designing wiring structure of semiconductor device and wiring structure designed accordingly The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure. ... // - 2 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... 03/16/06 - 20060059444 - High level validation of designs and products A method for high level validation of a design includes receiving input associated with a design; generating a message diagram in response to the input, wherein the message diagram describes a relationship of messages communicated between multiple processes; resolving at least one scenario from the message diagram, wherein the scenario ... 03/09/06 - 20060053394 - Method and apparatus for estimating parasitic capacitance One embodiment of the present invention provides a system for estimating parasitic capacitance for an integrated circuit. During operation, the system reads a technology file, which describes the composition of a vertical cross-section of the integrated circuit. Next, the system reads a design file, which specifies the layout of the ... 03/02/06 - 20060048083 - Chip development system enabled for the handling of multi-level circuit design data A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be ... 03/02/06 - 20060048082 - Test-cases for functional verification of system-level interconnect Generation of test cases for functional verification of a complex system-under-test is achieved by the use of a probability matrix. The probability matrix represents a non-uniform distribution function of resource combinations used in the transactions, and can be created randomly, or by application of various types of testing knowledge. The ... 02/16/06 - 20060036984 - Device and method for extracting parasitic capacitance of semiconductor circuit A device for extracting parasitic capacitance including the influence of a dummy metal pattern inserted between the circuit wires of a semiconductor device comprises a permittivity correction unit for correcting the permittivity of a dielectric existing between the circuit wires in accordance with the insertion of the dummy metal and ... 02/16/06 - 20060036983 - Logic verification device, logic verification method, and computer product A logical verification device includes an input unit, a generator, an input constraint information calculator, an output constraint information calculator, an input/output constraint information calculator, a determining unit, and a logic verifying unit. The input unit inputs hardware description information and interface specification description information concerning a communication procedure of ... 02/16/06 - 20060036982 - Method and apparatus for detecting nets physically changed and electrically affected by design eco A method for detecting nets physically changed and electrically affected by a design ECO includes steps as follows. An ECO is executed on an IC design to produce a post-ECO IC design. A first group of nets of the IC design physically changed by the ECO is identified by comparing ... 02/09/06 - 20060031795 - Methods and apparatuses for transient analyses of circuits Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group ... 01/19/06 - 20060015834 - Method for correcting crosstalk In a semiconductor integrated circuit, there is provided a method for correcting crosstalk, which exerts an influence via coupling capacitance between wiring by the signal transitions between adjacent wiring, comprising the step of creating a candidate for buffer division, the step of creating a candidate for cell movement, or the ... 01/19/06 - 20060015833 - System and method for verifying trace lengths and trace spaces in a circuit The present invention provides a method for verifying trace lengths and trace spaces in a circuit. The method includes the steps of: retrieving information of a trace layout of the circuit; retrieving preset design rules on the trace lengths and the trace spaces of the trace layout; computing trace lengths ... 01/12/06 - 20060010407 - System and method for operation verification of semiconductor integrated circuit A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout ... 01/12/06 - 20060010406 - Method of verification of estimating crosstalk noise in coupled rlc interconnects with distributed line in nanometer integrated circuits A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform ... 01/05/06 - 20060005154 - Integrated opc verification tool An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification components (e.g., layout versus schematic, design rule check, optical process correction, ... 01/05/06 - 20060005153 - Device, method and program for estimating the number of layers of bga component mounting substrate To estimate the number of layers required for drawing wirings out of a BGA component at a high speed. A layer number estimation device includes: a bottleneck line detection means, a wiring layer adding means, and a repeating means. The bottleneck line detection means detects a line as a bottleneck ... 12/15/05 - 20050278670 - Mechanical-electrical template based method and apparatus A method and apparatus for identifying sections of an existing schematic that are consistent with best design practices, the method comprising the steps of providing a template set, each template specifying a sub-set of components and relationships that are consistent with best design practices and examining the existing schematic to ... 12/15/05 - 20050278669 - Invariant checking In one embodiment, a method for invariant checking includes executing one or more first steps of a finite state machine (FSM) corresponding to one or more binary decision diagrams (BDDs) to traverse a state space of the FSM in a first direction with respect to an initial state and an ... 12/15/05 - 20050278668 - Method of estimating crosstalk noise in lumped rlc coupled interconnects A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects is provided. In the invention, high-speed VLSI interconnects are modeled as lumped RLC coupled trees. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the ... 12/08/05 - 20050273740 - Program, method and apparatus for analyzing transmission signals From design information on a circuit board a wiring designation unit designates a wiring model for signal analysi |