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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Testing Or Evaluating Testing Or EvaluatingTesting Or Evaluating patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266353 - Predictive event scheduling in an iterative resolution network A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. ... 11/15/07 - 20070266351 - Method and system for evaluating computer program tests by means of mutation analysis The invention relates to a method and system for evaluating computer program tests by means of mutation analysis. The inventive method comprises the execution (F7) of mutated programs (Pj) with the insertion (F1) of mutations (Mj) and the identification (F12) of mutated programs (Pj) which, with a pre-determined test (Tk), ... 11/15/07 - 20070266350 - Microwave circuit performance optimization by on-chip digital distribution of operating set-point A method and circuit are outlined allowing the performance of an RF circuit to be established through the use of digital calibration data, which is stored within a programmable memory store and used to establish the control signal inputs of the RF circuit elements. ... 11/15/07 - 20070266349 - Directed random verification A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested coverage event, and finds a logical, deterministic crossover point between at least two test cases. Once a ... 11/08/07 - 20070261011 - Modeling small mosfets using ensemble devices A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The method creates synthetic single finger data using the scaled simulation. The method physically measures ... 11/01/07 - 20070256039 - Dummy fill for integrated circuits Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by ... 10/25/07 - 20070250798 - Method and apparatus in locating clock gating opportunities within a very large scale integration chip design A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The ... 10/18/07 - 20070245274 - Integrated circuit design apparatus and method thereof An integrated circuit apparatus according to an aspect of the present invention includes: an input portion for inputting information on a physical form relating to a wiring and an element which are desired out of first schematic data as physical form information on the wiring and the element; a schematic ... 10/11/07 - 20070240086 - Range pattern definition of susceptibility of layout regions to fabrication issues A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at ... 10/11/07 - 20070240085 - Method for computing the sensitivity of a vlsi design to both random and systematic defects using a critical area analysis tool A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method ... 10/04/07 - 20070234247 - Automatic test component generation and inclusion into simulation testbench Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the ... 10/04/07 - 20070234246 - Identifying layout regions susceptible to fabrication issues by using range patterns A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside ... 10/04/07 - 20070234245 - Sub-system power noise suppression design procedure Aspects of the disclosure provide methods and systems to design a distributed discrete capacitor bank incorporating power plane capacitance to concentrate the suppression of AC coupling to the frequencies caused by clocks and signal transitions. Aspects of the disclosure provide a procedure for designing a distributed capacitor bank from a ... 09/20/07 - 20070220456 - On-chip test circuit and method for testing of system-on-chip (soc) integrated circuits A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command includes an operation code component, data component(s), and expected time component. The received operation command is processed to supply ... 09/20/07 - 20070220455 - Method and computer program for efficient cell failure rate estimation in cell arrays A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a ... 09/20/07 - 20070220454 - Analyzing structural design relative to vibrational and/or acoustic loading A computer-performed method of designing a structure. User-selected design parameters are input to a parametric model of the structure. Boundary conditions and load conditions are applied to the model to determine a response of the structure to the conditions. Based on the load conditions, an analysis method is selected. The ... 09/13/07 - 20070214439 - Methods of deriving switch networks A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as ... 09/13/07 - 20070214438 - Method for static power characterization of an integrated circuit A method for static power characterization of an analog integrated circuit includes detecting whether each of a plurality of input pins is electrically connected to a specific circuit; selecting a plurality of test benches of the static power characterization according to a number of the input pins electrically connected to ... 09/06/07 - 20070209027 - Simulation method for semiconductor circuit device and simulator for semiconductor circuit device A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias gate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. ... 09/06/07 - 20070209026 - Identifying parasitic diode(s) in an integrated circuit physical design A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction ... 08/30/07 - 20070204243 - Stress analysis method, wiring structure design method, program, and semiconductor device production method A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area ... 08/23/07 - 20070198959 - Hardware-based hdl code coverage and design analysis Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the ... 08/16/07 - 20070192752 - Influence-based circuit design An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is ... 08/09/07 - 20070186195 - Method and system for debugging using replicated logic and trigger logic A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of ... 08/02/07 - 20070180411 - Method and apparatus for comparing semiconductor-related technical systems characterized by statistical data A method and an apparatus are provided for comparing a first semiconductor-related technical system with a second semiconductor-related technical system using statistical means. First statistical data characterizing the first technical system and second statistical data characterizing the second technical system are provided. A statistical test comparing the first statistical data ... 07/26/07 - 20070174797 - Predicting ic manufacturing yield by considering both systematic and random intra-die process variations One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for ... 07/26/07 - 20070174796 - Deflection analysis system and method for circuit design A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated ... 07/19/07 - 20070168895 - Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit An automatic design method of a semiconductor integrated circuit includes: increasing an interval between a plurality of wiring patterns provided on a chip region to relieve a density of the wiring patterns based on first reference information including a criterion about a restriction of wiring length and second reference information ... 07/05/07 - 20070157139 - Characterization and verification for integrated circuit designs Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics ... 07/05/07 - 20070157138 - Management of functions for block diagrams A method is provided that includes pattern-matching portions of a block diagram model as being equivalent, and creation of a common set of instructions in place of the occurrences of the pattern-matched portions to enhance the efficiency of simulation or generated code for the block diagram model, such as by ... 07/05/07 - 20070157137 - Method and apparatus for retrofitting semiconductor chip performance anaylsis tools with full-chip thermal analysis capabilities A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than ... 07/05/07 - 20070157136 - Selectively reducing the number of cell evaluations in a hardware simulation An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time. ... 07/05/07 - 20070157135 - Parallel multi-rate circuit simulation A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, and splitting the Jacobian matrix into two matrices M and N, where M is ... 07/05/07 - 20070157134 - Method for testing a hardware circuit block written in a hardware description language A method for testing a hardware circuit block written in a hardware description language (HDL) is provided, which can automatically produce a test pattern and an error message. The method includes converting an original class into a wrapper class, wherein the wrapper class, as compared to the original class, additionally ... 07/05/07 - 20070157133 - Circuit network analysis using algebraic multigrid approach This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to the grid coarsening and error smoothing operations to increase the processing speed. ... 06/28/07 - 20070150845 - Designing apparatus, designing method, and program thereof An apparatus and a program detect an error state of FSM coverage measurement, and shorten the checking time. The program for use in the FSM coverage measurement based on the language-described logical circuit and test bench is used to direct a computer to perform: a function of extracting an FSM ... 06/21/07 - 20070143719 - Synthesizing current source driver model for analysis of cell characteristics A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using ... 06/21/07 - 20070143718 - Feature failure correlation Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in ... 06/14/07 - 20070136700 - Method and apparatus for structured asic test point insertion Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC ... 06/14/07 - 20070136699 - Dependency matrices and methods of using the same for testing or analyzing an integrated circuit In a first aspect, a method of testing or analyzing an integrated circuit (IC) is provided. The method includes the steps of (1) generating information about a dependency between components of the IC based on a netlist describing the IC; and (2) reducing the generated information by at least one ... 05/31/07 - 20070124708 - Contrast based resolution enhancement for photolithographic processing A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold. ... 05/31/07 - 20070124707 - Method and apparatus for facilitating variation-aware parasitic extraction One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random ... 05/17/07 - 20070113209 - Chip design verifying and chip testing apparatus and method A chip design verifying and chip testing apparatus includes a storing means for storing an application program verifying an operation of a designed chip and testing a manufactured chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the ... 05/10/07 - 20070106967 - Layout analysis method and apparatus for semiconductor integrated circuit A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of ... 05/10/07 - 20070106966 - Method and apparatus for extracting characteristic of semiconductor integrated circuit A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter. ... 05/03/07 - 20070101302 - Mixed signal circuit simulator The waveform created by a circuit simulator is selected. The input data 11 inputted by an inputting means are obtained for a point on the waveform or the waveform. The selected waveform and the input data 11 are analyzed by a waveform analyzing means 12 to create circuit parameter updating ... 04/26/07 - 20070094623 - Timing, noise, and power analysis of integrated circuits DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation ... 04/26/07 - 20070094622 - Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the ... 04/19/07 - 20070089075 - Method for optimizing integrated circuit device design and service Improved analysis and refinement of integrated circuit device design and other programs is facilitated by methods in reach-ability analysis is performed using hints which define a particular path through a program. To ensure that a reasonable number of states are reached during reach-ability analysis a order to apply the hints ... 03/15/07 - 20070061763 - Method of generating development environment for developing system lsi and medium which stores program therefor A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions. ... 03/01/07 - 20070050737 - Functional cells for automated i/o timing characterization of an integrated circuit Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions ... 02/22/07 - 20070044050 - Method for searching for potential faults in a layout of an integrated circuit A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by ... 02/22/07 - 20070044049 - Apparatus and methods for predicting and/or calibrating memory yields An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated ... 02/22/07 - 20070044048 - System and method for circuit noise analysis Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract ... 02/15/07 - 20070038970 - System and method for testing pattern sensitive algorithms for semiconductor design A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each ... 02/15/07 - 20070038969 - Electronic ultimate defects analyzer detecting all defects in pcb/mcm A system for electric testing PCB/MCM before and after assembly. The system uses energy taken from a heating source, timely applied at certain ports of the PCB/MCM (entry ports). The energy is defused through the board inner layer tracks terminating at the end of the channel tracks of the PCB/MCM ... 02/08/07 - 20070033554 - Delay distribution calculation method, circuit evaluation method and false path extraction method Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects ... 02/08/07 - 20070033553 - Inductance analysis system and method and program therefor System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal ... 02/08/07 - 20070033552 - Method for detecting flaws in a functional verification plan This method uses 2 copies of the design under test. These 2 copies use different values (including primary inputs and initial states) to feed the supposedly irrelevant logic while using the same (or consistent as desired) values to feed the feature being verified. Symbolic method is used to efficiently determine ... 01/25/07 - 20070022393 - Recognition of a state machine in high-level integrated circuit description language code A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as VHDL and Verilog®, of an IC design and extracts description information corresponding to a state machine. The description information can be, ... 01/18/07 - 20070016879 - Method for identifying a physical failure location on an integrated circuit A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test ... 01/04/07 - 20070006104 - Electronic-circuit analysis program, method, and apparatus A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A determining unit compares a characteristic of an element model before change and that of the element model after change. An analysis-necessity deciding unit decides ... 12/28/06 - 20060294480 - Library creating device and interconnect capacitance estimation system using the same An interconnect capacitance estimation system includes a first storage device, a library creating device and an interconnect capacitance estimating device. The first storage device stores layout data. The library creating device creates a library used for estimating a capacitance of a net in a semiconductor circuit based on the layout ... 12/28/06 - 20060294479 - System for analyzing an electronic circuit described by characterization data A system for analyzing an electronic circuit described by characterization data forms an interpolation/approximation function over an analysis interval for analyzing the electronic circuit. An edge detection is applied to the characterization data to determine edges in the data, with the detected edges as subinterval limits used to form subinterval ... 12/21/06 - 20060288316 - Semiconductor device having predictable electrical properties A circuit element of a semiconductor device is provided. The circuit element has an electrical property and is formed by at least two like individual elements, each of said individual elements having an individual electrical property, the individual electrical property of each individual element including an error portion that is ... 12/14/06 - 20060282804 - Novel test structure for automatic dynamic negative-bias temperature instability testing The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement ... 12/14/06 - 20060282803 - Estimation of average-case activity for digital circuits A method for estimating the average-case activity in a digital circuit includes the steps of assigning initial activity values to outputs of flops in the digital circuit, and repeatedly updating the activity values in an iterative procedure until a predetermined termination criterion is met, wherein the updating of the activity ... 12/14/06 - 20060282802 - Method of extracting a semiconductor device compact model This invention is a method of extracting a semiconductor device compact model by using knowledge of the equations used inside the compact model. Starting by fitting a small subset of the model parameters, the remaining model parameters are fitted and as each new subset of model parameters are fitted, the ... 12/07/06 - 20060277506 - System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at ... 12/07/06 - 20060277505 - Method for automatically designing semiconductor device and automatic designing apparatus thereof In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire spacings is performed. Areas interposed among tower ... 11/30/06 - 20060271888 - Method and apparatus for simulating physical fields In order to design on-chip interconnect structures in a flexible way, a CAD approach is advocated in three dimensions, describing high frequency effects such as current redistribution due to the skin-effect or eddy currents and the occurrence of slow-wave modes. The electromagnetic environment is described by a scalar electric potential ... 11/16/06 - 20060259881 - Semiconductor circuit device and circuit simulation method for the same An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a ... 11/09/06 - 20060253812 - Source synchronous timing extraction, cyclization and sampling A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with ... 11/09/06 - 20060253811 - Moment computation algorithms in vlsi system An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. ... 11/09/06 - 20060253810 - Integrated circuit design to optimize manufacturability Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability ... 10/19/06 - 20060236275 - Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal Method for determining relevant circuit parts in a circuit in the event of loading with a temporally variable signal, the circuit having a number of circuit components which are connected up to one another and are in each case connected up by means of connections between at least two circuit ... 10/12/06 - 20060230369 - Interface configurable for use with target/initiator signals Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of ... 10/12/06 - 20060230368 - Detecting short circuits within an integrated circuit design In one embodiment, the present invention includes a method for obtaining a physical layout for an integrated circuit (IC) design of a substrate having at least one of an n-well and a deep n-well; and extracting a layout netlist for the IC design from the physical layout by identifying the ... 10/05/06 - 20060225010 - Semiconductor device and scan test method A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates ... 10/05/06 - 20060225009 - Computing current in a digital circuit based on an accurate current model for library cells In one embodiment, a method for computing current in a digital circuit based on an accurate current model for library cells includes accessing a cell library, for each cell in the cell library corresponding to a cell in a digital circuit, generating multiple waveforms of current drawn by the cell ... 09/28/06 - 20060218512 - System and method for rapid prototyping of asic systems A method for designing a computational device or circuit having one or more desired characteristics, preferably input and/or output characteristics. The method involves using an inner, iterative search that is preferably used within one or more genetic operators. As a first step, one of a population of computational circuits or ... 09/14/06 - 20060206839 - Method and system for evaluating design costs of an integrated circuit Method and system for evaluating design costs of an integrated circuit are disclosed. The method includes choosing a design point for evaluation, dividing circuit specifications of the design point into at least two groups comprising a first group of specifications and a second group of specifications, computing a first set ... 08/31/06 - 20060195804 - Method and apparatus for configurable circuitry A method and apparatus for configurable circuitry have been disclosed. ... 08/31/06 - 20060195803 - Method and apparatus for computing feature density of a chip layout One embodiment of the present invention provides a system that computes feature density for a number of areas within a layout by moving a window across the layout, which allows the system to identify areas in the layout that violate a design rule. During operation, the system receives a layout. ... 08/24/06 - 20060190863 - Method for improving accuracy of mosfet models used in circuit simulation integrated circuits Disclosed is a method of modeling submicron MOSFETs for the purpose of circuit simulation. This invention is capable of accurately predicting performance of a MOSFET with complex geometry closely approximating the actual geometry of a device manufactured as part of an integrated circuit. Actual device geometry is predicted using physical ... 08/24/06 - 20060190862 - Event driven switch level simulation method and simulator A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an operating frequency passes a functional requirement, identifying a weak signal node based on the simulation result, and performing a ... 08/24/06 - 20060190861 - Method and apparatus for evaluating coverage of circuit, and computer product An apparatus for evaluating coverage includes a determining unit that checks description rules when a receiving unit receives hardware description data. If the hardware description data matches a first or a second description rule, an optimizing unit performs a logic optimization by rewriting of the hardware description data according to ... 08/24/06 - 20060190860 - Method and system for debugging using replicated logic and trigger logic A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of ... 08/24/06 - 20060190859 - Negative bias temperature instability modeling A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in ... 08/24/06 - 20060190858 - System and method for accurately modeling an asynchronous interface using expanded logic elements A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration ... 08/24/06 - 20060190857 - Methods, systems and media for functional simulation of noise and distortion on an i/o bus Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the ... 08/24/06 - 20060190856 - Method and apparatus to generate circuit energy models with clock gating A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power ... 08/24/06 - 20060190855 - Identifying high e-field structures Power plane structures that may generate high E-fields can be identified and flagged for additional review by representing a boundary of the structures as a function, and evaluating the second derivative of that function. The result can be compared against a threshold value to determine if further review of the ... 08/24/06 - 20060190854 - Method for incorporating pattern dependent effects in circuit simulations Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of ... 08/24/06 - 20060190853 - Method for estimating a frequency-based ramptime limit A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal ... 08/17/06 - 20060184904 - Analyzing substrate noise In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation ... 07/06/06 - 20060150129 - Stochastic analysis process optimization for integrated circuit design and manufacture An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a ... 07/06/06 - 20060150128 - Method of fabricating and integrated circuit to improve soft error performance The present invention provides, in one aspect, a method of designing an integrated circuit 500. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit 500 by locating a structure 526, 528 relative to a node 516 of the integrated circuit 500 to reduce a ... 06/29/06 - 20060143583 - Methods and apparatus to maintain and utilize mobile power profile information A controller in PSE (Power Sourcing Equipment) controls how to provision uninterruptible power through corresponding data ports (and cables) of the PSE to network devices. For example, the controller receives power profile information associated with the network devices indicating how to provision power to the network devices during a power ... 06/29/06 - 20060143582 - Generating testcases based on numbers of testcases previously generated A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive elements and a goal for each of the elements. In various embodiments, the elements may represent commands or parameter values for a device to be tested. Testcases are generated based on the elements. If the numbers of testcases ... 06/22/06 - 20060136849 - Selectively reducing the number of cell evaluations in a hardware simulation An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time. ... 06/15/06 - 20060129957 - Method and computer program product for register transfer level power estimation in chip design A method for register transfer level power estimation in chip design includes the steps of: (A) parsing all possible condition branches of conditional statements in a register transfer level code, and establishing power modes inducible by each of the possible condition branches; (B) selecting a plurality of representative input vector ... 06/15/06 - 20060129956 - Method for generating hints for program analysis The present invention provides a method, apparatus and article of manufacture for generating hints for use when performing reach-ability analysis of a program such as programmatic representations of hardware circuits. The hints are generated from external inputs to the program which are used in conditional statements of the program. Further ... 06/15/06 - 20060129955 - Printed circuit board development cycle using probe location automation and bead probe technology Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probes insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in ... 06/15/06 - 20060129954 - Method, apparatus, and computer program product for rtl power sequencing simulation of voltage islands A method, apparatus and computer program product are provided for implementing RTL power sequencing simulation of voltage islands for application specific integrated circuit (ASIC) designs. RTL sequential state saving elements in a voltage island hierarchy are identified. A state is invalidated for each identified RTL sequential state saving element during ... 06/08/06 - 20060123365 - Power managers for an integrated circuit A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with ... 06/08/06 - 20060123364 - Method, system and program product for evaluating a circuit An improved solution for designing and/or evaluating a circuit is provided. A rule violation can be detected in design data for the circuit and a prediction can be generated based on an adjustment to the design data. For example, multiple predictions can be generated based on an adjustment window for ... 06/01/06 - 20060117280 - Digital circuit layout techniques using binary decision diagram for identification of input equivalence A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with ... 06/01/06 - 20060117279 - Method for storing multiple levels of design data in a common database An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The ... 05/25/06 - 20060112358 - System and method for designing a delayer emulation model A system for designing a delayer emulation model (1) includes a delayer emulation model generating apparatus (2). The delay emulation model generating apparatus includes: a delay circuit defining module (20) for defining delay parameters of a delay circuit, and generating the delay circuit; a delay signal setting module (21) for ... 05/25/06 - 20060112357 - Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysis A system and a method are disclosed for modeling an electronic element. Sensitivity of an output current to an input voltage without noise is determined. Output current is calculated in the event noise is present at an input using sensitivity. An output voltage is derived from the output current. The ... 05/18/06 - 20060107244 - Method for designing semiconductor intgrated circuit and system for designing the same A total random number sequence generator generates a total random number sequence of an entire circuit, as fabrication variation. A signal path random number sequence extracting section extracts, from the total random number sequence, a signal path random number sequence for a partial circuit obtained by dividing the entire circuit. ... 05/18/06 - 20060107243 - Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical ... 05/18/06 - 20060107242 - Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature ... 05/18/06 - 20060107241 - Evaluation device and circuit design method used for the same There is provided an evaluation apparatus capable of measuring the I-V characteristic in the MOSFET AC operation with a high accuracy. There are also provided a circuit design method and a circuit design system used for the evaluation apparatus. In the evaluation apparatus (1), an AC input signal superimposing circuit ... 05/11/06 - 20060101358 - Circuit design simulation Various approaches for simulating a circuit design are described. In one approach, charge-holding combinations of connected circuit components in a non-hierarchical representation of a circuit design are identified as known circuit components. Each identification is made as a function of characterized responses of the combinations. Identification information of the known ... 05/04/06 - 20060095876 - Method and apparatus for full-chip thermal analysis of semiconductor chip designs A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to ... 04/27/06 - 20060090147 - Inspection method and inspection apparatus for semiconductor integrated circuit In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit comprising plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconductor integrated circuit, the time during which a voltage applied upon each of the ... 04/27/06 - 20060090146 - In-line xor checking of master cells during integrated circuit design rule checking Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and ... 04/20/06 - 20060085773 - Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can ... 04/20/06 - 20060085772 - Model-based pattern characterization to generate rules for rule-model-based hybrid optical proximity correction A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by ... 04/20/06 - 20060085771 - Method of screening asic defects using independent component analysis of quiescent current measurements A method and computer program for screening defects in integrated circuit die includes steps of: (a) receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die; (b) generating a test matrix from the quiescent current measurements for each die in the sample lot; ... 04/20/06 - 20060085770 - A method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains Level shifter modules, used in integrated circuits (ICs), are automatically inserter and their correctness verified. A level shifter module for signals crossing voltage domains is generated, and instances thereof are inserted in a pre-determined voltage domain. Several checks ensure the correctness of the inserted level shifter module. The level shifter ... 04/13/06 - 20060080624 - Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout ... 04/13/06 - 20060080623 - Efficient large-scale full-wave simulation Significant improvement is achieved in the analysis of IC layout by utilizing the fact that IC designs exhibit a large amount of regularity. By employing a unique mesh generation approach that takes advantage of the regularity, combined with the use of a limited number of different shapes for the majority ... 04/06/06 - 20060075366 - Test structures for feature fidelity improvement Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more ... 03/23/06 - 20060064655 - Method and apparatus for locating circuit deviations A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of interconnected function blocks. The function blocks of the circuit ... 03/02/06 - 20060048081 - System and method for modeling an integrated circuit system The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated ... 03/02/06 - 20060048080 - Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip A method for computer aided design of semiconductor chips which minimizes sensitivity to latchup is provided. The method evaluates electron transmission, reflection and absorption at geometric shapes that represent components of the semiconductor. ... 02/23/06 - 20060041851 - Renesting interaction map into design for efficient long range calculations Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions ... 02/23/06 - 20060041850 - Test method for unit re-modification The present invention described a test method for unit re-modification, in which there is a test end and a host end. The method generated a sample pattern at a test end, generates a control pattern and modifies a re-modification unit. Otherwise, an experimental pattern is generated and then whether or ... 02/16/06 - 20060036981 - Validation of electrical performance of an electronic package prior to fabrication An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the ... 02/16/06 - 20060036980 - Method and apparatus for jitter analysis and program therefor A method, an apparatus and a program for comprehensively analyzing the power supply noise and consequent jitter for external output signals of the LSI in real time. From LSI layout designing data 601, the resistance, capacitance and inductance of the power supply interconnection are extracted to formulate a power supply ... 02/16/06 - 20060036979 - Computer-implemented methods for generating input for a simulation program or generating a simulated image of a reticle Various computer-implemented methods are provided. One computer-implemented method for generating input for a simulation program includes combining information about a defect detected on a partially fabricated reticle with information about phase assigned to an area of the reticle proximate to the defect. The phase is to be added to the ... 02/16/06 - 20060036978 - Board design aiding apparatus, board design aiding method and board design aiding program A board design aiding apparatus that simplifies a designed printed wiring board to predict a displacement quantity of the printed wiring board includes a layer thickness calculation section 21 for obtaining a mean thickness of an area of a board by a prescribed rule for an essential material forming a ... 02/16/06 - 20060036977 - Physical design system and method A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target ... 02/16/06 - 20060036976 - Method for designing an integrated circuit defect monitor A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and ... 02/16/06 - 20060036975 - Defect diagnosis for semiconductor integrated circuits A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, ... 02/09/06 - 20060031794 - Method and apparatus for thermal modeling and analysis of semiconductor chip designs A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures ... 02/09/06 - 20060031793 - Spice simulation system for diode and method of simulation using the same A system and method for simulating a diode device measures electrical characteristics of a plurality of diodes; normalizes the measured electrical characteristics of the diode; extracts a plurality of device parameters of each of the diodes from the normalized characteristics; converts the device parameters of each of the diodes to ... 02/09/06 - 20060031792 - Method and apparatus for locating short circuit faults in an integrated circuit layout The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming ... 02/02/06 - 20060026542 - Systems and methods for generating node level bypass capacitor models Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a ... 02/02/06 - 20060026541 - Method and apparatus for expediting convergence in model-based opc One embodiment of the invention provides a system that expedites or stabilizes convergence in a model-based optical proximity correction (OPC) process. During operation, the system receives a layout for an integrated circuit. Next, the system dissects shapes in the layout into a number of segments, and then runs a number ... 02/02/06 - 20060026540 - Electro-migration (em) and voltage (ir) drop analysis of integrated circuit (ic) designs Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of ... 01/19/06 - 20060015832 - Method of moment computations in r(l)c interconnects of high speed vlsi with resistor loops A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can ... 01/19/06 - 20060015831 - Minimizing computational complexity in cell-level noise characterization Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an arc (combination of input pin and output pin) of a cell is determined, and NP characteristics and NIC are generated only for the worst case ... 12/29/05 - 20050289490 - Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated ... 12/29/05 - 20050289489 - On-board performance monitor and power control system A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module ... 12/29/05 - 20050289488 - System and method for mask defect detection A mask defect detection system. The mask defect detection system comprises a first processing device, a second processing device, a third processing device, and a storage device. The first processing device processes mask design information to generate first writer-formatted mask information, wherein the first processing device comprises a first processing ... 12/29/05 - 20050289487 - Method and system for dynamic modeling and recipe optimization of semiconductor etch processes A method and system are disclosed for creating dynamic models of etch processes in semiconductor manufacturing. In one embodiment, a method comprises modeling an etch process used in semiconductor manufacturing to generate a dynamic process model. The dynamic process model is used to determine input values that result in a ... 12/22/05 - 20050283747 - Opc simulation model using socs decomposition of edge fragments A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the window area. Results of the decomposition are used to access lookup tables that store data related to the contribution ... 12/22/05 - 20050283746 - System and method for calculating trace lengths of a pcb layout A system for calculating trace lengths of a PCB layout includes a computer (10) and a database (11). The computer includes: an object setting module (100) for setting objects to define section rules; a section rule defining module (101) for selecting objects as a start point and an end point ... 12/22/05 - 20050283745 - Design checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first ... 12/15/05 - 20050278667 - Integrated circuit diagnosing method, system, and program product The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical ... 12/15/05 - 20050278666 - System and method for testing and configuring semiconductor functional circuits The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors including manufacturing defects, compatibility characteristics, performance requirements, and system health ... 12/15/05 - 20050278665 - Methods to gather and display pin congestion statistics using graphical user interface The present invention is a method for collecting, analyzing, and displaying statistics regarding block pin placement prior to routing of an integrated circuit. The statistics are graphically displayed in a graphical user interface (GUI). The GUI graphically displays indications of where block pin congestion problems lie, which allows an integrated ... 12/15/05 - 20050278664 - Predicting power consumption for a chip A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time ... 12/15/05 - 20050278663 - Method and system for improving integrated circuit manufacturing productivity A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated ... 12/15/05 - 20050278662 - Method for preventing circuit failures due to gate oxide leakage A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as ... 12/08/05 - 20050273739 - Pattern analysis method, pattern analysis apparatus, yield calculation method and yield calculation apparatus A critical area of one via is calculated on the basis of sizes of a plurality of vias, sizes of defects causing random defect failures of the plural vias and a distance from the one via to another adjacent via. ... 12/08/05 - 20050273738 - Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit A clock integration method, tool, and a computer program product that captures, creates, and seamlessly integrates a clock specification to achieve a correct-by-construction design flow of a semiconductor product, such as an ASIC, from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed ... 12/08/05 - 20050273737 - Language and templates for use in the design of semiconductor products During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character ... 12/08/05 - 20050273736 - Rules and directives for validating correct data used in the design of semiconductor products A method, rules and directives engine, and a computer program product that simplifies the design of semiconductor products. Starting with an application set which is a partially manufactured semiconductor platform that is correct-by-construction, as a chip designer inserts her/his own designs into the platform, a system of rules and directives ... 12/08/05 - 20050273735 - Tuple propagator and its use in analysis of mixed clock domain designs Names of signals are propagated through a circuit design inside tuples, with each tuple including at least a signal name and a sequential depth. A tuple being propagated is added to a list of zero or more tuples currently identified with a circuit element, unless a tuple of the same ... 12/08/05 - 20050273734 - Correcting design data for manufacture A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in a predetermined order, and providing corrected design data. ... 12/08/05 - 20050273733 - Opc conflict identification and edge priority system An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edges segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments ... 12/01/05 - 20050268258 - Rule-based design consultant and method for integrated circuit design A rule-based design consultant and analysis method for an integrated circuit (“IC”) layout design compares an IC design against a list of rules. The IC design information may be included in a set of databases, including a database containing physical implementation and technology specific timing and area information. The consultant ... 12/01/05 - 20050268257 - Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104 ... 12/01/05 - 20050268256 - Modeling resolution enhancement processes in integrated circuit fabrication A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process ... 11/24/05 - 20050262458 - Capacitance modeling Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves ... 11/24/05 - 20050262457 - Checking the robustness of a model of a physical system The invention provides a system and a method for verifying the robustness of a model of a physical system, the method comprising the following steps: defining a first model of the physical system comprising a set of components and at least one input interface for inserting input values, said first ... 11/24/05 - 20050262456 - Verifying one or more properties of a design using sat-based bmc In one embodiment, a method for satisfiability (SAT)-based bounded model checking (BMC) includes isolating information learned from a first iteration of an SAT-based BMC process and applying the isolated information from the first iteration of the SAT-based BMC process to a second iteration of the SAT-based BMC process subsequent to ... 11/24/05 - 20050262455 - System and method for verifying a layout of circuit traces on a motherboard A system for verifying a layout of circuit traces on a motherboard includes a computer (1) and a database (2). The database is used for storing data generated and used by the system. The computer includes: a substandard layout area creating module (101) for creating substandard layout areas; a substandard ... 11/24/05 - 20050262454 - Method for vlsi system debug and timing analysis A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes ... 11/17/05 - 20050257182 - System and method for verifying trace distances of a pcb layout A system for verifying trace distances of a PCB layout includes a computer (10) and a database (11). The computer includes: a segment receiving module (100) for receiving segments of a selected trace, and depositing the segments in a segment set; a segment selecting module (101) for selecting an unverified ... 11/17/05 - 20050257181 - Method and apparatus for identifying line-end features for lithography verification One embodiment of the invention provides a system that facilitates identifying line-end features in a layout for an integrated circuit. The system operates by first receiving the layout for the integrated circuit. Next, the system selects a polygon from the layout and marks a line-end seed on the polygon. The ... 11/10/05 - 20050251768 - Function verification method A function verification method comprises preparing a first function block that can execute the required functions in a semiconductor integrated circuit, preparing a second function block to be a verification target having a substantially identical configuration as the first function block and verifying functions of the second function block using ... 11/10/05 - 20050251767 - Processing of circuit design data One example embodiment of an approach to circuit design analysis comprises partitioning a circuit design into first, second and boundary parts, the boundary part including circuit portions from each of the first part and second part at a boundary between the first part and second part. The first, second and ... 11/10/05 - 20050251766 - Circuit design interface According to an example embodiment of an approach to circuit design processing involves using an interface for retrieving and processing circuit design data for use by a plurality of simulation tools. The interface includes an application program callable function configured to return functional classification data in response to an application ... 11/10/05 - 20050251765 - Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource ... 10/27/05 - 20050240887 - Generating test patterns having enhanced coverage of untargeted defects Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e.g., stuck-at faults or bridging faults) in an integrated circuit design are ... 10/27/05 - 20050240886 - Method of performing design rule checking A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number ... 10/20/05 - 20050235234 - Method and computer program for verifying an incremental change to an integrated circuit design A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database ... 10/13/05 - 20050229123 - Computer-aided design system to automate scan synthesis at register-transfer level A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, ... 10/13/05 - 20050229122 - Logic verification device, logic verification method and logic verification computer program A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic ... 10/13/05 - 20050229121 - Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure A method and apparatus for verifying an integrated circuit device test for testing an integrated circuit device on an automated tester is presented. An integrated circuit device simulator simulates a flawed integrated circuit device that models one or more known flaws, or physical defects, in an assumed good integrated circuit ... 10/06/05 - 20050223346 - Random code generation using genetic algorithms Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which ... 10/06/05 - 20050223345 - Circuit design assistant system, circuit design method, and program product for circuit design The computer program product according to an embodiment of the invention causes a computer to execute the process including acquiring circuit information generated by behavioral synthesis, determining an active condition of a net, determining an active condition of an alternate path, determining an active condition of an alternate data path, ... 09/29/05 - 20050216871 - Scheduling events in a boolean satisfiability (sat) solver In one embodiment, a method for scheduling events in a Boolean satisfiability (SAT) solver includes collecting one or more first-order statistics on a search for a valid solution to an SAT problem, deriving one or more second-order statistics on the search from the one or more first-order statistics, and scheduling ... 09/29/05 - 20050216870 - Ic design density checking method, system and program product A system, method and program product for performing density checking of an IC design. The invention establishes an evaluation array for the IC design including an array element for each evaluation window of the IC design. The number of evaluation windows is based on a smallest necessary granularity. A single ... 09/22/05 - 20050210430 - System and method to optimize logical configuration relationships in vlsi circuit analysis tools A method for optimizing relationships between logic commands defining a circuit design is described. The method comprises, for each logic command determining whether the logic command is a primitive logic command; and, responsive to the logic command not being a primitive logic command, decomposing the logic command into its most ... 09/22/05 - 20050210429 - System and method to limit runtime of vlsi circuit analysis tools for complex electronic circuits A method of using a software tool to analyze a VLSI circuit is described. In one embodiment, the method comprises, prior to initiating analysis of the circuit, performing a complexity check on the circuit; responsive to the circuit failing the complexity check, aborting analysis of the circuit; and responsive to ... 09/22/05 - 20050210428 - System and method for flattening hierarchical designs in vlsi circuit analysis tools One embodiment is a method for enabling a first circuit analysis tool to flatten a hierarchical design for processing by a second circuit analysis tool. The method comprises reading a logical representation of the hierarchical design; and, for each block of the hierarchical design, loading RC information for the block ... 09/22/05 - 20050210427 - System and method for facilitating efficient application of logical configuration information in vlsi circuit analysis |