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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Translation (e.g., Conversion, Equivalence) Translation (e.g., Conversion, Equivalence)Translation (e.g., Conversion, Equivalence) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266347 - Method of automatic synthesis of sequential quantum boolean circuits A method of automatic synthesis of sequential quantum Boolean circuits for transferring a self-timed circuit into a sequential quantum Boolean circuit and synthesizing the sequential quantum Boolean circuit, which comprises the steps of: (A) transferring the self-timed circuit into a state graph having M state nodes, where M is an ... 07/05/07 - 20070157132 - Process of automatically translating a high level programming language into a hardware description language A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level ... 06/28/07 - 20070150844 - Behavioral synthesizer system, operation synthesizing method and program The present invention is intended to realize a behavioral synthesis system which can synthesize behavioral without inline-expanding a callee function even if a pointer is passed to the callee function during a behavioral synthesis of a caller function. The behavioral synthesis system comprises language analyzing means for analyzing the behavioral-level ... 06/28/07 - 20070150843 - Method for generating minimal leakage current input vector using heuristics A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS and NMOS parts and P and N devices of the integrated circuit into edges, selecting between PMOS and NMOS logic ... 06/21/07 - 20070143717 - Formally proving the functional equivalence of pipelined designs containing memories One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, ... 04/26/07 - 20070094621 - Method and system for converting netlist of integrated circuit between libraries The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. ... 02/08/07 - 20070033551 - Method for simulating hardware Integrated circuit design often involves combination of blocks of circuit from different sources to create new designs. However, a simulation of a block developed using a given method may not be compatible with another simulation created using another method. A method for modifying hardware simulation having one internal timing regime ... 02/08/07 - 20070033550 - Automated migration of analog and mixed-signal vlsi design A method for migrating an electronic circuit from a source technology to a target technology includes accepting a source circuit that operates in the source technology. The source circuit includes source components interconnected at nodes in accordance with a source topology. Source voltages at the nodes of the source circuit ... 02/01/07 - 20070028198 - Method and apparatus for allocating data paths to minimize unnecessary power consumption in functional units A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises power management formulations can be used to gear the allocation process to generate hardware architecture of minimal spurious switching. Bipartite weighted Assignment is used to determine the sharing of functional units, through cost formulations and the Hungarian ... 02/01/07 - 20070028197 - Method and apparatus for auto-generation of shift register file for high-level synthesis compiler A method and apparatus for auto-generation of shift register file for high-level synthesis compiler includes parsing input source codes for specific definition of shift register file, a plurality of compiler directives to indicate the shift register file name, shift register file size, shift register file read access order, and shift ... 02/01/07 - 20070028196 - Resource estimation for design planning A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step ... 01/11/07 - 20070011629 - Adaptive application of sat solving techniques A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance ... 12/21/06 - 20060288315 - Method and apparatus for compiling a parameterized cell A method of generating a parameterized cell is disclosed herein. The method comprises performing a compiling interpretation (56) on a structure layout. The compiling interpretation (56) includes i) determining and analyzing shape relationships of the structure layout (72), and ii) mapping shapes and calculating properties of mapped shapes (74). The ... 11/02/06 - 20060248484 - Method for preserving constraints during sequential reparameterization A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut ... 10/19/06 - 20060236274 - Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial ... 10/12/06 - 20060230367 - Method and system for reduction of and/or subexpressions in structural design representations A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from ... 10/12/06 - 20060230366 - Method and system for reduction of xor/xnor subexpressions in structural design representations A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set ... 10/05/06 - 20060225008 - Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, ... 08/24/06 - 20060190852 - Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives ... 08/24/06 - 20060190851 - Asynchronous circuit design tool and computer program product It is the object of the present invention to provide asynchronous circuit design tools for those engineers who are versed in standard hardware description languages (HDLs), which is widely used in industry mainly for synchronous circuit design, to design asynchronous circuits with relative ease. To accomplish the object, the asynchronous ... 08/17/06 - 20060184903 - Logical equivalence verifying device, logical equivalence verifying method, and logical equivalence verifying program The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs ... 07/13/06 - 20060156260 - Behavioral transformations for hardware synthesis and code optimization based on taylor expansion diagrams A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated with any suitable architectural synthesis system. It can also be built into a compiler tool for general purpose processor or into a specific ... 06/15/06 - 20060129953 - Method for verifying and representing hardware by decomposition and partitioning A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables ... 06/01/06 - 20060117277 - Circuit design support methods and systems A method for circuit design support. A netlist file is received. A first 4-terminal device is acquired from the netlist. A second 4-terminal device with the same specifications as the first 4-terminal device is acquired. A first determination is performed to determine whether all control terminals of the first device ... 05/25/06 - 20060112356 - System and method for converting a flat netlist into a hierarchical netlist System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing ... 05/11/06 - 20060101357 - Technology migration for integrated circuits with radical design restrictions A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to ... 05/11/06 - 20060101356 - Technology migration for integrated circuits with radical design restrictions A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of ... 03/02/06 - 20060048079 - Special tie-high/low cells for single metal layer route changes A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a first power rail and ... 02/16/06 - 20060036974 - Ip-based lsi design system and design method An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating ... 02/09/06 - 20060031791 - Compiling memory dereferencing instructions from software to hardware in an electronic design Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory ... 12/29/05 - 20050289486 - Equivalence checking of scan path flush operations A method, apparatus, system, and signal-bearing medium that in an embodiment apply a latch behavior to a first and second netlist, where the latch behavior exhibits transparent behavior. Flush enabling conditions are applied to the first netlist and a second netlist. For each latch in a first scan chain in ... 12/22/05 - 20050283744 - Integrated circuit designing system, method and program When a simulation model generation unit converts logic on the gate level into a basic primitive which can be executed by a simulator to generate a simulation model, for the basic primitives a degeneracy processing unit determines and deletes a gate which can be deleted and which will not affect ... 12/15/05 - 20050278661 - Multi-valued digital information retaining elements and memory devices The invention discloses models and methods to create stable binary and non-binary sequential devices comprised of one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input information retaining devices from two logic functions are disclosed. ... 11/17/05 - 20050257180 - Method of optimizing rtl code for multiplex structures A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register ... 11/17/05 - 20050257179 - Method, system and program product for building an automated datapath system generating tool A method, system and program product for building an automated bit-sliced datapath system generating tool so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type ... 11/10/05 - 20050251764 - Method of generating protected standard delay format file A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal ... 11/10/05 - 20050251763 - Methods and apparatus for scan insertion The traditional method of scan insertion and balancing clocks involves first having a system clock, which can be used for scan mode and normal mode, then synthesizing the design, defining scan chain or scan chains, and inserting them in the design using a script. After that, the cells are placed ... 11/03/05 - 20050246668 - Method and device for an equivalence comparison of digital circuits Assignment information items for assigning signal-path identifiers of circuit descriptions in accordance with a second description format also as a function of the circuit description in accordance with a first description format, from which circuit description the circuit descriptions in accordance with the second description format have been produced by ... 10/27/05 - 20050240885 - Efficient sat-based unbounded symbolic model checking An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in SAT-based unbounded symbolic model checking. ... 09/29/05 - 20050216869 - Compiler A compiler apparatus enabling description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file 24, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser ... 09/22/05 - 20050210422 - Method and apparatus for performing logical transformations for global routing The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves ... 09/08/05 - 20050198596 - Dynamically configuring resources for cycle translation in a computer system A method and system that enables customized computer machines to be more readily developed by removing the function of resource translation out of the hardware abstraction layer (HAL). A machine manufacturer describes a machine in firmware, such as accordance with the Advanced Configuration and Power Interface (ACPI) specification, using ACPI ... 08/04/05 - 20050172245 - System and method for providing interface compatibility between two hierarchical collections of ic design objects A system and method for providing interface compatibility between two hierarchical collections of integrated circuit (IC) design objects. Upon establishing an associative correspondence between a design object from a first hierarchical collection and a design object from a second hierarchical collection, a port compatibility map is generated based on determination ... 07/28/05 - 20050166165 - Verilog to c++ language translator Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a Verilog file and substituting the Verilog pattern with a C++ language expression, wherein the C++ language expression is associated with the same functionality as ... 07/21/05 - 20050160385 - Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for asic designs A method, apparatus and computer program product are provided for implementing application specific integrated circuit (ASIC) designs having high performance and reduced leakage current. Standard voltage threshold (SVT) circuits in a SVT circuit library are identified. For each SVT circuit, each SVT PFET is replaced with a low voltage threshold ... 07/21/05 - 20050160384 - Recognition of a state machine in high-level integrated circuit description language code A method and apparatus for recognizing a state machine in circuit design in a high-level IC description language. The present invention analyzes high-level IC description language code, such as VHDL and Verilog®, of an IC design and extracts description information corresponding to a state machine. The description information can be, ... 07/14/05 - 20050155002 - Combinational equivalence checking methods and systems with internal don't cares An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate ... 07/07/05 - 20050149891 - Memory compiler with ultra low power feature and method of use The present invention relates to a method of creating a design for a semiconductor memory. In an embodiment, a memory compiler for a semiconductor memory has access to a set of leaf cell designs for use by the memory compiler, the leaf cell designs comprising a power management circuit design ... 07/07/05 - 20050149890 - Programming reconfigurable packetized networks A configurable circuit including a heterogeneous mix of processing elements is programmed. ... 07/07/05 - 20050149889 - Reorganizing rectangular layout structures for improved extraction Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a second rectangle that intersects the first rectangle, and if the second rectangle is ... 06/30/05 - 20050144575 - Circuit arrangement design method and circuit arrangement design program A circuit arrangement design method includes a step of performing a logic conversion of logic, the logic forming a circuit arrangement where a cell arrangement and a connection arrangement between cells are provisionally arranged prior to a detailed mounting design, and thereby wiring efficiency is improved. ... 06/23/05 - 20050138580 - Method of generating dependency specification file capable of reconfiguring function block of soft ip and recording medium storing codes embodying the method Provided is a method of generating a dependency specification file of a soft IP comprising, extracting constituent element information by parsing a netlist file of a soft IP and designating an instance name and a component name to input and output ports and function blocks which are constituent elements existing ... 06/09/05 - 20050125749 - Method of selectively building redundant logic structures to improve fault tolerance A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the ... ### FreshPatents.com Support |