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Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask > Circuit Design > Optimization (e.g., Redundancy, Compaction) Optimization (e.g., Redundancy, Compaction)Optimization (e.g., Redundancy, Compaction) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070256037 - Net-list organization tools The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern; ... 10/25/07 - 20070250797 - Method and system of modeling leakage A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the ... 10/25/07 - 20070250796 - Method and computer program product for designing power distribution system in a circuit A method for designing a power distribution system including: receiving a cross section file that contains the layout of a PCB including a location of one or more power sinks and sources on the PCB; creating an initial power distribution system; evaluating the initial power distribution system against a cost ... 10/18/07 - 20070245273 - Task concurrency management design method A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality ... 10/18/07 - 20070245272 - Concurrent optimization of physical design and operational cycle assignment Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In ... 10/11/07 - 20070240084 - System and method to improve chip yield, reliability and performance Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. ... 10/04/07 - 20070234243 - Design data creating method, design data creating program product, and manufacturing method of semiconductor device According to an aspect of the invention, there is provided a design data creating method of creating design data of a semiconductor device including extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a ... 08/30/07 - 20070204242 - Gate modeling for semiconductor fabrication process effects In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation ... 08/23/07 - 20070198956 - Method and system for improving yield of an integrated circuit Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising ... 08/16/07 - 20070192751 - Method and apparatus to reduce random yield loss One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine ... 08/02/07 - 20070180410 - System and method for reducing the power consumption of clock systems A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed ... 07/05/07 - 20070157130 - Method for multi-cycle clock gating An apparatus includes a multi-cycle clock gater and a circuit design updater. The multi-cycle clock gater generates multi-cycle gating groups of data latching devices of a circuit design. The circuit design updater updates the circuit design with selected multi-cycle gating groups. Each gating group is associated with a single gating ... 06/21/07 - 20070143716 - Circuit layout compaction using reshaping A critical path minimization technique uses a novel reshaping layout reorganization mechanism. Circuit objects and/or object fragments which belong to a critical path in a reference direction are reshaped using resources of an orthogonal direction. A fragment may decrease its size in the layout in the reference direction and increase ... 06/07/07 - 20070130549 - Clock-gating through data independent logic Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent ... 05/10/07 - 20070106965 - Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, ... 05/10/07 - 20070106964 - Optimized microchip and related methods Various embodiments of an optimized microchip and methods of fabricating and operating the same are provided. One microchip embodiment, among others, comprises a repeater-type transistor located in a first path corresponding to a first path type, the repeater-type transistor having a parameter at a first design value, and a logic-type ... 05/10/07 - 20070106963 - Method and system for predicate-based compositional minimization in a verification environment A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or more next-state functions ... 04/19/07 - 20070089074 - Method and apparatus for automated circuit design Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In one aspect of the present invention, a method to design a circuit ... 04/19/07 - 20070089073 - Shape-based geometry engine to perform smoothing and other layout beautification operations A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously ... 04/19/07 - 20070089072 - Signal transmission structure A signal transmission structure includes an aggressor line and a victim line parallel with the aggressor line, and a number of delay portions formed in the victim line. Noise due to crosstalk passing through the delay portion is delayed an amount of time equal to or greater than a rise ... 04/12/07 - 20070083832 - Method for performing post-synthesis circuit optimization Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by ... 04/05/07 - 20070079263 - Design method of semiconductor integrated circuit device, a program, and the support method of measurement evaluation Sample evaluation is effectively conducted within a short period of time using a general purpose software by changing programs, data files and register libraries in accordance with measuring specifications of semiconductor integrated circuit devices. The automatic measuring program used for sample evaluation includes a basic standard frame and can realize ... 04/05/07 - 20070079262 - Clock tree layout method for semiconductor integrated circuit By executing the steps of sequentially retrieving buffers on a clock tree from a clock source to input pins of the cells other than the buffers and recognizing the buffer retrieved, organizing a group of the buffers recognized on the clock tree into an instance as a hierarchical block and ... 03/01/07 - 20070050736 - Method of facilitating integrated circuit design An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (110). The method utilizes one or more library element (150A-F) to provide a flexible modeling template. Each library element includes one or more module ports (160A-F) each for accepting any ... 02/22/07 - 20070044047 - Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven ... 02/22/07 - 20070044046 - Method for providing a current sink model for an asic A current sink model is provided by determining the charge consumed by each type of a predetermined group of standard cell types under each of a plurality of conditions, determining the quantity of such standard cells of each type in the region of interest on the chip, and then using ... 02/22/07 - 20070044045 - Method and apparatus for optimizing a logic network in a digital circuit One embodiment of the present invention provides a system that optimizes a logic network. During operation, the system receives a first logic network which defines a logical function, wherein the first logic network cannot be efficiently optimized by directly using an optimization process that preserves the logical function. Next, the ... 02/15/07 - 20070038968 - Increased power line noise immunity in ic using capacitor structure in fill area Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a ... 02/08/07 - 20070033549 - Interconnect model-order reduction method An interconnect model-order reduction method for reduction of a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms disclosed. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select order of the reduced-order ... 02/01/07 - 20070028195 - Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction ... 01/11/07 - 20070011628 - Method and apparatus for removing dummy features from a data structure A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and ... 12/28/06 - 20060294478 - Method and system for reducing delay noise in an integrated circuit A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is computed for each net. The effective capacitance ... 12/14/06 - 20060282801 - Enhanced method of optimizing multiplex structures and multiplex control structures in rtl code A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and ... 12/14/06 - 20060282800 - Bus representation for efficient physical synthesis of integrated circuit designs A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the compactness of a bus level representation as well as the uniqueness of a bit level representation. Connectivity abstraction significantly reduces network complexity, i.e., the ... 12/14/06 - 20060282799 - Method of determining high-speed vlsi reduced-order interconnect by non-symmetric lanczos algorithm Two-sided projection-based model reductions has become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered ... 11/23/06 - 20060265674 - System and method for statistical design rule checking Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working ... 11/16/06 - 20060259880 - Optimization of circuit designs using a continuous spectrum of library cells The present invention comprises a method of optimizing a circuit design having a plurality of library cells. In one embodiment, the method includes the steps of providing a plurality of logically equivalent cells that vary in at least one design parameter, the plurality of logically equivalent cells having a relatively ... 11/16/06 - 20060259879 - Modeling a mixed-language mixed-signal design A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For ... 11/02/06 - 20060248483 - Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate ... 11/02/06 - 20060248482 - Method for heuristic preservation of critical inputs during sequential reparameterization A method, system, and computer program product for preserving critical inputs is disclosed. The method comprises receiving an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements. A ... 11/02/06 - 20060248481 - Method and system for reversing the effects of sequential reparameterization on traces A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step ... 10/12/06 - 20060230365 - Method for designing a circuit, particularly having an active component A method for designing a circuit, particularly having an active component, preferably a high-frequency circuit, wherein: (a) a plurality of load lines is determined at least approximately; (b) a course of a small-signal parameter along each load line is determined at least approximately; (c) a region of each load line ... 10/05/06 - 20060225007 - Antenna effect prevention by model extraction in a circuit design for advanced processes A method is disclosed for determining an antenna ratio for an interconnect in a circuit. The interconnect may be routed through one or more connection layers and may be electrically coupled to one or more gate oxide areas. A cumulative antenna ratio for all components on each connection layer is ... 10/05/06 - 20060225006 - Method and apparatus of optimizing the io collar of a peripheral image An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO ... 10/05/06 - 20060225005 - Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Methods, systems and program products are disclosed that prioritize each target via for via redundancy based on at least one of the following: subnet timing information, a distance of a target via along a path from a driving source and a target via net/subnet characteristic, and attempt to add a ... 08/24/06 - 20060190850 - Method for optimizing the geometry of structural elements of a circuit design pattern and method for producing a photomask A method for optimizing the geometry of structural elements of a circuit pattern involves providing an overall circuit pattern of the circuit design and a plurality of basic patterns. Subsequently, the circuit pattern of the circuit design is iteratively decomposed into corresponding basic patterns in order to classify those parts ... 08/24/06 - 20060190849 - Micro computer and method of optimizing microcomputer A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency ... 08/24/06 - 20060190848 - Low power consumption designing method of semiconductor integrated circuit In a standard cell synthesizing step 101, a net list is synthesized from an RTL description, and an instance name list is formed which contrasts a register description portion with an instance name contained in the net list; in a simulation step 103, an operation simulation written by the RTL ... 08/24/06 - 20060190847 - Ic compaction system An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding ... 07/06/06 - 20060150127 - Method of achieving timing closure in digital integrated circuits by optimizing individual macros Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than ... 06/29/06 - 20060143581 - Method and device for electronic circuit designing, and computer product Noise related to a part of electronic circuits that are to be designed is computed. If the computed noise exceeds a limiting value, parameters of the electronic circuits are modified by using a predetermined method (simple noise check) so that the noise is less than or equal to the limiting ... 06/15/06 - 20060129952 - Method for incremental design reduction via iterative overapproximation and re-encoding strategies A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design ... 06/01/06 - 20060117276 - Semiconductor integrated circuit designing method and program An object of the present invention is to prevent occurrence of an unconnected terminal during arrangement and connection, shorten the time required for automatic arrangement and connection, improve a yield, and improve the properties of a cell. A recognized object-of-wiring thinning cell (minimum-rule cell) is temporarily replaced with a preferred-rule ... 05/18/06 - 20060107240 - Logic injection A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data ... 05/11/06 - 20060101355 - Yield improvement An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is ... 05/04/06 - 20060095875 - Design method of semiconductor integrated circuit General-purpose software is used to efficiently perform sample evaluation in a short period of time by changing a register library in accordance with register configuration of a semiconductor integrated circuit device. A register setup program is used for sample evaluation and is composed of a register setup main program and ... 05/04/06 - 20060095874 - Power network synthesizer for an integrated circuit design A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select ... 05/04/06 - 20060095873 - Apparatus and method for detecting body diode conduction in a semiconductor device An apparatus is for detecting body diode conduction in a semiconductor device that includes first regions fixed with a substrate having an upper surface to establish a source, gate and drain with drain-to-source current flow parallel with the surface. The first regions experience body diode conduction in a first inter-region ... 04/27/06 - 20060090145 - Method of optimizing critical path delay in an integrated circuit design A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for ... 04/27/06 - 20060090144 - Method of automating place and route corrections for an integrated circuit design from physical design validation A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the ... 04/20/06 - 20060085769 - Improving systematic yield in semiconductor manufacture Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are ... 04/20/06 - 20060085768 - Integrated circuit selective scaling Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the ... 04/06/06 - 20060075365 - Novel optimization for circuit design Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. ... 04/06/06 - 20060075364 - Method and apparatus for driving on-chip wires through capacitive coupling One embodiment of the present invention provides a system which drives on-chip wires using capacitive coupling. During operation, the system drives a signal onto a driven wire. This signal feeds from the driven wire through a coupling capacitor onto a coupled wire, which is an on-chip wire that routes the ... 03/23/06 - 20060064654 - Routed layout optimization with geotopological layout encoding for integrated circuit designs The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some ... 03/23/06 - 20060064653 - Automatic layout yield improvement tool for replacing vias with redundant vias through novel geotopological layout in post-layout optimization The present invention provides a new way of improving yield in the physical design stage after detail routing, thereby optimizing integrated circuit (IC) layout designs for manufacturing. Embodied in an automatic layout yield improvement tool, the present invention replaces vias with redundant vias having redundant cut shapes or larger metal ... 03/16/06 - 20060059443 - Hierarchical feature extraction for electrical interaction A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the ... 03/09/06 - 20060053393 - Method of improving routes of nets in circuits One disclosed method for improving the route of at least one net of a circuit comprises: receiving a circuit design that includes a plurality of circuit elements and at least one communication carrier element; determining a location for each circuit element; determining an original route for the communication carrier element; ... 02/23/06 - 20060041849 - Method and apparatus for reducing redundant data in a layout data structure The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the ... 02/02/06 - 20060026539 - Method of automated repair of crosstalk violations and timing violations in an integrated circuit design A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according ... 01/19/06 - 20060015830 - Systems, methods, and articles of manufacture for flexible path optimization A flexible transportation optimization approach is described that can easily be implemented on multi-tiered computer systems and that does not unnecessarily consume processing and memory resources. On a database tier a data model is defined. The data model comprises master data including a state set with a plurality of states ... 01/19/06 - 20060015829 - Method and apparatus for designing electronic circuits using optimization Methods and apparatus for designing electronic circuits, including analog and mixed signal (AMS) circuits, based on an evolutionary optimization approach. In one exemplary embodiment, the optimization approach is implemented using a computer program running on one or more computers. The optimization program receives inputs from the designer regarding (i) optimization ... 01/05/06 - 20060005152 - Method and device for designing semiconductor integrated circuit and logic design program A method for designing a semiconductor integrated circuit includes performing logic design and physical design. The method estimates whether logic design data generated in the logic design is appropriate for use in the physical design before the physical design is started. The result of the estimation is fed back to ... 12/15/05 - 20050278660 - Automatic circuit design method with a cell library providing transistor size information A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several ... 12/08/05 - 20050273732 - Optimization and design method for configurable analog circuits and devices Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application. ... 11/17/05 - 20050257178 - Method and apparatus for designing electronic circuits Methods and apparatus for designing electronic circuits, including analog and mixed signal circuits. In one exemplary embodiment, a hierarchical design and sizing flow is used, in conjunction with one or more evaluation models (e.g., performance and feasibility models), such that results generated at one level remain valid and pertinent other ... 10/27/05 - 20050240884 - Via spacing violation correction method, system and program product A method, system and program product for correcting via spacing violations by generating a redundant via to replace one of a pair of vias that violate a ground rule, are disclosed. The redundant via corrects the ground rule violation. The target via corresponding to the redundant via is then removed, ... 09/15/05 - 20050204317 - Integrated circuit design system, integrated circuit design program, and integrated circuit design method An integrated circuit design system able to generate circuit data enabling a clear grasp of power switch cells and circuit cells whose power is cut off without obstructing the efficiency of the design, a method of same, and a program of same, wherein in the description of RTL data generated ... 09/15/05 - 20050204316 - Predictable design of low power systems by pre-implementation estimation and optimization A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams ... 09/15/05 - 20050204315 - Data structures for representing the logical and physical information of an integrated circuit A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock is a data structure which contains data ... 09/15/05 - 20050204314 - Placement and routing method to reduce joule heating A new method to optimize a signal routing in an integrated circuit is achieved. The method comprises providing a signal routing in an integrated circuit layout. The signal routing comprises a configuration of metal lines in a stack of metal levels. Each metal level is separated from an underlying substrate ... 09/08/05 - 20050198595 - State machine optimization system This invention details a process whereby state assignments and decode logic of a state machine can be mapped to an optimized representation. Optimization may constitute a reduction of gates, an increase of speed, or a reduction of power utilization. Optimization is particularly important when implementing timing systems. A timing system ... 09/08/05 - 20050198594 - Method of designing semiconductor integrated circuit, designing apparatus, and inspection apparatus A method of designing a semiconductor integrated circuit, comprises: replacing a circuit element disposed in the semiconductor integrated circuit with a transistor having a high threshold value or a circuit element having a small juxtaposition number in order to prevent deviation of a signal voltage flowing through the semiconductor integrated ... 08/18/05 - 20050183046 - Method for optimization of logic circuits for routability Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the ... 08/11/05 - 20050177806 - [method for reducing standard delay format file size] A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are impossible to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the ... 07/28/05 - 20050166164 - Method for successive placement based refinement of a generalized cost function A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method relies upon a “look ahead” technique, combined with any generic cost function that can be used to set placement directives. ... 07/14/05 - 20050155001 - Method for designing a semiconductor integrated circuit and a semiconductor integrated circuit A method for designing a semiconductor integrated circuit, includes placing first, second and third cells, respectively including first stage synchronous circuit having signal propagation time, second stage synchronous circuit having a signal propagation time almost equal to the first stage synchronous circuit, and logic circuit; routing wirings so as to ... 07/07/05 - 20050149888 - Method and apparatus for minimizing weighted networks with link and node labels A method and apparatus are provided for optimizing finite state machines with labeled nodes. Under the method, labels from the nodes are shifted onto the labels of the links connected to the nodes. The finite state machine is then optimized. After optimization, the labels on the links are examined to ... 07/07/05 - 20050149887 - Design method and system for optimum performance in integrated circuits that use power management The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage ... 07/07/05 - 20050149886 - Methods for adaptive real time control of a thermal processing system Methods for adaptive real time control of a system for thermal processing substrates, such as semiconductor wafers and display panels. Generally, the method includes creating a dynamic model of the thermal processing system, incorporating wafer bow in the dynamic model, coupling a diffusion-amplification model into the dynamic thermal model, creating ... 07/07/05 - 20050149885 - Rugged heterojunction bipolar transistor power device and the method thereof A rugged heterojunction bipolar transistor (HBT) power device and the optimal design method thereof are disclosed. By combining the epitaxial layer structure design (embedded emitter ballasting resistor and high breakdown voltage) and power cell design (clamping diodes and base ballasting resistor optimization), HBT power devices with excellent power performance and ... 06/23/05 - 20050138579 - Ic design process including automated removal of body contacts from mosfet devices An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a ... 06/23/05 - 20050138578 - Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a ... 06/09/05 - 20050125748 - Circuit area minimization using scaling A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the ... ### FreshPatents.com Support |