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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Error/fault Detection Technique > Parity Bit > Parity Generator Or Checker Circuit Detail Parity Generator Or Checker Circuit DetailParity Generator Or Checker Circuit Detail patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/22/07 - 20070271496 - 3-stripes gilbert ldpc codes A method and apparatus are provided for a coding process of a communication signal. A 3-stripes parity-check matrix is generated from a parity-check matrix of a Gilbert low density parity-check code, where the parity-check matrix of the Gilbert low density parity-check code has a first stripe containing identity matrices and ... 08/23/07 - 20070198905 - Transmitter for a communications network p1T=−D−1(−ET−1A+C)sT. ... 05/31/07 - 20070124660 - Error correcting processing device and error correcting processing method According to one embodiment, modulation processing to convert digital information sequences into a form that meets a request from a recording/reproducing system is performed on a digital information sequence and a dummy bit is added to the sequence, and furthermore, an error correcting parity bit sequence is added to the ... 05/17/07 - 20070113163 - Belief propagation decoder cancelling the exchange of unreliable messages The present invention relates a method and a decoder for decoding codewords, the decoding being performed as message passing on a graph representation of the code, e.g. on low density parity-check (LDPC) code, wherein for each non-zero entry in a parity check matrix, the message matrix elements of a first ... 04/26/07 - 20070094582 - Encoding method to qc code In an encoding method to a self-orthogonal QC code whose parity check matrix is expressed by at least one circulant matrix, a code sequence is generated which satisfies a check matrix. The check matrix is designed so that a column weight w of each circulant matrix is three or larger ... 04/19/07 - 20070089045 - Triple parity technique for enabling efficient recovery from triple failures in a storage array A triple parity (TP) technique reduces overhead of computing diagonal and anti-diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of three storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a ... 04/19/07 - 20070089044 - Method and apparatus for error management To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for ... 04/05/07 - 20070079226 - Semiconductor memory device A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation ... 03/22/07 - 20070067705 - Nand flash memory device performing error detecting and data reloading operation during copy back program operation A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of the parity planes stores a ... 03/15/07 - 20070061693 - Parity error checking and compare using shared logic circuitry in a ternary content addressable memory Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed. ... 03/15/07 - 20070061692 - Parallel parity checking for content addressable memory and ternary content addressable memory Methods and arrangements for parallel parity checking for content addressable memory and ternary content addressable memory during compare cycles are disclosed. Further, methods and arrangements for remedying storage bit corruption are also disclosed. ... 02/08/07 - 20070033514 - Apparatus and method for detecting data error A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with ... 02/08/07 - 20070033513 - Radio communication system, transmitter and decoding apparatus employed in radio communication system Radio-communication-system includes transmitting-station and receiving-station. The transmitting-station includes first-encoding-unit configured to generate plural parity-information by using the different-data, second-encoding-unit configured to encode each of the plural parity-information and each of the different-data to produce plural encoded-data, modulation-unit configured to modulate carriers by the plural encoded-data to generate plural modulated-signals, and ... 02/08/07 - 20070033512 - Method and apparatus for detecting communication errors on a bus A semiconductor memory comprising multi-mode reporting signals, a state register, and parity detectors is disclosed. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enables reporting of communication faults without adding additional signals to the semiconductor memory by being configured ... 01/25/07 - 20070022364 - Data management architecture A performance optimized RAID Level 3 storage access controller with a unique XOR engine placement at the host/network side of the cache. The invention utilizes multiple data communications channels and a centralized cache memory in conjunction with this unique XOR placement to maximize performance and fault tolerance between a host ... 01/11/07 - 20070011600 - Decoding method and apparatus According to a method and apparatus taught herein, a decoding circuit and method decode linear block codes based on determining joint probabilities for one or more related subsets of bits in received data blocks. The use of joint probabilities enables faster and more reliable determination of received bits, meaning that, ... 01/11/07 - 20070011599 - Method, apparatus, and computer program product for testing ability to recover from cache directory errors A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache ... 01/11/07 - 20070011598 - Error detection and correction for encoded data Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of ... 12/14/06 - 20060282757 - On-the fly error checking and correction codec system and method for supporting non-volatile memory An on-the-fly error checking and correcting system and method of supporting a non-volatile memory processes data using an on-the-fly error correction method to be performed between a temporary memory and a flash memory. The flash memory stores actual data read from the temporary memory and parity generated on-the-fly in a ... 12/14/06 - 20060282756 - Device and method for determining a position of a bit error in a bit sequence In a device for determining a position of a bit error in a bit sequence, a check matrix is used which has a predefined number of rows and a predefined number of columns. The check matrix includes a plurality of square submatrices having a submatrix row number and a submatrix ... 12/14/06 - 20060282755 - Random access memory having ecc A memory includes a memory array for storing data, a parity generation and error check circuit configured to receive data from the memory array and detect errors in the data, and error registers configured for storing addresses of failing memory array locations detected by the parity generation and error check ... 09/07/06 - 20060200733 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix may be partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning may be performed in accordance with a rate allocation among the plurality of correlated data sources. ... 08/03/06 - 20060174185 - Method and apparatus for encoding and precoding digital data within modulation code constraints Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of ... 07/13/06 - 20060156214 - Semiconductor memory Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are ... 07/06/06 - 20060150068 - Parity signal generator Provided is a parity signal generator for generating a parity signal by continuously detecting a horizontal sync signal. The parity signal generator includes a first detecting unit for generating a first detection signal by detecting whether the number of a horizontal sync signal is odd or even during an activation ... 06/08/06 - 20060123328 - Recording apparatus, reproducing apparatus and recording medium A first run length encoder implements run length modulation of a first information signal to generate a second information signal of a run-length-limited code while subjecting the second information signal to DSV control and adding a sync signal to the second information signal to get a third information signal. A ... 05/18/06 - 20060107193 - Method and apparatus for efficiently decoding low density parity check code A method and apparatus are provided for decoding a forward error correction code in a mobile communication system using a LDPC code. A check node processor performs check node processing on information received with a plurality of check nodes and an accumulator accumulates check node output values from the check ... 02/16/06 - 20060036933 - Method and apparatus for encoding and decoding data A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f; i, j)} for a code ... 02/09/06 - 20060031745 - Methods and apparatus for constructing low-density parity check (ldpc) matrix Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, ... 02/09/06 - 20060031744 - Method and apparatus for encoding and decoding data A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part ... 11/24/05 - 20050262424 - Efficient design to implement ldpc (low density parity check) decoder Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder's front ... 11/10/05 - 20050251730 - Method and apparatus for encoding and decoding data A deterministic structure for controlled distribution of weight-2 columns is proposed for a parity-check matrix H that reduces the occurrence of undetected frame errors and significantly enhances the code performance in comparison to a randomly-constructed parity-check matrix. H comprises a non-deterministic section H1 and a deterministic section H2, and wherein ... 11/03/05 - 20050246618 - Efficient design to implement min**/min**- or max**/max**- functions in ldpc (low density parity check) decoders Efficient design to implement min**/min**− or max**/max**− functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation presented herein allows for the use of substantially less hardware and surface area within an actual communication device implemented to perform these calculations. In ... 11/03/05 - 20050246617 - Apparatus and method for coding/decoding block low density parity check code with variable block length Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code based on one of a first parity check matrix and ... 11/03/05 - 20050246616 - System, apparatus and method for transmitting and receiving data coded by low density parity check code having variable coding rate A system, an apparatus and a method for transmitting/receiving data coded by a low density parity check matrix code are provided. The apparatus for transmitting data coded by a low density parity check code includes: a low density parity check encoder for encoding input data based on the low density ... 11/03/05 - 20050246615 - Check matrix generation method and check matrix generation device A method of generating a check matrix for a LDPC code includes determining a code length and a coding rate, and a basic matrix; selecting a maximum value of the weight of the column; searching an ensemble of the weights of the row and the column weights; deleting the rows ... 10/13/05 - 20050229091 - Iterative decoding of linear block codes by adapting the parity check matrix A method of decoding linear block code uses an iterative message passing algorithm with a binary image of a parity check matrix of the linear block code, wherein the parity check matrix is adapted from one iteration to another based on the reliabilities of bits in the linear block code. ... 10/13/05 - 20050229090 - Ldpc (low density parity check) coded signal decoding using parallel and simultaneous bit node and check node processing LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified ... 10/13/05 - 20050229089 - Error correction for memory A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity ... 09/29/05 - 20050216821 - Mapping method for encoded bits using ldpc code, transmitting and receiving apparatuses employing this method, and program for executing this method A method for mapping of coded bits using a low density parity check (LDPC) code, comprises encoding information bits by using the LDPC code to generate coded bits, sorting the coded bits in accordance with degrees of variable nodes represented by a parity check matrix of the LDPC code, dividing ... 09/22/05 - 20050210367 - Methods and apparatus for communication using generalized low density parity check codes Techniques and systems for design and use of generalized LDPC codes. A generalized LDPC code comprises a set of codewords producing valid results when submitted to a validator comprising a set of variable nodes and a set of check nodes, with outputs of the variable nodes being connected to inputs ... 09/15/05 - 20050204274 - Parity checking circuit for continuous checking of the party of a memory cell A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with ... 09/15/05 - 20050204273 - Apparatus and method for encoding and decoding a space-time low density parity check code with full diversity gain In a mobile communication system including a transmitter and a receiver, an LDPC code is generated by encoding received information data such that a fifth partial matrix obtained by combining a second partial matrix having even-numbered columns of a first partial matrix corresponding to the information data with a fourth ... 09/15/05 - 20050204272 - Decoding apparatus and method and information processing apparatus and method In implementing calculations in a log area of a message passing algorithm, the results of calculations of a message from a check node to a variable node are to be found readily on a circuit or by a computer. To this end, a decoding apparatus, decoding the LDPC code using ... 09/15/05 - 20050204271 - Method for decoding a low-density parity check (ldpc) codeword wherein the procuct of the LDPC codeword b and a predetermined (M×N) parity check matrix H is zero (H*bT=0) wherein the parity check matrix H represents a bipartite graph comprising N variable nodes (V) connected to M check nodes (C) via edges according to matrix elements hij of the parity ... 07/28/05 - 20050166133 - Method and system for decoding low density parity check (ldpc) codes An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system ... 07/28/05 - 20050166132 - Iphd (iterative parallel hybrid decoding) of various mlc (multi-level code) signals IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation ... 07/21/05 - 20050160351 - Method of forming parity check matrix for parallel concatenated ldpc code Provided is a method of forming a parity-check matrix for a parallel concatenated LDPC code, wherein the parallel concatenated LDPC code is composed of a first LDPC code, a second LDPC code, and an interleaver connecting therebetween. The method includes: the steps of (a) finding a degree distribution of a ... 07/07/05 - 20050149845 - Method of constructing qc-ldpc codes using qth-order power residue An LDPC encoding method in a digital communication system is provided, in which a parity-check matrix H having a plurality of circulant matrices as elements is first generated. A generation matrix G is generated using the parity-check matrix. Information bits are then encoded using the generation matrix G. ... 06/23/05 - 20050138537 - Method and system to encode and decode wide data words A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a parity signal indicating the parity of the corresponding data bits when the hard latch signal is inactive. Each bit-generation circuit drives the ... ### FreshPatents.com Support |