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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Error/fault Detection Technique > Parity Bit Parity BitParity Bit patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070260966 - Error correction method and apparatus for low density parity check An apparatus for and a method of correcting an error using a low density parity check (LDPC) matrix. A resultant matrix is generated by performing XOR and modular 2 operations with respect to the LDPC matrix and a code word vector and a number of 1 bits in the resultant ... 09/20/07 - 20070220410 - Apparatus and method for iterative decoding in a communication system Disclosed are an apparatus and a method for iterative decoding of a plurality of Frame Error Check (FEC) blocks included in a frame in a wireless communication system. The method includes decoding a first FEC block by considering a first decoding iteration count; determining whether there is another FEC block ... 09/13/07 - 20070214403 - Method and apparatus for error detection and correction A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a ... 07/12/07 - 20070162838 - Data writing apparatus and a storage system An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the ... 05/31/07 - 20070124659 - Method and system for data replication A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n−1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data, ... 05/17/07 - 20070113162 - Error code for wireless remote control device and method A method and apparatus to provide error coding for remote control communications. ... 03/15/07 - 20070061691 - System for encoding digital data and method of the same The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a ... 03/15/07 - 20070061690 - Block puncturing for turbo code based incremental redundancy A method of block puncturing for turbo code based incremental redundancy includes a first step (1200) of coding an input data stream into systematic bits and parity bits. A next step (1202) includes loading the systematic bits and parity bits into respective systematic and parity block interleavers in a column-wise ... 01/25/07 - 20070022363 - Redundant 3-wire communication system and method A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data ... 01/11/07 - 20070011597 - Method and apparatus for extracting specific data from bis data Methods and apparatus for extracting a portion of data from a plurality of BIS data are disclosed. The portion of data can be extracted from the plurality of BIS data stored in a first storage unit when those BIS data are accessed by other components. Alternatively, the extraction of the ... 01/11/07 - 20070011596 - Parity check circuit to improve quality of memory device A system and method for internal error checking a semiconductor memory device in a much more area and energy efficient manner. According to the method, a predefined data pattern is written to a plurality of memory cells in the memory device. A pause or waiting time interval is initiated after ... 12/14/06 - 20060282754 - Device, data sector, method of processing data, and signal-bearing medium embodying program of device A device for processing data read from a memory, the data including a word and a parity element with respect to the word, the device including a data recovery circuit that corrects error data in the word using a correction code generated from the parity element. ... 11/23/06 - 20060265636 - Optimized testing of on-chip error correction circuit The present invention includes a memory system with a data memory and a control circuit. The data memory has multiple memory segments, including a data memory array and a parity memory array. The control circuit is configured to receive a set of data having a plurality of bits, at least ... 10/26/06 - 20060242548 - Error correction method for high density disc An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte x m x o. The method comprises the steps of ... 08/31/06 - 20060195775 - Method and apparatus for providing a read channel having combined parity and non-parity post processing A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events ... 08/31/06 - 20060195774 - Error correction circuit and method The present invention includes an error correction circuit with a data memory, a write tree, a parity memory, and a read tree. The data memory is configured to hold a set of data. The write tree is configured to receive the set of data and to generate parity data. The ... 08/17/06 - 20060184864 - Error detection A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but ... 08/10/06 - 20060179401 - Low complexity hybrid arq scheme based on rate compatible zigzag codes A channel coding method, apparatus and computer program product that provides efficient hybrid automatic repeat request (HARQ) comprising low complexity rate compatible zigzag codes, and by further applying data reshaping in combination with rate matching rules to substantially avoid sub-optimality due to puncturing, in combination with irregular parallel concatenation of ... 08/03/06 - 20060174184 - Method and apparatus for encoding and decoding data using a pseudo-random interleaver A pseudo-random bit interleaver and de-interleaver comprising a source for generating pseudo-random numbers and transformation logic that transforms each pseudo-random number generated by the source into a plurality of different pseudo-random numbers. Each of the transformed pseudo-random numbers identifying a parity equation to which an incoming bit will be assigned ... 07/13/06 - 20060156213 - Semiconductor memory During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to ... 07/13/06 - 20060156212 - Semiconductor memory A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a ... 07/13/06 - 20060156211 - Method and system for syndrome generation and data recovery A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one ... 06/15/06 - 20060129904 - Method and apparatus for encoding and decoding data A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb. Base matrix Hb comprises a section Hb1 and a section Hb2. Section Hb2 comprises column hb having weight wh>=3 and H′b2 having a dual-diagonal structure with matrix elements at row i, column j ... 06/08/06 - 20060123327 - Method and circuit for error correction in cam cells A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the following steps: a row parity bit ... 05/18/06 - 20060107192 - Hybrid automatic repeat request system and method A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value ... 02/16/06 - 20060036932 - Method and apparatus for encoding and decoding data A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f, i, j)} for a code ... 02/09/06 - 20060031743 - Method and apparatus for a modified parity check A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity ... 12/15/05 - 20050278612 - Storage device parity computation Provided are a techniques for receiving a modification to at least one data block. Parity blocks that are to be computed for the at least one data block are determined. At least one common term for computations for the determined parity blocks is determined. A first parity block from the ... 10/27/05 - 20050240856 - Hologram recording and reproducing apparatus and hologram reproducing apparatus A hologram recording and reproducing apparatus having a reduced encoding error and high reliability even when a signal-to-noise (S/N) ratio of reproducing signals is deteriorated due to various disturbances. The hologram recording and reproducing apparatus includes: a unit generating a recording low-density parity check code from recording data; a unit ... 10/20/05 - 20050235195 - Apparatus and method for encoding and decoding a low density parity check code with maximum error correction and error detection capability An apparatus and method for decoding a Low Density Parity Check (LDPC) code having a maximum error correction capability and an error detection capability. In the apparatus, a decoder receives a signal, and decodes the received signal according to a second parity check matrix having parity check expressions obtained by ... 10/13/05 - 20050229088 - Systems and methods for ldpc coded modulation Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error ... 10/13/05 - 20050229087 - Decoding apparatus for low-density parity-check codes using sequential decoding, and method thereof Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes: (a) dividing nodes into check nodes for a parity-check message and ... 09/29/05 - 20050216820 - Channel encoding apparatus and method A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order ... 09/15/05 - 20050204270 - Data processing method and apparatus, recording medium, reproducing method and apparatus A row of the data block which is a set of the data sector is distributed to constitute two blocks. In this case, as a distribution condition, an even-number row block of the even-number sector and the odd-number row block of the even-number sector, the odd-number row block of the ... 09/01/05 - 20050193320 - Methods and apparatus for improving performance of information coding schemes Various modifications to conventional information coding schemes that result in an improvement in one or more performance measures for a given coding scheme. Some examples are directed to improved decoding techniques for linear block codes, such as low-density parity-check (LDPC) codes. In one example, modifications to a conventional belief-propagation (BP) ... 09/01/05 - 20050193319 - Method of forward error correction An iterative method of correcting errors in a data block. Bad bytes are first identified using information derived from an 8 B/10 B decoding of the data block. Within each identified bad byte, suspect bits are subsequently identified using information derived from parity decoding of a row of the data ... 07/28/05 - 20050166131 - Method and apparatus for implementing a low density parity check code in a wireless system A low density parity check (LDPC) code is used within a wireless apparatus to perform forward error correction (FEC) coding. In at least embodiment of the invention, a (2000, 1600) bit-length LDPC code is used. ... 07/28/05 - 20050166130 - Signal, storage medium, method and device for encoding, method and device for decoding The invention relates to a signal comprising a runlength limited (RLL) encoded binary d,k channel bitstream 3, wherein parameter d defines a minimum number and parameter k defines a maximum number of zeroes between any two ones of said bitstream 3 or vice versa, comprising a number of sections of ... 07/21/05 - 20050160350 - Compact high-speed single-bit error-correction circuit A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, ... 07/14/05 - 20050154968 - Detection of errors A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but ... 07/07/05 - 20050149844 - Decoding ldpc (low density parity check) code with new operators based on min* operator Decoding LDPC (Low Density Parity Check) code with new operators based on min* operator. New approximate operators are provided that may be employed to assist in calculating one or a minimum value (or a maximum value) when decoding various coded signals. In the context of LDPC decoding that involves both ... 07/07/05 - 20050149843 - Bandwidth efficient coded modulation scheme based on mlc (multi-level code) signals having multiple maps Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to ... 07/07/05 - 20050149842 - Channel encoding/decoding apparatus and method using a parallel concatenated low density parity check code A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second LDPC encoder generates a second component LDPC ... 07/07/05 - 20050149841 - Channel coding/decoding apparatus and method using a parallel concatenated low density parity check code A parallel concatenated low density parity check (LDPC) code having a variable code rate is provided by generating, upon receiving information bits, a first component LDPC code according to the information bits, interleaving the information bits according to a predetermined interleaving rule, and generating a second component LDPC code according ... 07/07/05 - 20050149840 - Apparatus for encoding and decoding of low-density parity-check codes, and method thereof An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parity-check matrix received from the code matrix ... 07/07/05 - 20050149839 - Soft error detection and correction by 2-dimensional parity The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the ... ### FreshPatents.com Support |