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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Data Error Correction > Forward Error Correction By Tree Code (e.g., Convolutional) > Viterbi Decoding Viterbi DecodingViterbi Decoding patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266303 - Viterbi decoding apparatus and techniques Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals. A Viterbi decoder may include a branch metric generator, a trellis interconnect, an add-compare element, a path metric memory, and a traceback element. The ... 10/04/07 - 20070234190 - Viterbi decoding apparatus and viterbi decoding method In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the ... 09/20/07 - 20070220409 - Symbol-level soft output viterbi algorithm (sova) and a simplification on sova A method and apparatus for processing symbols of a block code is presented. A sequence of symbols is received, e.g., from an inter-symbol interference (ISI) channel. A soft value is determined for each symbol using a binary trellis. ... 09/20/07 - 20070220408 - Decoding a concatenated convolutional-encoded and block encoded signal Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented ... 08/02/07 - 20070180352 - Memory system and method for use in trellis-based decoding Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of ... 07/26/07 - 20070174757 - Decoder and method for decoding a tail-biting convolutional encoded signal using viterbi decoding scheme A decoder and method for decoding a tail-biting convolutional encoded signal using Viterbi decoding scheme performs a traceback operation for a first portion of a total code block, which includes a code block of the tail-biting convolutional encoded signal and a padded block. During the traceback operation for the first ... 07/19/07 - 20070168847 - Equalization techniques using viterbi algorithms in software-defined radio systems A system and method for channel equalization using a Viterbi algorithm. Information from an output of a matched filter and channel parameters from a channel estimation circuit are correlated and passed on to a reconfigurable data path. The reconfigurable data path includes a reconfigurable branch metric calculation block. The reconfigurable ... 07/19/07 - 20070168845 - Viterbi decoder In the present invention, the most likely transition source state bits are selected according to the path metric of the state bits corresponding to the state bits that could be taken for the encoded bits to be input, and are stored in the survival path memory. Therefore in the trace ... 05/17/07 - 20070113160 - Convolutional decoding In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes. The convolutional codes may also be block convolutional codes. The lazy ... 05/10/07 - 20070106926 - Viterbi decoding method and apparatus for high speed data transmissions Disclosed are a Viterbi decoding method and apparatus for high speed data transmissions. Branch metric is used with data inputted from a Viterbi decoder used in a communication system, and, when current state metric is used for addition, comparison, and selection, the selection operation is performed after simultaneous addition and ... 05/03/07 - 20070101245 - Method for reducing the computational complexity of viterbi decoder A method for reducing the computational complexity of a Viterbi decoder, which is suitable for all code rates of a convolutional code applied by the Viterbi decoder. The method dramatically reduces the branch metric computation to thus reduce the complexity of implementing the Viterbi decoder, without affecting the capability of ... 04/19/07 - 20070089043 - Viterbi decoder and viterbi decoding method The present invention relates to a Viterbi decoder and a Viterbi decoding method in a register exchange method. The Viterbi decoder receives an encoded bit sequence of a convolutional encoding method from a channel, generates an expanded encoded bit sequence by cyclically adding a part of the encoded bit sequence ... 04/12/07 - 20070083804 - Method and apparatus for analyzing delay in circuit, and computer product An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail ... 04/05/07 - 20070079225 - Trace-ahead method and apparatus for determining survivor paths in a viterbi detector Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a status memory is maintained for ... 03/22/07 - 20070067704 - Deinterleaver and dual-viterbi decoder architecture Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for ... 02/22/07 - 20070044008 - Acs circuit and viterbi decoder with the circuit An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder ... 02/08/07 - 20070033509 - Method and apparatus for concatenated channel coding with variable code rate and coding gain in a data transmission system A novel method and apparatus for efficiently coding and decoding data in a data transmission system is described. A concatenated coding scheme is presented that is easily implemented, and that provides acceptable coding performance characteristics for use in data transmission systems. The inventive concatenated channel coding technique is well suited ... 02/08/07 - 20070033508 - Interative stripewise trellis-based symbol detection method and device for multi-dimensional recording systems When processing a two dimensional data area it is known to be advantageous to divide the two dimensional are into stripes and process each stripe using a stripe-wise detector. The stripe being processed shifts row per row downwards. Each stripe has as its output the bit-decisions of the top bit-row ... 01/11/07 - 20070011594 - Application of a meta-viterbi algorithm for communication systems without intersymbol interference Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed ... 01/04/07 - 20070006058 - Path metric computation unit for use in a data detector A data detector for use in a communication channel is provided. The data detector includes a path metric unit, which is configured to operate at a rate of at least two samples per clock cycle. The path metric unit includes multiple add units and multiple compare units. In the determination ... 10/26/06 - 20060242547 - Decoding method A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of ... 10/26/06 - 20060242546 - Decoding method and apparatus A method and apparatus for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits that together reflect a ... 10/26/06 - 20060242545 - Decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation A decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation (EFM/ESM), which has an analog to digital converter (ADC), an adaptive equalizer and a Viterbi decoder. The ADC receives an analog signal with an EFM or ESM feature, and converts the analog signal into a digital signal with the EFM or ... 09/21/06 - 20060212786 - Viterbi path generation for a dynamic bayesian network Methods, systems, and apparatus are provided to generate a Viterbi path for a DBN. The DBN is converted to a chain of junction trees, where each tree represents a decision-making process. The trees are forwardly iterated and the Viterbi path is generated during the forward iteration (forward pass). This is ... 08/31/06 - 20060195773 - Viterbi decoder architecture for use in software-defined radio systems A reconfigurable Viterbi decoder comprising a reconfigurable data path and a programmable finite state machine that controls the reconfigurable data path. The reconfigurable data path comprises a plurality of reconfigurable functional blocks including: i) a reconfigurable branch metric calculation block; and ii) a reconfigurable add-compare-select and path metric calculation block. ... 08/31/06 - 20060195772 - Method and apparatus for evaluating performance of a read channel Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, ... 08/31/06 - 20060195771 - Application of a meta-viterbi algorithm for communication systems without intersymbol interference Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed ... 07/27/06 - 20060168501 - Viterbi decoder for executing trace-back work in parallel and decoding method A Viterbi decoder for executing a trace-back work in parallel and a decoding method. The Viterbi decoder includes a branch metric calculator which calculates a branch metric from a branch code passing each state on a trellis diagram and a predetermined input code, at least one adder/comparator/selector which adds the ... 07/06/06 - 20060150067 - Error detector, semiconductor device, and error detection method An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift ... 06/29/06 - 20060143554 - Scalable traceback technique for channel decoder Apparatus, system, and method for scalable traceback techniques for channel decoding are described. ... 06/15/06 - 20060129903 - Prediction device and method applied in a viterbi decoder A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the ... 04/20/06 - 20060085730 - Distributed ring control circuits for viterbi traceback Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding. ... 03/23/06 - 20060064628 - Viterbi decoder with direct current restoration A decoder for detecting data within an input signal with attenuated low frequency components that comprises a Viterbi decoder, is disclosed. Viterbi decoder internal data is used along with its output bits to reduce delay between the restored direct current (DC) component and the input signal to zero. As a ... 02/02/06 - 20060026494 - Modified soft output viterbi algorithm for truncated trellis A method, system and computer program product for obtaining the reliability values for the hard decisions obtained by a Viterbi equalizer in a wireless communication system. A difference parameter is obtained for each Viterbi state at a stage while advancing the Viterbi trellis by the stage. The difference parameter for ... 01/26/06 - 20060020876 - Method for simplifying a viterbi decoder and a simplified viterbi decoder using the same A method for simplifying a Viterbi decoder includes receiving a partial response, and determining an amount of redundant selector modules according to a tap number of the partial response; analyzing an output signal of the redundant selector modules for determining an initial input signal; and taking Viterbi decoding process to ... 01/19/06 - 20060015800 - Method for determining output signals of a viterbi decoder A method for determining output signals of a Viterbi decoder. The method includes: (a) receiving a plurality of digital signals through a path memory module of the Viterbi decoder with decoding an input signal; (b) comparing the received digital signals in step (a) with a default number; and (c) determining ... 01/19/06 - 20060015799 - Proxy-based error tracking for real-time video transmission in mobile environments This invention provides an efficient method of error tracking which quickly recovers the error packet of data. A side information is sent along with a normal video stream that can be used by an intermediate network node in order to improve the quality of the video transmission. The intermediate node ... 01/19/06 - 20060015798 - Viterbi bit detection method and device The present invention relates to a Viterbi bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier along an N-dimensional channel tube, N being at least two, of at least two bit rows one-dimensionally evolving along a first direction and ... 12/29/05 - 20050289445 - Data reproducing apparatus avoiding selection of incorrect path An apparatus for reproducing data includes a branch metric computation unit and a plurality of parallel computation units, each of which includes path metric computation units configured to compute path metric values based on branch metric values, path metric memories operable to store the path metric values to be used ... 09/01/05 - 20050193318 - Adaptive waveform equalization for viterbi-decodable signal and signal quality evaluation of viterbi-decodable signal The waveform equalizing device includes: an FIR filter for generating an equalized signal pattern y(i, n) on the basis of equalization of a waveform of the reproduced signal pattern u(i, n); a Viterbi decoding circuit for detecting a path metric difference s(n) between a correct path determined as a survivor ... 08/04/05 - 20050172211 - Data demodulation apparatus and method The invention provides a data decoding apparatus and method by which the data rate can be discriminated at a high speed using a Viterbi decoding process. Receive data are successively Viterbi decoded beginning with the top thereof. At a point of time when receive data which may possibly be end ... 08/04/05 - 20050172210 - Add-compare-select accelerator using pre-compare-select-add operation How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result. The first result or the second result may be selected in response to the identification, and the ... 07/07/05 - 20050149838 - Unified viterbi/turbo decoder for mobile communication systems A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control ... 06/02/05 - 20050120287 - Branch metric computation and add-compare-select operation in viterbi decoders An apparatus for branch metric computation and add-compare-select operation in a rate 1/n Viterbi decoder with a constraint length of K. The apparatus of the invention includes a branch metric generator and an add-compare-select unit. The branch metric generator calculates a plurality of branch metrics each of which is a ... ### FreshPatents.com Support |