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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Data Error Correction > Forward Correction By Block Code > Code Based On Generator Polynomial Code Based On Generator PolynomialCode Based On Generator Polynomial patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266301 - Techniques for generating cyclic redundancy check (crc) values Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values ... 09/27/07 - 20070226596 - Apparatus and method for reduced power consumption communications over a physical interconnect A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second ... 09/13/07 - 20070214402 - Method and system for bluetooth decoding where RX(n) may include the received bit sequence. The codeword with a metric value equal to M0 may be selected, if the calculated remainder value is equal to 0. ... // - 14 - ... 08/23/07 - 20070198901 - Configurable interface for connecting various chipsets for wireless communication to a programmable (multi-)processor Among the embodiments of the present invention, one of the embodiment thereof includes a heterogeneous, high-performance, scalable processor including at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, ... 08/16/07 - 20070192668 - Implicit message sequence numbering for locomotive remote control system wireless communications A method for providing wireless communications between a locomotive control unit (LCU) (14) on board a locomotive (16) and a portable operator control unit (OCU) (12) for use in controlling operation of the locomotive from an off-board location includes calculating a transmit bit error check value for a wireless message. ... 07/19/07 - 20070168841 - Frame format for millimeter-wave systems A single frame format is employed by a millimeter wave communication system for single-carrier and OFDM signaling. A Golay-coded sequence in the start frame delimiter (SFD) field identifies the data transmission as single carrier or OFDM. Complementary Golay codes are employed in a channel estimation field to allow a perfect ... 06/28/07 - 20070150797 - Partial iterative detection and decoding apparatus and method in mimo system A partial iterative detection and decoding apparatus in a Multiple Input Multiple Output (MIMO) system includes a detector for detecting signals received through at least one receive antenna to generate a first soft decision value, a decoder for decoding the first soft decision value to generate a second soft decision ... 06/28/07 - 20070150796 - Decoding method for detecting plsc from frames of satellite broadcasting system Provided is a decoding method for detecting Physical Layer Signaling Codes (PLSCs) from frames of a satellite broadcasting system. The method includes: a) acquiring a summation vector and a subtraction vector from an inputted symbol vector; b) performing parallel Reed-Muller (32,6) decoding onto the summation and subtraction vectors based on ... 06/28/07 - 20070150795 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself ... 06/28/07 - 20070150794 - Error correction using finite fields of odd characteristic on binary hardware Binary data representing a code word of an error-correcting code is used for calculating a syndrome, wherein a given portion of the binary data comprises k groups of data bits and represents a field element of the finite field GF(pk), p being an odd prime number, the field element comprising ... 05/31/07 - 20070124653 - Method and system for detecting a security violation using an error correction code A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP) ... 05/24/07 - 20070118790 - Apparatus and method for stopping iterative decoding in a mobile communication system An apparatus and method are provided for stopping iterative decoding in a channel decoder of a mobile communication system. Constituent decoding of received signals is performed and decoded signals are output. Hard decision processes for the decoded signals are performed and hard-decided signals are output. The hard-decided signals are cyclic ... 04/19/07 - 20070089041 - Duplicate detection circuit for receiver A duplicate detection circuit for a receiver includes a CRC generator for generating a CRC value of frame header information, and a control circuit coupled to the CRC generator. The control circuit has a first output, a second output, and a control input. When the control input is not set, ... 03/29/07 - 20070074095 - Method and apparatus for n‘packet level mesh protection Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload ... 03/15/07 - 20070061688 - Decoding error correction codes using a modular single recursion implementation Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, a plurality of modules are used to calculate the current and previous ... 01/18/07 - 20070016842 - Method and apparatus for configuring a cyclic redundancy check (crc) generation circuit to perform crc on a data stream A method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream are disclosed. The method includes storing a generator polynomial associated with a CRC equation in a register, where the generator polynomial has a length capable of varying such that the ... 10/19/06 - 20060236211 - Cyclic redundancy check modification for length detection of message with convolutional protection In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, appending the flipped ... 08/31/06 - 20060195768 - Techniques for performing reduced complexity galois field arithmetic for correcting errors Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to ... 06/22/06 - 20060136801 - Methods and apparatus for dynamically reconfigurable parallel data error checking In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in ... 06/08/06 - 20060123325 - Condensed galois field computing system A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive ... 03/30/06 - 20060069980 - Crc counter normalization The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization ... 02/23/06 - 20060041825 - Cyclic code circuit with parallel output A cyclic code is generated by a circuit including a group of logic gates that generate one multiple-bit code segment from another multiple-bit code segment. The logic gates may, for example, receive B initial bits, where B is the degree of the generator polynomial, and generate one complete (2B−1)-bit code ... 02/23/06 - 20060041824 - Method and apparatus for computing parity characters for a codeword of a cyclic code A method for computing parity characters for a codeword of a cyclic code successively generates a sum of an output value and a respective message character of a first message section adjacent to parity characters within a first block. The method then successively multiplies a respective sum by corresponding coefficients ... 01/26/06 - 20060020875 - Multi-rate viterbi decoder A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code ... 12/22/05 - 20050283714 - Method and apparatus for multiplication in galois field, apparatus for inversion in galois field and apparatus for aes byte substitution operation A method and apparatus for multiplication in a Galois field. The method of multiplication in a Galois field (GF) for preventing an information leakage attack by performing a transformation of masked data and masks in GF(2n) includes: receiving a plurality of first and second masked input data, a plurality of ... 12/08/05 - 20050273690 - System and method for detecting codeword errors in error correction code or cyclic redundancy check code A method for detecting errors in data that comprises encoding the data into a codeword using a generation polynomial, transmitting the codeword over a channel, receiving the transmitted codeword, generating syndromes for the received codeword using the generation polynomial, the syndromes comprising a plurality of syndrome symbols, providing a plurality ... 10/20/05 - 20050235192 - Method and apparatus for preventing a false pass of a cyclic redundancy check at a receiver during weak receiving conditions in a wireless communications system At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those ... 10/13/05 - 20050229086 - Randomizer systems for producing multiple-symbol randomizing sequences A system that produces one or more non-repeating randomizer sequences of up to 2m-1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The system combines the randomizer sequence with all the symbols of ECC ... 10/13/05 - 20050229085 - Method and apparatus for embedding an additional layer of error correction into an error correcting code The present invention relates to a method of embedding an additional layer of error correction into an error correcting code, wherein information is encoded into code words of said code over a first Galois field and wherein a number of code words rare arranged in the columns of a code ... 09/29/05 - 20050216818 - Recording/regenerating device, method of encoding error correction, method of recording data Embodiment of the invention is to make the number of interleave sequences and the number of redundant bits as small as possible without increasing the number of bits per symbol so much. By encoding data into an error-correcting code by using an algebraic geometric code consisting of an algebraic curve ... 09/22/05 - 20050210364 - Channel coding/decoding apparatus and method for a cdma mobile communication system A apparatus for generating (2k-2t) first order Reed-Muller codes from 2k first order Reed-Muller codes based on k input information bits. The apparatus includes a code generator configured to generate (2k-2t) bits first order Reed-Muller codes, and an encoder for multiplying the k input information bits with the (2k-2t) bits ... 09/22/05 - 20050210363 - Error correction coding method using at least twice a same elementary code, coding method, corresponding coding and decoding devices The invention relates to an error correction coding method, using at least two distinct sections of a predetermined elementary code, associating an arrival vector (s2, s3) with a starting state vector (s0, s1), according to a vector of branch labels (b0, b1, b2, b3), defining a code word, two sections ... 09/15/05 - 20050204268 - Decoding and error correction for algebraic geometric codes A method of decoding a one-point algebraic geometric code defined on an algebraic curve of the kind C(a,b), represented by an equation of degree b in X and of degree a in Y, comprises, for any received word, a step of locating transmission errors affecting said received word. The correction ... 07/07/05 - 20050149834 - (18, 9) error correction code for double error correction and triple error detection where β is a root of the polynomial x17−1 in the finite field of 256 elements. Logic circuitry for efficiently determining the locations of single and double errors as well as for detecting the presence of uncorrectable errors is also disclosed. ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 10 - ... // - 9 - ... // - 13 - ... // - 15 - ... // - 16 - ... // - 8 - ... // - 4 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 1 - ... // - 2 - ... // - 1 - ... // - 5 - ... // - 11 - ... // - 14 - ... // - 7 - ... // - 12 - ... // - 6 - ... // - 3 - ... 07/07/05 - 20050149833 - H-matrix for error correcting circuitry A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first ... 07/07/05 - 20050149832 - Methods and apparatus for coding and decoding data using reed-solomon codes Methods and apparatus are provided for encoding data. The method includes (a) providing a first table of first component values multiplied by code generator coefficients and a second table of second component values multiplied by the code generator coefficients, (b) determining a Galois field element based on a message symbol ... ### FreshPatents.com Support |