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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Data Error Correction > Forward Correction By Block Code > Memory Access Memory AccessMemory Access patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266298 - Apparatus for improving data access reliability of flash memory An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and ... 11/15/07 - 20070266297 - Controller and storage device having the same A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the ... 11/15/07 - 20070266296 - Nonvolatile memory with convolutional coding Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be ... 11/15/07 - 20070266295 - Convolutional coding methods for nonvolatile memory Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be ... 11/08/07 - 20070260962 - Methods and apparatus for a memory device with self-healing reference bits A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the ... 11/01/07 - 20070255998 - Memory command unit throttle and error recovery A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the ... 10/25/07 - 20070250756 - High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a ... 10/25/07 - 20070250755 - Dormant error checker In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein. ... 10/04/07 - 20070234182 - Error checking and correction (ecc) system and method A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The ... 10/04/07 - 20070234181 - Error correction device and methods thereof A device for error correction and methods thereof are disclosed. The method includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a ... 09/27/07 - 20070226591 - Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to ... 09/27/07 - 20070226590 - Semiconductor memory in which error correction is performed by on-chip error correction circuit A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected ... 09/27/07 - 20070226589 - System and method for error correction in cache units A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first ... 09/06/07 - 20070208989 - System and method of utilizing a network to correct flawed media data A system and method of utilizing a network to correct flawed media data. The media device includes a processor, a memory, a network adapter, a removable media interface, an error-correction module, and a communication module. The network device enables the media device to connect to the network and server. The ... 08/16/07 - 20070192664 - Semiconductor memory A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted ... 08/09/07 - 20070186141 - Method and information apparatus for improving data reliability Reliability of data that is stored in a disk drive by a storage system is enhanced. An information apparatus has a processor, a memory, an interface control unit, and a system control unit, which controls communications between the processor, the memory, and the interface control unit. The system control unit ... 07/19/07 - 20070168837 - Method for implementing error-correction codes in flash memory The present invention teaches a method and device for implementing error-correction code (ECC) in flash memory. The present invention discloses methods which utilize a modified ECC algorithm, and a flash memory device which incorporates these methods. ... 07/19/07 - 20070168836 - Repair bits for a low voltage cache A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired ... 07/12/07 - 20070162826 - Method for detecting error correction defects A method, device and system for detecting error correction defects calculates a written error checking and correction (ECC) code for a written data and writes the written data and the written ECC code into a plurality of memory cells. When data is read from the memory cells including data representing ... 07/12/07 - 20070162825 - Unidirectional error code transfer for a bidirectional data link A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link ... 06/28/07 - 20070150792 - Memory module comprising a plurality of memory devices A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second ... 06/28/07 - 20070150791 - Storing downloadable firmware on bulk media A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and the parity data is stored with the portions of data, the corrupted data may be reconstructed from the parity data and ... 06/28/07 - 20070150790 - Method of storing downloadable firmware on bulk media A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and the parity data is stored with the portions of data, the corrupted data may be reconstructed from the parity data and ... 06/14/07 - 20070136640 - Defect detection and repair in an embedded random access memory An integrated circuit comprises a volatile memory array, a non-volatile memory array, a plurality of registers, and a plurality of flip-flops. A portion of the non-volatile memory array is used for storing an address of a defective memory cell of the volatile memory array. The plurality of registers is coupled ... 06/14/07 - 20070136639 - Method for adapting a memory system to operate with a legacy host originally designed to operate with a different memory system A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. ... 06/07/07 - 20070130496 - Apparatus, method and computer program product for reading information stored in storage medium, and storage medium for storing information based on charge amount A reproducing apparatus includes a storage unit including a plurality of memory elements each capable of holding an electric charge, each memory element indicating a 2-bit code which is related to each other so that the Hamming distance between adjacent codes is unity in four ranges determined by a charge ... 05/31/07 - 20070124648 - Data protection method One embodiment disclosed is method for protecting data stored on at least one storage unit against uncorrectable media errors. The method includes associating a given redundancy set of at least one redundancy information sector (R) with a given data set of at least two data information sectors (D). The information ... 05/31/07 - 20070124647 - Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield A method and system for a non-volatile memory (NVM) with multiple bits error correction and detection for improving production yield are provided. Forward error correction (FEC) operations and cyclic redundancy check (CRC) operations may be utilized in an NVM array integrated in a chip to correct errors in memory elements ... 05/17/07 - 20070113155 - Semiconductor storage device equipped with ecc function A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the ECC circuit when a data width of ... 05/17/07 - 20070113154 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/17/07 - 20070113153 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/17/07 - 20070113152 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/17/07 - 20070113151 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/17/07 - 20070113150 - Apparatus and method for memory asynchronous atomic read-correct-write operation A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each ... 05/03/07 - 20070101240 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/03/07 - 20070101239 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/03/07 - 20070101238 - Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each ... 05/03/07 - 20070101237 - Memory card and memory controller A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area ... 05/03/07 - 20070101236 - Method and system for performing function-specific memory checks within a vehicle-based control system Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of sub-module checksums. A checksum for one or more subsystem modules is initially calculated based upon a checksum routine and the values of data residing ... 04/26/07 - 20070094572 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 04/26/07 - 20070094571 - Ecc circuit of semiconductor memory circuit An error detection and correction (EEC) circuit of a semiconductor memory device includes first through m'th ECC engines (m is a natural number) connected in series, and a flipflop that receives output data from the m'th ECC engine, outputs an error detection/correction signal in response to a clock signal, and ... 04/26/07 - 20070094570 - Error detection in storage data Provided are a method, system, and an article of manufacture for detecting errors while accessing a storage device. A host system writes an identical initialization pattern into each block of a plurality of blocks while formatting the storage device. Each block of the plurality of blocks has a checksum field ... 04/26/07 - 20070094569 - Determining hard errors vs. soft errors in memory In a preferred embodiment, the invention provides a method for determining soft and hard errors in memory. First one or more errors are detected in memory. Next correct data is written back to the memory locations were the error(s) were detected. Data is then read from the memory locations where ... 04/19/07 - 20070089034 - Method of error correction in mbc flash memory A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical ... 04/19/07 - 20070089033 - System and method of accessing non-volatile computer memory A system and method for organizing a non-volatile memory is disclosed. The system includes a non-volatile memory with a first data region and a first redundant memory area associated with the first data region. The first redundant memory area includes a first portion associated with a first data sector. The ... 04/19/07 - 20070089032 - Memory system anti-aliasing scheme Embodiments of the invention are generally directed to systems, methods, and apparatuses for a memory device anti-aliasing scheme. In an embodiment, a memory controller includes an error check agent to receive a codeword from a rank of memory and to provide an error indication in response to detecting a correctable ... 04/19/07 - 20070089031 - Methods and arrangements to remap degraded storage blocks Methods and arrangements to remap degraded storage blocks on, e.g., IDE/ATA drives are disclosed. Embodiments may comprise a host and/or a data storage device for, e.g., a handheld device. The host may comprise remapping logic. In many embodiments, the remapping logic may track degraded storage blocks as indicated by the ... 04/05/07 - 20070079219 - Semiconductor memory device having data holding mode using ecc function When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period ... 04/05/07 - 20070079218 - Semiconductor memory device having data holding mode using ecc function When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence ... 04/05/07 - 20070079217 - Method and apparatus for implementing error correction coding in a random access memory Apparatuses and methods for utilizing error correction code in a data buffer or data storage device. In one variation, a single memory device is utilized to store both the data and the associated error correction code. The data and the associate error correction codes are stored on separate memory banks ... 04/05/07 - 20070079216 - Fault tolerant encoding of directory states for stuck bits A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field ... 03/29/07 - 20070074094 - Method for detecting code error A method for detecting a code error is proposed. The method is mainly applied for detecting whether there is a code error existed in the accessed data, in other words, for detecting whether there is only an error bit existed in the accessed data. After the data are accessed, the ... 03/29/07 - 20070074093 - Nand flash memory controller exporting and nand interface A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the ... 03/29/07 - 20070074092 - Techniques to determine integrity of information Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and ... 03/22/07 - 20070067699 - Semiconductor integrated circuit device A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs ... 03/22/07 - 20070067698 - Techniques to perform prefetching of content in connection with integrity validation value determination Techniques are described herein that are capable to perform a retrieval of content from a destination buffer prior to completion of determining an integrity validation value on content of a source buffer. In some cases, if an integrity checking operation on content of the source buffer is successful, the content ... 03/15/07 - 20070061683 - Error correction apparatus and method for data stored in memory An error correction device includes: a main memory for storing data; a memory bus, coupled to the main memory; and a correction module, directly connected to the memory bus, for reading an error data from the main memory, generating a correct data according to the error data, and writing the ... 02/22/07 - 20070044004 - Cache memory device, semiconductor integrated circuit, and cache control method A memory cache device in which a storage area used for a memory data protection function is effectively used at the time of not using the memory data protection function. A mode selection signal makes ECC code sections for storing an ECC code function as a storage area for storing ... 02/22/07 - 20070044003 - Method and apparatus of detecting and correcting soft error Briefly, a method and apparatus of detecting and correcting soft error in a way of a ways group of a cache bank The detection of the soft error may be done by comparing between two replicas of the ways groups. The correction may be done by copying data from one ... 02/15/07 - 20070038919 - Semiconductor memory device A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such ... 02/08/07 - 20070033491 - Repair techniques for memory with multiple redundancy In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a ... 02/08/07 - 20070033490 - Semiconductor memory module with error correction A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board ... 02/08/07 - 20070033489 - Semiconductor memory device and method of operating the same A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as ... 02/08/07 - 20070033488 - Persistent error detection in digital memory A method for detecting a persistent error in a digital memory is provided. Error location information for errors detected in the digital memory is received. A group of the errors that are associated with a same error position is identified from the error location information. A number of the errors ... 02/08/07 - 20070033487 - Semiconductor memory device and method of operating the same A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at ... 01/11/07 - 20070011580 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks. ... 01/11/07 - 20070011579 - Storage system, management server, and method of managing application thereof In a storage system having a plurality of disk array devices connected through a network to a host for running an application, and a management server for monitoring the disk array devices, the disk array device includes a physical disk error detecting unit for detecting an error in a physical ... 01/11/07 - 20070011578 - Reducing false positives in configuration error detection for programmable devices A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data ... 01/11/07 - 20070011577 - Trie-type memory device with a compression mechanism The invention relates to a tri-type memory device comprising a compression mechanism. According to the invention, the memory stores binary patterns that are associated with respective references. Data chains are analyzed by successive section of K bits (K>1) in order to extract one of the references when there is a ... 01/11/07 - 20070011576 - Data managing method and optical disc drive for handling an decoding error of a readback data retrieved from an optical disc A data managing method and optical disc drive capable of handling decoding errors of readback data retrieved from an optical disc. The data managing method includes providing a buffering pointer and a decoding pointer; utilizing the buffering pointer to indicate an address utilized for storing an un-decoded readback data; controlling ... 01/11/07 - 20070011575 - Autonomous method and apparatus for mitigating soft-errors in integrated circuit memory storage devices at run-time Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device ... 01/11/07 - 20070011574 - Memory device A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are ... 01/04/07 - 20070006057 - Semiconductor memory chip and method of protecting a memory core thereof Provided is a semiconductor memory chip that includes a memory core and an interface circuit having decoding, selecting and scheduling circuit means for decoding from a signal frame a respective type of data signals, command signals and address signals, selection of actions which are required in the memory chip according ... 12/28/06 - 20060294449 - Storage device that transfers block data containing actual data and check code from storage device to host computer A method of transferring data from a storage device transfers block data to a host computer, has a first data transfer processing of temporarily holding only actual data by excluding a check code from the block data, and transferring the actual data to the host computer; and a second data ... 12/14/06 - 20060282747 - Ecc flag for testing on-chip error correction circuit The present invention includes an error correction circuit with a data memory, a control circuit, a parity memory, and a recorder. The data memory is configured to receive and store a set of data. The control circuit is configured to receive the set of data and to generate parity bits ... 11/16/06 - 20060259848 - System and method for enhanced error detection in memory peripherals A system and method for detecting and correcting errors in a memory in a device includes generating an error value of data stored at first predetermined locations in a first memory. The generated error value is compared to a corresponding error value stored in an error memory, each value in ... 11/02/06 - 20060248434 - Non-systematic coded error correction Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity ... 10/26/06 - 20060242539 - Nonvolatile ferroelectric memory device including failed cell correcting circuit A nonvolatile ferroelectric memory device including a failed cell correcting circuit which effectively processes randomly distributed cell data. The nonvolatile ferroelectric memory device checks horizontal parity of a main memory cell array and stores the parity in a horizontal parity check cell array, and checks vertical parity of a main ... 10/26/06 - 20060242538 - Multi-bit nonvolatile ferroelectric memory device having fail cell repair circuit and repair method thereof A multi-bit nonvolatile ferroelectric memory device comprises a plurality of memory cell arrays each including a plurality of multi-bit unit cells connected serially, and a correcting block adapted and configured to group the predetermined number of multi-bit unit cells in one memory group to store a data level signal corresponding ... 10/26/06 - 20060242537 - Error detection in a logic device without performance impact An apparatus and method to perform error detection in a logic device without performance impact. The apparatus includes an Error Detection Device (EDD) coupled to a memory module and a processor. The memory module connects to the processor. As information transfers from the memory module to the processor, the EDD ... 10/19/06 - 20060236207 - Error detection, documentation, and correction in a flash memory device A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as ... 10/19/06 - 20060236206 - Semiconductor memory device In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a ... 10/19/06 - 20060236205 - Storage control circuit, and method for address error check in the storage control circuit A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written ... 10/19/06 - 20060236204 - Memory device with serial transmission interface and error correction mehtod for serial transmission interface The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial ... 10/12/06 - 20060230329 - Chip correct and fault isolation in computer memory systems Systems and methods for implementing chip correct and fault isolation in computer memory systems are disclosed. An exemplary method may include interleaving check bits with a data word to form at least one interleaved data word. The method may also include writing the at least one interleaved data word to ... 10/12/06 - 20060230328 - Device and method for recording information A device for recording records information in blocks having logical addresses at a physical address in a track on a record carrier. The logical addresses are translated into the physical addresses in dependence of defect management information, such as primary and secondary defect lists and remapping tables, maintained in defect ... 10/12/06 - 20060230327 - Apparatus for and method of recording digital information signals A recording apparatus for recording digital information signals on a removable rewritable disc like recording medium has been proposed. The apparatus comprises writing means (21, 22, 25) for recording the digital information signals and controls means (20) for controlling the recording. The apparatus is capable of performing initialization, formatting and ... 09/28/06 - 20060218469 - Low power cost-effective ecc memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves ... 09/28/06 - 20060218468 - Memory initialization device, memory initialization method, and error correction device In a case where a data missing area has occurred when a memory portion in a SYNC information set buffer memory is being overwritten with SYNC information sets (error correction data), an initialization DMA unit obtains the starting address and the end address in the data missing area from an ... 09/28/06 - 20060218467 - Memory having a portion that can be switched between use as data and use as error correction code (ecc) A memory has an ECC-enabled mode and an ECC-disabled mode in which the portion of the memory dedicated to use as storing ECC in the ECC-enabled mode is used for storing general purpose information (data) in the ECC-disabled mode. This is achieved in a non-volatile memory (NVM) by having the ... 09/21/06 - 20060212777 - Medium storage device and write path diagnosis method A medium storage device writes the data on a medium by a write element and executes the diagnosis of a write system path without dropping the performance of the device. For a write command from a host, write data is stored in a data memory, a response is returned to ... 09/07/06 - 20060200729 - Data storing method of dynamic ram and semiconductor memory device When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error ... 09/07/06 - 20060200728 - Synchronous semiconductor storage device having error correction function A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines ... 09/07/06 - 20060200727 - Semiconductor device When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention ... 09/07/06 - 20060200726 - Failure trend detection and correction in a data storage array Method and apparatus for detecting and correcting parametric failure trends in a data storage array. A plurality of data storage devices, such as hard disc drives, are arranged to form a multi-device addressable memory array space. A controller controls access to the array space, and is configured to accumulate operational ... 08/17/06 - 20060184858 - Memory circuit, such as a dram, comprising an error correcting mechanism A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address ... 08/10/06 - 20060179397 - Interface for generating an error code An error code is generated by generating error correction data from a data sequence. These error correction data together with the data sequence are then written to a memory unit so as to be read from the memory unit. During the reading or during the writing, one bit in the ... 07/27/06 - 20060168499 - Data archive verify software The invention is directed to verify software to determine the quality and accuracy of data recorded on an optical data storage disk by an optical disk drive. A verify software module receives error information from the optical disk drive indicative of errors associated with the recovered data. The verify software ... 07/20/06 - 20060161833 - Software testing A system and method for generating executable units suitable for unit testing of a module for integration errors, the method comprising; recording, for a module, an interface specification that specifies pre-condition constraints on input values of methods of the module and post-condition constraints on output values of the methods of ... 07/13/06 - 20060156195 - Information recording medium, recording apparatus and method for an information recording medium, reproducing apparatus and method for an information recording medium computer program for controlling record or reproduction, and data structure including co An information recording medium (100) is provided with: a user data area (108) for recording therein record data; a plurality of temporary defect management areas (104, 105) for temporarily recording therein defect management information (120) which is a basis of defect management for a defect in the data area; and ... 07/13/06 - 20060156194 - Method for reallocation of a memory of a subsystem, and subsystem The method for reallocation of a memory, in particular a command memory, wherein the memory is part of a subsystem and the memory is assigned to a processing unit available on the subsystem, and wherein the occurrence of a memory error in the memory (RAM) is detected, whereupon the content ... 07/13/06 - 20060156193 - Error test for an address decoder of a non-volatile memory A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching ... 07/13/06 - 20060156192 - Semiconductor memory device Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit ... 07/13/06 - 20060156191 - Memory addressing error protection systems and methods Systems and methods for protecting against memory addressing errors are disclosed. When data is to be written to a storage location in a memory, address protection information is calculated based on an address of the storage location, and combined address and data protection information is calculated based on both the ... 07/13/06 - 20060156190 - System and method for efficient use of memory device bandwidth In a device that utilizes a memory device, the access bandwidth of the memory device is efficiently utilized by determining a set of operations to be performed on information stored in the memory device, and sorting the operations into an order so as to minimize the number of accesses to ... 07/13/06 - 20060156189 - Method for copying data in reprogrammable non-volatile memory The present invention presents methods for improving data relocation operations. In one aspect, rather than check the quality of the data based on its associated error correction code (ECC) in every relocation operation, it is determined whether to check ECC based on predetermined selection criteria, and if ECC checking is ... 07/06/06 - 20060150062 - Method and system for correcting soft errors in memory circuit A method and a system for correcting a soft error in a memory circuit during a stand-by mode are disclosed. According to the disclosure, after reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, ... 06/22/06 - 20060136800 - Memory system and semiconductor memory device A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection ... 06/08/06 - 20060123323 - Interleaving apparatus and method for orthogonal frequency division multiplexing transmitter An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of ... 06/08/06 - 20060123322 - Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, ... 06/08/06 - 20060123321 - System and method for reconstructing lost data in a storage system A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method. ... 06/01/06 - 20060117242 - Methods and devices for defect and reallocation management on write-once media The invention relates to a method and a device for random write and overwrite to a write once recordable medium, a method and a device for defect management on a write once recordable medium, a method and a device for undo changes made to a write once recordable medium, and ... 06/01/06 - 20060117241 - Method and apparatus for managing disc defects A defect management method and apparatus including (a) recording data in predetermined units of data; (b) verifying the recorded data to detect an area of the disc in which a defect exists; (c) designating an area from the defective area to the following area containing data as the defective area ... 05/18/06 - 20060107185 - Recording medium having spare area for defect management and information on defect management, and method of allocating spare area and method of managing defects A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary ... 04/13/06 - 20060080589 - Memory interface with write buffer and encoder A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data ... 04/06/06 - 20060075320 - Method of detecting and correcting errors for a memory and corresponding integrated circuit A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in ... 03/23/06 - 20060064624 - Writing and reading of data in probe-based data storage devices Methods and apparatus are provided for controlling writing and reading of data in an array of A storage fields of a probe-based data storage device in which data is written to and read from the array of storage fields by a corresponding array of probes. One method provides error-tolerance by ... 03/16/06 - 20060059406 - Memory with embedded error correction codes A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus ... 03/16/06 - 20060059405 - Using a phase change memory as a high volume memory A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may ... 03/09/06 - 20060053360 - Methods and apparatus for correcting errors in data read from a disk drive Data requested from a disk drive by a host is read continuously from sectors in tracks on a rotating disk and is temporarily stored in buffer memory within the disk drive. Before releasing the sectors for host access, each sector is checked for errors, and if errors are identified, error ... 02/23/06 - 20060041823 - Method and apparatus for storing and retrieving multiple point-in-time consistent data sets A method, apparatus, and article of manufacture containing instructions for processing multiple point-in-time consistent data sets. The method consists of creating multiple point-in-time data sets associated with a backup appliance which is associated with backup storage. Upon the transfer of a first update from a primary storage controller to the ... 02/09/06 - 20060031739 - Converting circuitforpreventing wrong errorcorrection codes from occurring due to an error correction rule duringdata reading operation A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0×FF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and ... 01/05/06 - 20060005107 - Error correction in rom embedded dram Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM). ... 12/29/05 - 20050289442 - Error correction in rom embedded dram Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM). ... 12/29/05 - 20050289441 - Semiconductor device improving error correction processing rate In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level ... 12/29/05 - 20050289440 - System and method for controlling application of an error correction code (ecc) algorithm in a memory subsystem In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption ... 12/29/05 - 20050289439 - System and method for controlling application of an error correction code (ecc) algorithm in a memory subsystem In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, ... 12/01/05 - 20050268208 - Semiconductor memory device and signal processing system A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion ... 12/01/05 - 20050268207 - Techniques for operating semiconductor devices Techniques for data storage are provided. In one aspect, a method for writing one or more magnetic memory cells comprises the following steps. Data is written to one or more of the magnetic memory cells. It is detected whether there are any errors in the data written to the one ... 11/17/05 - 20050257120 - Pipelined data relocation and improved chip architectures The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time ... 11/10/05 - 20050251728 - Method for testing a memory chip and test arrangement A test arrangement with a test memory chip and a control device is provided, which has a first and a second interface. The test arrangement is connected to a memory slot of a computer system and is connected by its second interface to a memory module. Error correction data that ... 11/03/05 - 20050246613 - Error recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed ... 11/03/05 - 20050246612 - Real-time file system repairs A file system enables the real-time correction of detected corruptions to on-disk data. An enhancement to a file system responds in real time to file system corruptions detected on a running volume, and repairs the corruptions at the point where the file system detects them. Upon detection of a corruption ... 10/13/05 - 20050229080 - Semiconductor memory device equipped with error correction circuit The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error ... 09/22/05 - 20050210362 - Recording medium with status information thereon which changes upon reformatting and apparatus and methods for forming, recording, and reproducing the recording medium A recording medium, such as a high-density and/or optical recording medium and apparatus and methods for recording to and reproducing from the recording medium, in order to initialize, reinitialize, format, and/or re-format the high-density and/or optical recording medium. ... 08/18/05 - 20050182997 - Semiconductor device with memory and method for memory test A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data ... 08/11/05 - 20050177781 - Method and apparatus for accessing memory A two-dimensional array is stored in a first storage memory. A data accessing direction of the first storage memory is in a row direction. A method for reading data in the two-dimensional array in a column direction contains reading a plurality of data sets in the array from the first ... 08/04/05 - 20050172207 - Error detection and correction scheme for a memory device Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller ... 07/21/05 - 20050160344 - Method of recording/reproducing data on storage medium A method of recording/reproducing data on a storage medium. The method includes decoding a radio frequency (RF) signal read from the storage medium into corresponding binary data; storing the binary data in an external memory connected with a host interface through which a host inputs an instruction to read data ... 07/14/05 - 20050154963 - Deinterleaving device for digital broadcast receivers having a downsized deinterleaver memory and deinterleaving method thereof Disclosed is a deinterleaving device and method for digital broadcast receivers having a downsized deinterleaver memory. The deinterleaving device includes a memory having storage space for performing the deinterleaving in a number of deinterleaving units over the K groups of input data in correspondence with an interleaving unit at a ... 07/14/05 - 20050154962 - Method and system to spin up a hard disk prior to a hard disk data exchange request Method and system to spin up a hard disk prior to a data exchange request. In one embodiment, the occurrence of a predetermined event is detected. In response, the hard disk is activated prior to a request to exchange data with the hard disk. In one embodiment, the predetermined event ... 07/14/05 - 20050154961 - Method of copy detection and protection using non-standard toc entries The invention relates to a method of copy detection of a record carrier. In one particular embodiment the table of content entries are mastered on the record carrier in a detectable non-standard way, e.g. the sequence of table of content entries is mixed or the number of repetitions is varied. ... 07/07/05 - 20050149825 - Method of recording/reproducing digital data and apparatus for same A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against ... 06/30/05 - 20050144551 - Mram having error correction code circuitry and method therefor An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or ... ### FreshPatents.com Support |