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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Data Error Correction > Forward Correction By Block Code > Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity)Error Correcting Code With Additional Error Detection Code (e.g., Cyclic Redundancy Character, Parity) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266294 - Forward error correction decoders Elements of a coding table which are error-free are found at S2. At S3, corresponding elements in an erasure information table are completed, indicating that the elements in the coding array are correct. A counter is initialised at Nmax, which is the maximum number of errors that can be corrected, ... 10/25/07 - 20070250754 - System and method of correcting video data errors The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a plurality of Internet Protocol (IP) video data packets at a generator of a video acquisition system. The method also includes calculating a first error correction code ... 10/18/07 - 20070245216 - Method and apparatus for detecting synchronization of broadcasting channel in an asynchronous mobile communication system An apparatus for detecting synchronization of a Broadcasting Channel (BCH) in an asynchronous mobile communication system. A Viterbi decoder calculates a zero state path metric and a minimum path metric through an Add-Compare-Select (ACS) process and a trace-back process while decoding a frame of a received BCH. A Cyclic Redundancy ... 10/18/07 - 20070245212 - Encoding method, transmitter, network element and communication terminal The invention relates to a transmitter comprising: means (304) for arranging information bits in an information matrix; means (304) for encoding rows of the information matrix for generating a base code matrix; means (304) for generating a parity check row for the base code matrix to obtain an extended code ... 10/18/07 - 20070245211 - Method for encoding/decoding concatenated ldgm code A decoding method in a concatenated low-density generator matrix (LDGM) code-based transmission system for detecting a signal using a parity check matrix including a systematic bit part mapped to systematic bits and a parity check part mapped to parity bits. The decoding method includes generating an outer code parity check ... 10/18/07 - 20070245210 - Quiescence for retry messages on bidirectional communications interface A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be ... 10/04/07 - 20070234179 - Method and system for providing short block length low density parity check (ldpc) codes in support of broadband satellite applications An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or ... 10/04/07 - 20070234178 - Soft information scaling for interactive decoding Methods and apparatus for scaling soft values as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for ... 10/04/07 - 20070234177 - Method and apparatus for checking pipelined parallel cyclic redundancy A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is ... 09/27/07 - 20070226588 - Memory device and bit error detection method thereof A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data ... 09/27/07 - 20070226587 - Apparatus and method for receiving signal in communication system Provided are an apparatus and a method for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a Low Density Parity Check (LDPC) decoding scheme in which the sequence of check node operations is scheduled, thereby improving the decoding performance of the ... 09/27/07 - 20070226586 - Apparatus and method for receiving signal in a communication system An apparatus and method is provided for receiving a signal in a communication system. The signal reception apparatus includes a receiver for receiving a signal, and a decoder for decoding the received signal according to a Low Density' Parity Check (LDPC) decoding scheme. The LDPC decoding scheme includes check node ... 09/27/07 - 20070226585 - Apparatus and method for receiving signal in communication system Disclosed is an apparatus for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme, in which elements of a Galois field are expressed by an exponent representation, thereby minimizing the memory capacity required ... 09/27/07 - 20070226584 - Apparatus and method for transmitting/receiving signal in a communication system A signal transmission/reception apparatus of a communication system. The signal transmission apparatus receives an information vector, encodes the information vector into a structured Low Density Parity Check (LDPC) codeword using a structured LDPC coding scheme, and transmits the generated structured LDPC code to the signal reception apparatus. Then the signal ... 09/27/07 - 20070226583 - Apparatus and method for transmitting/receiving signal in a communication system In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus ... 09/27/07 - 20070226582 - Systems and methods for achieving higher coding rate using parity interleaving The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity ... 09/27/07 - 20070226580 - Validating data using processor instructions In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy ... 09/27/07 - 20070226579 - Memory replay mechanism Embodiments of the invention are generally directed to systems, methods, and apparatuses for memory replay mechanisms. In some embodiments, the replay logic includes reset logic to reset at least some of the links in a point-to-point memory interconnect. In addition, the replay logic may include a replay queue to store ... 09/20/07 - 20070220399 - Low density parity check code-based hybrid automatic repeat request method A transmission method based on a Hybrid Automatic Repeat Request (HARQ) scheme for in a communication system. A codeword is generated using a Low Density Parity Check (LDPC) code. Parity bits of the codeword are classified on a basis of a transmission priority. Parity bits with an identical transmission priority ... 09/20/07 - 20070220398 - Ldpc decoding apparatus and method based on node memory An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs ... 09/20/07 - 20070220397 - Method for transmitting/receiving signals in a communications system and an apparatus therefor A method for transmitting a signal in a signal transmission apparatus of a communications system including receiving an information vector, and encoding the information vector according to a zigzag B-LDPC encoding scheme to generate a zigzag B-LDPC codeword, thereby advantageously reducing the encoding complexity together with enhanced error correction capability. ... 09/20/07 - 20070220396 - Error correction code striping A method is disclosed which decreases the amount of error correction code data required to detect and correct errors in digital data while still maintaining a specified ability to correct errors in large groups of contiguous data. The present invention accomplishes this by placing distance either in space or in ... 09/20/07 - 20070220395 - Method and apparatus for encoding and decoding data A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part ... 08/30/07 - 20070204198 - Apparatus and method for transmitting/receiving signal in communication system Disclosed is an apparatus and a method for transmitting/receiving a signal in a communication system, which generates an Affine Permutation Matrix-Low Density Parity Check (APM-LDPC) codeword by encoding an information vector in an APM-LDPC encoding scheme which is a preset structured LDPC encoding scheme, and detects the information vector by ... 08/30/07 - 20070204197 - Decoding device, control method, and program A decoding device for decoding LDPC (Low Density Parity Check) codes includes a message calculation unit for performing a variable node calculation for decoding the LPDC codes using a message to be supplied, or performing a check node calculation, and outputting the message to be obtained as a result of ... 08/23/07 - 20070198890 - Method for creating an error correction coding scheme The present invention relates to a method for reducing data loss comprising a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a ... 08/23/07 - 20070198889 - Method and system for repairing partially damaged blocks A method for reconstructing a logical block, wherein the logical block comprises a first set of sectors. The method including obtaining a copy of the logical block comprising a second set of sectors, determining which of the sectors in the first set of sectors are identical to sectors in the ... 08/09/07 - 20070186140 - Parity check matrix generation method, data transmission system, encoding device, decoding device, and a parity check matrix generation program A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 ... 08/09/07 - 20070186139 - Interleaving method for low density parity check encoding An interleaving method for use in a low density parity check (LDPC) encoding process employed by a network across which data is transmitted and/or in a recording/reproducing apparatus when information is stored on a recording medium. The method includes generating more than one code word vector by generating parity information ... 07/19/07 - 20070168835 - Serial communications system and method A communications system and method are disclosed. A transmitter includes a scrambler for scrambling original data, an ECC encoder for converting scrambled data into ECC data, and a serializer for converting the ECC data into a serial stream. A receiver includes a frame recoverer for converting the serial data into ... 07/19/07 - 20070168834 - Method and system for routing in low density parity check (ldpc) decoders An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within ... 07/19/07 - 20070168833 - Apparatus and method for receiving signal in a communication system using a low density parity check code An apparatus and a method for receiving a signal in a communication system using a Low Density Parity Check (LDPC) code. The apparatus and the method includes decoding a received signal according to a hybrid decoding scheme, wherein the hybrid decoding scheme is generated by combining two of a first ... 07/19/07 - 20070168832 - Memory efficient ldpc decoding methods and apparatus Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to ... 07/12/07 - 20070162824 - Error detection and correction scheme for a memory device Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller ... 07/12/07 - 20070162823 - System and method for optimizing iterative circuit for cyclic redundency check (crc) calculation A system for generating CRC code words associated with data ranging up to w-bytes in width to be communicated over a communications channel includes a first plurality of serially coupled code-generation blocks each for generating a CRC value based on data input to each block, respective blocks of the first ... 07/12/07 - 20070162822 - Apparatus and method for transmitting/receiving signal supporting variable coding rate in a communication system Provided are an apparatus and method for transmtting/receiving signal, supporting a variable coding rate, in a communication system. The method includes receiving an information vector, generating a child parity check matrix based on a parent parity check matrix according to a coding rate to be applied for generating a block ... 07/12/07 - 20070162820 - Checksum generation apparatus and method thereof A checksum generation apparatus and method thereof. The checksum generation apparatus includes a control unit which, in response to information on a predetermined length, outputs a control signal when an amount of data corresponding to the predetermined length is received; an addition unit which receives data, performs an addition on ... 07/12/07 - 20070162819 - Signal transmitting method and transmitter in radio multiplex transmission system A disclosed signal transmission method in a radio multiplex transmission system comprises the steps of: serial-to-parallel converting serial data to be transmitted into N (N: two or more) parallel data series; independently performing an error-correcting encoding process on the parallel signals of the N data series serial-to-parallel converted; parallel-to-serial converting ... 06/28/07 - 20070150789 - Ldpc decoding apparatus and method using type-classified index Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing ... 06/14/07 - 20070136638 - System and method for checking and correcting bios errors A system for checking and correcting BIOS errors is provided. The system includes a program loading module (1001) for loading main programs from a BIOS ROM into a RAM; a checksum calculating module (1002) for reading the original checksum, and for calculating a new checksum for the main programs loaded ... 06/14/07 - 20070136637 - Device and method for correcting a data error in communication path There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an ... 06/07/07 - 20070130495 - Apparatus and method of multi-cyclic redundancy checking for section detection and reliability information acquisition in a dvb-h system A method and apparatus of multi-Cyclic Redundancy Checking (CRC) are provided for section detection and reliability information acquisition in a Digital Video Broadcasting-Handheld (DVB-H) system. A Packet Identifier (PID) filtering process is performed for a packet received through a radio network. A transport stream packet including section data is detected. ... 05/31/07 - 20070124646 - Recording medium, recording method and apparatus, reproducing method and apparatus, data transmitting method, and data decrypting method A recording medium having an area in which data that has been encoded with a first error correction code is recorded, wherein data that can be decoded with a second error correction code that is different from the first error correction code is recorded to the area along with the ... 05/31/07 - 20070124645 - Data transmission method Encrypted auxiliary information data DYAE/DCAE including no inhibited codes is generated based on auxiliary information data DYA/DCA including no inhibited codes, in an auxiliary data packet having an auxiliary data flag ADF formed of a first combination of a plurality of inhibited codes, the auxiliary data flag ADF is replaced ... 05/17/07 - 20070113148 - Decoding apparatus and method in a communication system using low density parity check codes A decoding method in a communication system using a Low Density Parity Check (LDPC) code. The method includes determining whether an LDPC codeword to be decoded is a general LDPC codeword to which a puncturing scheme is not applied or a punctured LDPC codeword to which the puncturing scheme is ... 05/17/07 - 20070113147 - Apparatus and method for transmitting/receiving a signal in a communication system using a low density parity check code An apparatus and method are provided for transmitting a signal in a communication system using a low density parity check (LDPC) code. An LDPC codeword is generated by encoding an information word at a coding rate. A puncturing pattern is generated when a hybrid automatic repeat request (HARQ) scheme to ... 05/17/07 - 20070113146 - System and method for low-density parity check (ldpc) code design Disclosed is a density evolution algorithm based on a refined definition of node and edge densities for different parts of the code. In particular, density functions ƒV(1)(i) and ƒV(2)(i) of the output edges of the variable nodes with degree i within different codeword regions w1 and we, respectively, are defined ... 05/03/07 - 20070101235 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the ... 05/03/07 - 20070101234 - Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number ... 05/03/07 - 20070101233 - System, method and computer program product for implementing rate 3/4 low density parity check code A method, system, apparatus and computer program product for correcting errors in a signal transmission using a rate 3/4 low density parity check (LDPC) code. At least a portion of a received data message is encoded by using a parity check matrix of the LDPC code. The encoded data message ... 04/26/07 - 20070094568 - Method for updating check node in low density parity check decoder A method is provided for updating a check node in a low density parity check (LDPC) decoder, including: transmitting log-likelihood ratio (LLR) messages from variable nodes to a plurality of check nodes; decomposing the LLR messages in a plurality of node messages for each check node; and updating each check ... 04/19/07 - 20070089028 - Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, ... 04/19/07 - 20070089027 - Apparatus and method for transmitting/receiving signal in a communication system using low density parity check code An apparatus is provided for transmitting a signal in a communication system using a Low Density Parity Check (LDPC) code. A controller determines a number of ‘0’s to be inserted in information data according to a first coding rate to be applied when generating the information data into an LDPC ... 04/19/07 - 20070089026 - Coding circuit and coding apparatus Disclosed is a coding circuit including: a holding unit to hold a first signal, and to output the held first signal as a fourth signal in synchronization with an input of a second signal and a third signal which respectively comprise one of two data produced by splitting a data ... 04/19/07 - 20070089025 - Apparatus and method for encoding/decoding block low density parity check codes having variable coding rate A method for encoding a rate-compatible block Low Density Parity Check (LDPC) code. The method includes designing specific LDPC codes for a predetermined number of coding rates, and generating a pruning pattern by comparing information node degrees of the predetermined number of LDPC codes; matching check node degrees of the ... 04/19/07 - 20070089024 - Method and apparatus for a low-density parity-check decoder A low-density parity-check (LDPC) decoder (304) has a memory (308), and a processor (306). The processor is programmed to initialize (202) the LDPC decoder, calculate (204) a probability for each check node, calculate (206) a probability for each bit node, calculate soft decisions, update the bit nodes according to the ... 04/19/07 - 20070089023 - System and method for system resource access The disclosure is directed to a controller including a memory interface to a memory device, a device driver configured to access the memory device via the memory interface, and a resource loader to provide a memory location of a resource to the device driver. The device driver is configured to ... 04/05/07 - 20070079213 - Wireless communications apparatus Wireless transmission of data is effected across a communications channel defined by a communications medium by means of an encoder, operable to apply a low density parity check (LDPC) code to data for transmission. The LDPC code is irregular with respect to the degree of variable nodes, and so the ... 04/05/07 - 20070079212 - Techniques for efficient error correction code implementation in a system A memory system with folding error correction. The memory comprises a first memory bank and a second memory bank. A means for generating error correction code for data to be written to said memory system is provided. A means for writing said received data to a location in said first ... 04/05/07 - 20070079211 - Cyclic redundancy check circuit and communication system having the same for multi-channel communication A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in ... 04/05/07 - 20070079210 - Method and system for handling stuck bits in cache directories A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the directory ... 04/05/07 - 20070079209 - Method of detecting occurrence of error event in data and apparatus for the same A method of detecting an occurrence of an error event in data and an apparatus for the same are provided. The method includes: preparing an error detection code wherein syndrome sequences for dominant error events are all different; generating a codeword from source data using the error detection code; detecting ... 03/22/07 - 20070067697 - Method and controller for processing data multiplication in raid system The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 32 bits or 64 bits). One or several XOR ... 03/22/07 - 20070067696 - System, transmitter, receiver, method, and computer program product for structured interleaved zigzag coding A system, transmitter, receiver, method, and computer program product are provided in which a plurality of structured interleavers permute data bits arranged in a data bit matrix for Zigzag encoding. For each interleaver, the data bits in each column of the data bit matrix are cyclically shifted, with the amount ... 03/15/07 - 20070061680 - Coding system and decoding system In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string ... 03/15/07 - 20070061679 - Coding system and decoding system In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string ... 03/15/07 - 20070061678 - Coding system and decoding system In a coding system where in an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code ... 03/15/07 - 20070061677 - Coding system and decoding system In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string ... 03/15/07 - 20070061676 - Coding system and decoding system In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed-code string 201 ... 03/15/07 - 20070061675 - Method, system, and apparatus for adjacent-symbol error correction and detection code A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases. ... 03/15/07 - 20070061674 - Transmission data packet construction for better header authentication The invention relates to a packet format for data being transmitted in a packet switched network. The packet as constructed in accordance with the invention enables the detection of data tampering and alteration of the data payload part as well as header part. The invention uses check code and encryption ... 03/15/07 - 20070061673 - Wireless communication method and apparatus for decoding enhanced dedicated channel absolute grant channel transmissions A wireless communication method and apparatus for decoding enhanced dedicated channel (E-DCH) absolute grant channel (E-AGCH) transmissions are disclosed. A wireless transmit/receive unit (WTRU) receives E-AGCH data which includes a cyclic redundancy check (CRC) part and a data part. The CRC part is masked with a WTRU identity (ID) at ... 03/15/07 - 20070061672 - Non-volatile memory with error detection Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair ... 03/15/07 - 20070061671 - Data memory system and method for transferring data into a data memory A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data ... 03/15/07 - 20070061670 - Digital data transmission error checking method and system A digital data transmission error checking method and system is proposed, which is designed for use with a data source unit and a data reception unit for providing a error checking function, and which is characterized by the use of an improved checksum algorithm that initially sets a checksum variable ... 03/15/07 - 20070061669 - Method, device and system for detecting error correction defects A method, device and system for detecting error correction defects calculates a written error checking and correction (ECC) code for a written data and writes the written data and the written ECC code into a plurality of memory cells. When data is read from the memory cells including data representing ... 03/15/07 - 20070061668 - Data corruption scrubbing for content addressable memory and ternary content addressable memory A method for remedying data corruption in a first circuit, which may be a CAM or a TCAM. The method includes providing a RAM circuit external to the first circuit, the RAM circuit being configured for storing error detection information for data stored in the first circuit. The method also ... 02/22/07 - 20070044002 - Offload system, method, and computer program product for performing cyclical redundancy check (crc)-related calculations An offload system, method, and computer program product are provided for utilizing a hardware network interface for identifying data and calculating at least a portion of a cyclical redundancy check (CRC) value for the data. ... 02/22/07 - 20070044001 - Single stage implementation of min*, max*, min and/or max to perform state metric calculation in siso decoder Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently, ... 02/22/07 - 20070044000 - Variable modulation with ldpc (low density parity check) coding Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an ... 02/22/07 - 20070043999 - Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order ... 02/22/07 - 20070043998 - Systems and methods for a turbo low-density parity-check decoder A method for forming a plurality of parity check matrices for a plurality of data rates for use in a Low-Density Parity-Check (LDPC) decoder, comprises establishing a first companion exponent matrix corresponding to a first parity check matrix for a first data rate, and partitioning the first parity check matrix ... 02/22/07 - 20070043997 - Reduced complexity error correction encoding techniques An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code ... 02/15/07 - 20070038918 - Data backup method and memory device In first and second areas 10 and 20 in an EEPROM 30, data storing areas 11 and 21 and checksum areas 12 and 22 are respectively provided. The highest bit of checksum data stored in each of the checksum areas 12 and 22 is used as the bit based on ... 02/15/07 - 20070038917 - Serial data communication - can memory error detection methods A method is provided for formatting a message, with a first plurality of bits forming a data component, and a second plurality of bits forming a reserved component, for transmission in a vehicle. The method comprises the steps of calculating an initial checksum from the data component, calculating a revised ... 02/15/07 - 20070038916 - Method of coding data A method of coding data for transmission in a communication medium or channel. A codeword is generated from a mother code parity check matrix and a macro matrix. The mother code parity check matrix includes sub-matrices that are m-by-m square matrices with cyclic structure, and the macro matrix includes elements ... 02/15/07 - 20070038915 - Adaptive archival format Data are stored on a random-access storage medium. A user set of data is received. The user set of data is mapped to multiple frames. For each frame, error-correction bytes are generated over the data mapped to that frame. In addition, the data mapped to that frame are written to ... 02/15/07 - 20070038914 - Method and apparatus for block and rate independent decoding of ldpc codes Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having ... 02/15/07 - 20070038913 - Method and apparatus for the reliability of host data stored on fibre channel attached storage subsystems A method for improving the reliability of host data stored on Fibre Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists ... 02/08/07 - 20070033486 - Channel interleaving/deinterleaving apparatus in a communication system using low density parity check code and control method thereof A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a ... 02/08/07 - 20070033485 - Low-complexity hybrid ldpc code encoder Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G ... 02/08/07 - 20070033484 - System and method for designing rs-based ldpc code decoder A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit ... 02/08/07 - 20070033483 - Method of generating quasi-cyclic low density parity check codes and an apparatus thereof Disclosed is a method and apparatus for completely recovering received data with high reliability using LDPC codes without short-sized cycles in a digital communication system using an error-correcting code. The method includes performing exponent conversion of a predetermined number of exponent matrixes stored in advance in a memory so as ... 02/08/07 - 20070033482 - Decoder device and decoding method and program A device and a method that improve decoding characteristics of an LDPC decoder to which SPA where the equation for the computation of messages is approximated and the number of messages are reduced is applied. A received LDPC code is decoded by repeating the passing of messages between a plurality ... 02/08/07 - 20070033481 - Decoding device and decoding method and program To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the ... 02/08/07 - 20070033480 - Efficient construction of ldpc (low density parity check) codes with corresponding parity check matrix having csi (cyclic shifted identity) sub-matrices Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero ... 02/08/07 - 20070033479 - Apparatus, method and computer program for correction of multiple bit errors The present invention relates to an apparatus and method for monitoring and correcting data errors in a computer system, in particular transient data errors in computer systems having very limited tolerance for deteriorations in performance. The method comprises the steps of: writing a set of data to a plurality of ... 02/08/07 - 20070033478 - System and method for blind transport format detection with cyclic redundancy check A method for BTFD decoding of signals having at least a message block of k-bit from a length candidate set S={s1, s2, . . . si}, wherein the k message bits are encoded by a CRC encoder and processed by an (n, l, m) convolutional encoder to generate encoded data ... 01/11/07 - 20070011572 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks. ... 01/11/07 - 20070011571 - Iterative method of decoding a received signal An iterative method and a device (20) for decoding received signals (21) transmitted in data frames via various channels (A, B). In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel (A; ... 01/11/07 - 20070011570 - Apparatus and method for transmitting/receiving data in a communication system using structured low density parity check code Provided is an apparatus and method for transmitting/receiving data in a communication system using a structured Low Density Parity Check (LDPC) code. The transmitter performs structured LDPC coding on input information data using a structured LDPC code, parallel-converts a structured LDPC codeword generated by performing the structured LDPC coding, in ... 01/11/07 - 20070011569 - Variable-rate low-density parity check codes with constant blocklength Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix. ... 01/11/07 - 20070011568 - hardware-efficient low density parity check code for digital communications A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). ... 01/11/07 - 20070011567 - Method for padding and puncturing low density parity check code Disclosed is a method for puncturing a Low Density Parity Check (LDPC) code that is expressed by a factor graph having a check node and a variable node, connected to each other by an edge, and is decoded by a parity check matrix including a parity part having a single ... 01/11/07 - 20070011566 - Clash-free irregular-repeat-accumulate code Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix ... 01/11/07 - 20070011565 - Method and apparatus for low-density parity check encoding A method of improving the error correcting performance using low-density parity check (LDPC) encoding includes, making an LDPC matrix by arranging non-zero matrices in a series of blockwise columns not to overlap with one another, making at least one LDPC codeword block by generating parity information based on the LDPC ... 01/11/07 - 20070011564 - Multi-channel ldpc decoder architecture A multi-channel decoder system has a decoder core, at least a portion of which comprises or is configurable as a LDPC decoder, a plurality of channels to and from the decoder core, and control logic for controlling application of the decoder core to data carried by one or more of ... 01/11/07 - 20070011563 - Shared redundancy in error correcting code A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundancy symbols. Shared redundancy symbols are generated for the cooperative ... 01/11/07 - 20070011562 - Mitigating silent data corruption in a buffered memory module architecture Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The ... 01/11/07 - 20070011561 - Method and apparatus for data transfer A data management layer of a layered protocol system and a method of transmitting data. The data management layer including: a cyclic redundancy check generator connected to a retry buffer through a multiplexer; a sequence number generator connected to the retry buffer through the multiplexer; means for generating a sequence ... 01/11/07 - 20070011560 - Method and system for performing fast checksum operations in a gprs communication system utilising tunnelling Methods have been provided for accomplishing fast checksum operations for various nodes in a GPRS network. According to one embodiment of the invention a method is provided for performing tunnelling wherein, a first packet (J) is received having a stored first checksum value (HC J) covering at least portions of ... 12/28/06 - 20060294448 - Apparatus and method for using an error correcting code to achieve data compression in a data communication network Data compression in a communication system is achieved by performing an error correction encoding operation on input data, and then providing, for transmission across a communication channel, compressed data that is representative of the input data and includes error correction information produced by the error correction encoding operation. ... 12/14/06 - 20060282746 - Method and apparatus for accessing data stored on an optical disc The present invention provides an apparatus for accessing data stored on an optical disc. The apparatus includes a PI decoding module, a storage unit, and a PO decoding module. The PI decoding module is utilized for PI decoding and correcting the digital data read from the optical disc to generate ... 12/14/06 - 20060282745 - Soft error protection in individual memory devices Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of ... 12/14/06 - 20060282744 - Technique for performing cyclic redundancy code error detection A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include a technique to perform cyclic redundancy code (CRC) generation. ... 12/14/06 - 20060282743 - Instructions for performing modulo-2 multiplication and bit reflection A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include an instruction to perform carry-less multiplication and an instruction to perform a bit reflection operation. ... 12/14/06 - 20060282742 - 2d-normalized min-sum decoding for ecc codes A method for decoding error-correcting codes normalizes messages generated by a bit node processor, and normalizes messages generated by the check node processor. ... 12/14/06 - 20060282741 - Method to secure an electronic assembly executing any algorithm against attacks by error introduction The invention concerns an automatic method to secure an electronic calculation assembly against attacks by error introduction or by radiation. The following are used: 1) Static information generated by the automatic process; 2) A dynamic part of the memory of the electronic system allocated by the automatic process; 3) Beacons ... 11/16/06 - 20060259847 - Data storing method for a non-volatile memory cell array having an error correction code An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A ... 11/09/06 - 20060253768 - Techniques to speculatively determine network protocol unit integrity Techniques to speculate boundaries of content of payload of a network protocol unit and to perform cyclical redundancy checking (CRC) on the content. The CRC validation on the content can be performed in a computing logic such as a network interface. The network protocol unit may be made available to ... 11/02/06 - 20060248433 - Disk controller architecture to allow on-the-fly error correction and write disruption detection Error correction in a disk drive is performed by error correction circuitry which accepts data read from a data storage medium. The error correction circuitry performs both block error correction in a first data domain and sector error correction in a second data domain. A sector FIFO buffer is used ... 11/02/06 - 20060248432 - Method and apparatus for implementing processor bus speculative data completion A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting ... 10/26/06 - 20060242536 - Decoding device and decoding method The present invention provides a decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device include: a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse ... 10/26/06 - 20060242535 - Detection of errors in the communication of data The invention relates to a method and a system for detecting errors in the communication of data from a transmitter to at least one receiver. In the method, in a first step on the side of the transmitter a first check value is generated at least from user data to ... 10/26/06 - 20060242534 - Low density parity check (ldpc) code Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown. ... 10/26/06 - 20060242533 - Method for updating check-node of low-density parity-check (ldpc) codes decoder and device using the same The invention provides a method for updating check-node of low-density parity-check (LDPC) codes decoder. The method comprises the following steps: First of all, sort all data that are input into the check-node of LDPC codes decoder to find a minimum absolute value and a second minimum absolute value. Secondly, compare ... 10/26/06 - 20060242532 - Techniques to provide information validation and transfer Techniques to issue a single application programming interface (API) to request both data copy and CRC validation operations. In some embodiments, a receiver of the API may observe which logic (e.g., software or hardware and/or combinations of software and hardware) is available to execute instructions for data copy and CRC ... 10/19/06 - 20060236202 - Method of detecting two-dimensional codes A method is described of detecting two-dimensional codes, in particular matrix codes, which include a plurality light and dark data bits arranged two dimensionally, in particular in matrix form. In the method, the code is detected as a gray scale value image; the detected gray scale value image is split ... 10/19/06 - 20060236201 - High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a ... 10/19/06 - 20060236200 - Image processor An image processor includes a JPEG 2000 codec. The JPEG 2000 codec generates a plurality of levels of encoded data, and a checksum circuit integrates the encoded data for each of the levels to determine a checksum. The determined checksum is written together with the encoded data into a header ... 10/19/06 - 20060236199 - Apparatuses and methods for checking integrity of transmission data A generator may include a monitoring unit, an engine unit and/or a register. The monitoring unit may selectively extract at least a portion of data to be transmitted to, or received from, an external communication device. The engine unit may generate an error check code using a polynomial expression or ... 10/19/06 - 20060236198 - Storage system with automatic redundant code component failure detection, notification, and repair A RAID system includes a non-volatile memory storing a first program and first and second copies of a second program, and a processor executing the first program. The first program detects the first copy of the second program is failed and repairs the failed first copy in the non-volatile memory ... 10/19/06 - 20060236197 - Transmission method combining trellis coded modulation and low-density parity check code and architecture thereof The present invention discloses a method combining Trellis Coded Modulation (TCM) and Low-Density Parity Check (LDPC) code and the architecture thereof, which incorporates TCM with LDPC code having better error-correction capability to promote transmission quality and to define TCM of different transmission rates. Further, TCM can utilize less number of ... 10/19/06 - 20060236196 - Combined command and data code An apparatus includes a source for a command and an associated data. An error code generator generates an error code for the combined command and associated data, which is distributed among the command and the associated data. A transmitter then transmits the command and the associated data separately. ... 10/19/06 - 20060236195 - Efficient check node message transform approximation for ldpc decoder In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp ... 09/28/06 - 20060218466 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks. ... 09/28/06 - 20060218465 - Low density parity check (ldpc) code decoder using min*, min**, max* or max** and their respective inverses Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are ... 09/28/06 - 20060218464 - Optical information recording medium and data recording apparatus thereon An optical information recording medium, a data recording apparatus, a data recording method used by the recording apparatus, and a data reproducing apparatus are provided, in which the optical information recording medium includes data provided in one or more recording blocks. A recording block of the optical information recording medium ... 09/28/06 - 20060218463 - Coding apparatus and decoding apparatus for transmission/storage of information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code ... 09/28/06 - 20060218462 - Coding apparatus and decoding apparatus for transmission/storage of information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check-bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion ... 09/28/06 - 20060218461 - Channel interleaving/de-interleaving apparatus in a communication system using a low density parity check code and control method thereof In a communication system, information data bits are encoded in a preset coding scheme when the information data bits are input, and a Low Density Parity Check (LDPC) codeword is generated. The LDPC codeword is interleaved according to a preset channel-interleaving rule. A channel-interleaved LDPC codeword is modulated in a ... 09/21/06 - 20060212775 - System and method for tolerating communication lane failures A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of ... 09/14/06 - 20060206782 - Data recording method, recording medium and reproduction apparatus A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, and second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability. The second error correcting codes have a ... 09/14/06 - 20060206781 - Method for puncturing low density parity check code A method is provided for puncturing a low density parity check (LDPC) code decoded by a parity check matrix that is expressed by a factor graph including a check node and a bit node, being connected to each other at an edge, and includes a parity part having a dual ... 09/14/06 - 20060206780 - Scrambler circuit, encoding device, encoding method and recording apparatus An encoding device includes a buffer for performing EDC generation, scrambling and ECC generation on user data arranged along user data direction Q that is read out from a data buffer of SDRAM and storing the operation results, a substitution buffer for repeatedly reading out the user data by burst ... 09/14/06 - 20060206779 - Method and device for decoding dvb-s2 ldpc encoded codewords The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable ... 09/14/06 - 20060206778 - Ldpc decoder for dvb-s2 decoding The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes ... 09/07/06 - 20060200725 - Coding apparatus and decoding apparatus for transmission/storage of information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code ... 09/07/06 - 20060200724 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning System and method for Slepian-Wolf coding using channel code partitioning. A generator matrix is partitioned to generate multiple sub-matrices corresponding respectively to multiple correlated data sources. The partitioning is in accordance with a rate allocation among the correlated data sources. Corresponding parity matrices may be generated respectively from the sub-matrices, ... 09/07/06 - 20060200723 - Method and apparatus for implementing enhanced vertical ecc storage in a dynamic random access memory A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can ... 08/31/06 - 20060195764 - Coding apparatus and decoding apparatus for transmission/storage of information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code ... 08/31/06 - 20060195763 - Coding apparatus and decoding apparatus for transmission/storage of information An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code ... 08/31/06 - 20060195762 - Hs-dsch transmitter and crc calculator therefor in a w-cdma system An HS-DSCH transmitter in a W-CDMA system is provided. In the HS-DSCH transmitter, a memory stores input transmission data. A bit scrambling code ROM stores random sequences for bit scrambling of the input data. A CRC calculator generates a bit scrambled sequence by attaching a CRC to the input transmission ... 08/31/06 - 20060195761 - Method of generating low-density parity check matrix and method of generating parity information using the low-density parity check matrix A method of generating a parity check matrix and a method of generating parity information using the parity check matrix, wherein the method of generating a parity check matrix includes selecting elements of a low-density parity check (LDPC) matrix such that every element of a top right corner portion of ... 08/31/06 - 20060195760 - Permuting mtr code with ecc without need for second mtr code Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint. In one embodiment, a system for processing data comprises a maximum transition run or timing-varying maximum transition run (hereinafter MTR) encoder configured to ... 08/31/06 - 20060195759 - Method and apparatus for calculating checksums A method for calculating checksums includes calculating a first checksum based at least in part on a first block of data, and calculating a partial checksum based at least in part on a second block of data. The second block of data comprises a data portion followed by a fill ... 08/31/06 - 20060195758 - Method of storing information on an optical disc A method is described for writing information to a record medium (2). 152 code words [11(j)] each having 248 bytes [mI(ij)] and 12 BIS words each having 62 BIS bytes [b2(r,s)] are combined to form an ECC block (M3) having 38 440 elements [m3(v,w)], which elements are consecutively written. Also, ... 08/24/06 - 20060190801 - Apparatus and method for generating low density parity check code using zigzag code in a communication system A method for generating a low-density parity check (LDPC) code supporting various code rates. The method includes finding a plurality of parity check matrixes showing the best performance at a predetermined code rate; matching the parity check matrixes in terms of the number of ‘1’s per row in units of ... 08/24/06 - 20060190800 - Copy protected dvd disc and method for producing and validating same A copy protected DVD disc and a method for producing a signature on the disc is provided. In an embodiment of the invention, the method for protecting a DVD disc includes producing a signature on the disc by non-destructively altering the content of at least one sector in the data ... 08/24/06 - 20060190799 - Decoding apparatus and method and program A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding ... 08/24/06 - 20060190798 - Verifier for remotely verifying integrity of memory and method thereof A verifier for remotely checking integrity of a device connected via a network, includes a calculator which fills free areas in a memory of the device with random numbers and generates a local check code; an interface which transmits integrity check parameters that are used by the device to generate ... 08/24/06 - 20060190797 - Low complexity decoding of low density parity check codes An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a ... 08/17/06 - 20060184857 - Data recording method, recording medium and reproduction apparatus A recording medium is provided for storing a data stream containing first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability, and the second error correcting codes have a ... 08/17/06 - 20060184856 - Memory circuit A memory circuit includes a data storage section for storing a plurality of data sets and a plurality of redundant data sets, which are used for error correction for the data sets; and an error correction section for performing at least error detection for the data sets in the data ... 08/10/06 - 20060179396 - Redundancy in signal distribution trees A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the ... 08/10/06 - 20060179395 - Method and circuit arrangement for verifying a data record having a plurality of data words A method for verifying a data record having a plurality of data words, the method including the steps of providing an encrypted data record having a plurality of encrypted data words and an error codeword assigned to the data record. After the decryption of the encrypted data words, it is ... 08/10/06 - 20060179394 - Method and apparatus for collecting failure information on error correction code (ecc) protected data Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The ... 08/10/06 - 20060179393 - Device and method for creating a signature A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cycle, a signature being formed ... 08/03/06 - 20060174179 - Erasure detection for a transport channel with an unknown format To perform erasure detection for an intermittently active transport channel with unknown format, a receiver determines an energy metric and a symbol error rate (SER) for a received block with CRC failure. The receiver computes uncorrelated random variables u and v for the received block based on the energy metric ... 07/27/06 - 20060168496 - Systems and methods for implementing cyclic redundancy checks The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. ... 07/27/06 - 20060168495 - Computation of cyclic redundancy check In one aspect, a method and apparatus for advancing a state of a cyclic redundancy check (CRC) computation on a transmitted message via a look-up table (LUT) storing a plurality of entries associated with possible states of the CRC computation is provided. A plurality of indexes is computed based on ... 07/27/06 - 20060168494 - Error protecting groups of data words Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for use in protecting groups of data words. One embodiment manipulates these data words to generate a resultant data word and an error correction code thereon for use in identifying a position of a bit error, with error ... 07/20/06 - 20060161832 - System and method for generating a cyclic redundancy check A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3rd to Nth order CRC polynomial key word, wherein N is an integer ... 07/20/06 - 20060161831 - Lowering voltage for cache memory operation Setting a minimum operating voltage (Vcc min) of the cache to a voltage value at which the number of cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining cells continue to function correctly at the ... 07/20/06 - 20060161830 - Combined-replica group-shuffled iterative decoding for error-correcting codes A method generates a combined-replica group-shuffled iterative decoder, comprising. First. an error-correcting code and an iterative decoder for an error-correcting code is received by the method. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica ... 07/13/06 - 20060156186 - Intercommunicating apparatus for duplex system capable of detecting failure thereof A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A ... 07/13/06 - 20060156185 - Error correction coding across multiple channels in content distribution systems Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of ... 07/13/06 - 20060156184 - Method and apparatus for transmitting and receiving data with high reliability in a mobile communication system supporting packet data transmission A method and apparatus for transmitting control information of a small block size with high reliability in a mobile communication system supporting uplink packet data service are provided. A 6-bit Absolute Grant indicating an allowed maximum data rate for uplink packet data transmission is generated and a 16-bit User Equipment ... 07/13/06 - 20060156183 - Method and apparatus for generating a low-density parity check code A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N−K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is ... 07/13/06 - 20060156182 - Parity bit system for a cam A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status portion has an independent status parity bit. The status parity bit is recalculated and updated whenever a status bit in the ... 07/13/06 - 20060156181 - Method for puncturing an ldpc channel code A method for puncturing a low density parity check (LDPC) code that is decoded through a parity check matrix expressed by a factor graph including check nodes and bit nodes connected to the check nodes through edges. The method includes classifying the bit nodes mapped to a parity part of ... 07/13/06 - 20060156180 - Device and method for determining a defective area on an optical media A device and method for determining a defective area on an optical media (disc) by counting the number of errors within ECC blocks of the data stored thereon. The defect detection is generally performed by Error Counters and Comparator circuits, for counting the number of occurrences of errors (e.g., parity ... 07/13/06 - 20060156179 - Construction of ldpc (low density parity check) codes using grs (generalized reed-solomon) code Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices ... 07/13/06 - 20060156178 - Data error control Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one ... 07/13/06 - 20060156177 - Method and apparatus for recovering from soft errors in register files An apparatus and method for recovering from soft errors in register files is disclosed. In one embodiment, an apparatus includes a register file and error-correcting-code generation logic. Each register in the register file has bits to store data and bits to store an error-correcting-code value for the data. ... 07/13/06 - 20060156176 - Crc format automatic detection and setting An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC format detection and switching without requiring a user ... 07/13/06 - 20060156175 - Error detection and correction A method for error detection and correction comprising performing a first modulation error scan of said modulation symbol, marking data that fails to comply with a predetermined criteria, demodulating said modulation symbols, computing a first error syndrome using said demodulated symbols, and correcting errors using said error syndrome computation. ... 07/13/06 - 20060156174 - Method, apparatus and system to detect and signal sequential hot plug failure diagnostics In some embodiments, a method, apparatus and system to detect and signal sequential hot plug failure diagnostics are presented. In this regard, a diagnostic agent is introduced to store a plurality of bits corresponding to a hot plug error code in a register sequentially such that a plurality of hot ... 07/06/06 - 20060150061 - Apparatus and method for transmitting and receiving a signal in a communication system An apparatus and method for transmitting a signal in a communication system. An information vector is encoded using a structured low density parity check (LDPC) coding scheme supporting a first coding rate, to generate a first structured LDPC codeword vector including a first part mapped to the information vector and ... 07/06/06 - 20060150060 - Read-only record carrier with recordable area in subcode channel A method of providing a read-only record carrier on which user data can be recorded at predetermined recordable positions of subcode frames of a subcode channel after mastering of said record carrier, includes the steps of setting the subcode symbols at said predetermined recordable positions to a first predetermined symbol ... 06/08/06 - 20060123319 - Signal processing method and apparatus, signal reproducing method and apparatus, and recording medium A signal processing method multiplexes/arranges digital data of a specific unit to form a predetermined unit, adds an error correction code to the predetermined unit to constitute an error correction coded block, replaces a part of the error correction coded block with specific data, and outputs the error correction coded ... 06/08/06 - 20060123318 - Method and apparatus for decoding low density parity check code using united node processing A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for ... 06/08/06 - 20060123317 - Optical disc recording and reproducing apparatus When an ECC error correction fails in both VMGI and VMGI_BUP, when the ECC error correction failed due to damage of PI in VMGI and PI for the same portion in VMGI_BUP is intact, in a case where the ECC error correction succeeds by using PI in VMGI_BUP as PI ... 06/08/06 - 20060123316 - Method and apparatus for detecting reception error in data service of digital audio broadcast A method and apparatus are provided for detecting a reception error in a data service by inserting an error detection packet between data service data packets. A data storage medium on which an error detection packet structure is recorded for a data service of digital audio broadcast (DAB) includes at ... 06/08/06 - 20060123315 - Decoder and method for decoding low-density parity-check code When received data is decoded, a CPU stores a value “1”, which is included in a vector obtained by multiplying the received data by a parity check matrix, as the number of parity errors and also stores hard-decision result information corresponding to the number of parity errors in an output ... 06/08/06 - 20060123314 - Apparatus for coding low density parity check code and method thereof The present invention provides a coding device of a low-density parity-check (LDPC) code for simply coding information data without generating a code generator matrix. The coding device forms a parity-check matrix having two sub-matrixes. At this time, the first sub-matrix is a random matrix or a structural matrix. The second ... 06/08/06 - 20060123313 - System and method for securely adding redundancy to an electronic message A system for adding a redundancy check to an electronic message to discourage tampering and facilitate identification of altered messages provides a communication device for composing message content, a messaging module with a formatting and encoding layer for encoding the message content with header information in a series of message ... 06/08/06 - 20060123312 - Method and system for increasing parallelism of disk accesses when restoring data in a disk array system In a disk array environment such as a RAID-6 environment, the overall performance overhead associated with exposed mode operations such as resynchronization, rebuild and exposed mode read operations is reduced through increased parallelism. By selecting only subsets of the possible disks required to solve a parity stripe equation for a ... 06/08/06 - 20060123311 - Crc-based error correction An ordered list of CRC syndromes, corresponding to s |