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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Data Error Correction > Forward Correction By Block Code Forward Correction By Block CodeForward Correction By Block Code patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070260957 - Encoded transmission Significant improvement in Raptor codes and punctured LDPC codes are obtainable by use of the invention. In both a transmission scheme for Raptor-encoded or LDPC-encoded information, a dynamic adjustment approach is employed. A fraction of a codeword or information frame is transmitted. A feedback signal is sent from the receiver ... 11/01/07 - 20070255996 - Information recording/reproducing apparatus, and information recording medium In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. ... 11/01/07 - 20070255995 - Information recording/reproducing apparatus, and information recording medium In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively. ... 10/25/07 - 20070250752 - Transmitter for transmitting information data and receiver for receiving information data A transmitter for transmitting information data present in a plurality of data sets comprises an assigner for assigning offset information to one or more data sets of the plurality of data sets, the offset information indicating where the data set is to be written in a memory of a receiver. ... 10/18/07 - 20070245206 - Method for transmitting a radio navigation signal The invention relates to a method of transmitting a radionavigation signal which comprises coded and interleaved data; the signal comprises a pathway modulated by the coded and interleaved data and another pathway not modulated by these data, and the pathway not modulated by these data comprises a known code Cp ... 10/04/07 - 20070234175 - Methods and apparatus for interleaving in a block-coherent communication system Methods and apparatus for communication over a block-coherent communication system are described. The present invention is directed to methods of interleaving coded bits that are encoded by codes, e.g., LDPC codes, having graph structures largely comprised, e.g., of multiple identical copies of a much smaller graph. ... 10/04/07 - 20070234174 - Method and device for error handling in the transmission of data via a communications system A method and a device for error handling in the transmission of coded data in the form of at least one data word via a communications system, for the at least one data word a code data word being selected according to a specifiable coding rule, the data being represented ... 10/04/07 - 20070234173 - Byte level protection in pci-express devices Method and system for protecting data in a PCI-Express device is provided. The method includes adding error correction code (ECC) to every byte of data that enters a PCI-Express Transaction Handler (“PTH”) Module and is destined for a host system memory or destined to another device, before the data is ... 10/04/07 - 20070234172 - Apparatus and method for transmitting and recovering encoded data streams across multiple physical medium attachments A method includes generating an encoded data block, dividing the encoded data block into a plurality of sub-blocks, and transmitting the plurality of sub-blocks over a plurality of physical medium attachments. The encoded data block may be generated using 64B/66B encoding, and the data being encoded could first be decoded ... 09/27/07 - 20070226578 - Method and apparatus for providing reduced memory low density parity check (ldpc) codes An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without ... 09/20/07 - 20070220393 - Transmitting data words There is provided a method of transmitting data words. The method includes (a) scrambling a first occurrence of a data word to produce a first scrambled data word, (b) block encoding the first scrambled data word to produce a first code word, (c) scrambling a second occurrence of the data ... 09/06/07 - 20070208986 - Message remapping and encoding Techniques for remapping messages prior to encoding to improve performance are described. L designated messages among K total messages are remapped to L remapped messages, which are associated with L codewords having larger relative distance between these codewords, where L may be much less than K. The L designated messages ... 08/23/07 - 20070198887 - Apparatus and method for applying unequal error protection during wireless video transmission Wireless transmission of high-definition video, whether essentially uncompressed or compressed, is prone to errors during reception due to the condition of the wireless link. To ensure video quality during changing link conditions it is desirable to ensure that those portions of the video that represent the more important components of ... 08/16/07 - 20070192663 - Methods and apparatus to select tornado error correction parameters Methods and apparatus to select Tornado forward error correction parameters for delivery systems are disclosed. A disclosed example system includes a transmitter station comprising a processor to select a Tornado error correction parameter based on an error correction configuration for a file and to indicate to a receiver the selected ... 08/09/07 - 20070186135 - Processor system and methodology with background error handling feature A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft ... 07/19/07 - 20070168828 - Decompressing method and device for matrices Decompressing a matrix having a plurality of redundant matrix rows by reading selected matrix rows including at least all non-redundant matrix rows of the matrix from a memory and computing remaining matrix rows of the matrix from the read matrix rows, wherein several matrix rows are computed simultaneously. The read ... 07/12/07 - 20070162816 - Method for constructing a parity check matrix of an irregular low density parity check code A method for generating a parity check matrix of a Low Density Parity Check (LDPC) code. A base matrix is generated in which elements with a value of 1 are arranged at predefined distances. The elements with the value of 1 in the base matrix are replaced with predefined sub-matrices. ... 07/12/07 - 20070162815 - System and method for providing h-arq rate compatible codes for high throughput applications In one embodiment, the present patent application comprises a method and apparatus to generate low rate protographs from high rate protographs, comprising copying a base graph; permuting end points of edges of a same type in copies of the base graph to produce a permuted graph; and pruning systematic input ... 07/12/07 - 20070162814 - Ldpc (low density parity check) code size adjustment by shortening and puncturing LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original ... 07/05/07 - 20070157062 - Implementation of ldpc (low density parity check) decoder by sweeping through sub-matrices Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity ... 07/05/07 - 20070157061 - Sub-matrix-based implementation of ldpc (low density parity check ) decoder Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing ... 07/05/07 - 20070157060 - Techniques to perform forward error correction for an electrical backplane Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed. ... 06/21/07 - 20070143657 - Encoder, decoder, methods of encoding and decoding An information sequence having a code length of N (N=K+M), where K is information length and M is parity length, is encoded into a code sequence by using an LDPC code. The LDPC code is generated based on a matrix H, with M rows and N columns. The matrix H ... 06/21/07 - 20070143656 - Ldpc concatenation rules for ieee 802.11n system with packets length specified in octets An improved LDPC encoding with concatenation rule and code size with packet lengths specified in octets is provided. The LDPC block size is selected to be an integer number of OFDM tones. The concatenation rule is an improvement of the shortening and puncturing scheme for low data rate. The improvement ... 06/21/07 - 20070143655 - Ldpc concatenation rules for ieee 802.11n system with packets length specified in ofdm symbols A method of concatenation for LDPC encoding in an OFDM wireless system selects codewords based on the data packet payload size, wherein the payload size is the number of transmitted information bits in octets. For low transmission rates, shortening and puncturing across all codewords within the packet is applied to ... 06/21/07 - 20070143654 - Method and apparatus for using long forward error correcting codes in a content distribution system Method and apparatus for using long FEC codes in a content distribution system is described. One aspect of the invention relates to encoding frames of content. Each frame is partitioned into un-coded bits and bits to be encoded. For each frame, an FEC code is applied to the bits to ... 06/14/07 - 20070136636 - Data encoding method for error correction A data encoding method for error correction is provided. Before recording data into a recording media, the data are added with an Error Correction Code (ECC) comprising Check Sum on Row (CSR) and Check Sum on Column (CSC), thereby forming an ECC block. More than one ECC block are integrated ... 06/14/07 - 20070136635 - Method of generating structured irregular low density parity checkcodes for wireless systems A method of generating structured irregular LDPC codes for a wireless network such as a wireless local area network (WLAN) system, allowing systematic generation of improved code ensembles using density evolution, and providing essentially the best tradeoff between decoding threshold and decoding complexity. Such an LDPC code has a higher ... 05/31/07 - 20070124644 - Iterative metric updating when decoding ldpc (low density parity check) coded signals and ldpc coded modulation signals Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been ... 05/31/07 - 20070124643 - Method, encoder and communication device for encoding parallel concatenated data A method of encoding data in a code block comprising an information bit sequence in a communication device of a communication system comprising the steps of distributing the bits of the information bit sequence of a first coding branch having a length k into a first plurality of n subsets ... 05/24/07 - 20070118787 - Method and apparatus for forward error correction in a content distribution system Method, apparatus, and computer readable medium for forward error correction (FEC) in a content distribution system is described. One aspect of the invention relates to encoding frames of content. In one example, each frame is set partitioned into un-coded bits and bits to be encoded. For each frame, parity bits ... 05/17/07 - 20070113142 - Method and system for providing low density parity check (ldpc) encoding An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences ... 05/03/07 - 20070101229 - Ldpc concatenation rules for 802.11n systems Improved LDPC code structure and concatenation rules for IEEE 802.11n systems, providing two code sets per rate, one longer codeword and one shorter codeword. The longer codeword length is determined by the system parameters, while the shorter codeword length is ⅓ of the longer codeword length. A LDPC concatenation rule ... 05/03/07 - 20070101228 - Burst transmission A terrestrial digital video broadcasting (DVB-T) network is used to transmit IP datagrams to receiving devices using multiprotocol encapsulation (MPE). MPE datagram sections and forward error correction (FEC) datagram sections are transmitted in separate time-sliced bursts using transport stream packets with different packet identifiers (PIDs). ... 04/26/07 - 20070094565 - Decoding of multiple data streams encoded using a block coding algorithm A system implemented for example in the form of an SoC comprises a first demodulator for generating a first data stream to be decoded, and a second demodulator for generating a second data stream to be decoded, and a block decoder. The block decoder comprises an input memory for storing ... 04/26/07 - 20070094564 - Systems and methods for message encoding and decoding Presented herein are systems and methods for checking the integrity of data transmissions between or within one or more digital processing systems by identifying a data characteristic that is likely to change if there is an error in transmission. According to one embodiment, data messages are modified to achieve a ... 04/19/07 - 20070089021 - Transmit driver data communication Aspects describe a transmit driver that processes data communication between a scheduler and a turbo encoder. Transmit driver receives a request for a super frame and ascertains whether it has enough information to start the super frame. If there is enough data, the super frame is written to an appropriate ... 04/19/07 - 20070089020 - Block processing in a block decoding device A device for storing blocks of bits intended to be decoded according to a block decoding algorithm. The blocks are likely to belong to a given category out of a first category and a second category. The first category corresponds to a first given block size, and the second category ... 04/19/07 - 20070089019 - Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured low-density parity-check (ldpc) codes, including calculating check-to-variable messages An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements include an iterative decoder ... 04/19/07 - 20070089018 - Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured low-density parity-check (ldpc) codes, including reconfigurable permuting/de-permuting of data values An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements can include a permuter ... 04/19/07 - 20070089017 - Error correction decoder, method and computer program product for block serial pipelined layered decoding of structured low-density parity-check (ldpc) codes with reduced memory requirements An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements include an iterative decoder ... 04/19/07 - 20070089016 - Block serial pipelined layered decoding architecture for structured low-density parity-check (ldpc) codes An error correction decoder for block serial pipelined layered decoding of block codes includes primary and mirror memories that are each capable of storing log-likelihood ratios (LLRs) for one or more iterations of an iterative decoding technique. The decoder also includes a plurality of elements capable of processing, for one ... 04/12/07 - 20070083802 - Broadcast message passing decoding of low density parity check codes Decoding by passing messages back and forth between a set of variable nodes and a set of check nodes, where at least one of the nodes broadcasts the same message to each of its associated nodes, is provided. For example, the variable nodes can broadcast and the check nodes can ... 03/29/07 - 20070074091 - Checksum calculation In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first ... 03/22/07 - 20070067694 - Set of irregular ldpc codes with random structure and low encoding complexity A set of irregular LDPC codes having a pseudo-random structure and low encoding complexity. A block-cyclic LDPC code has an irregular row or an irregular column weight and includes a parity check matrix and an encoding matrix each of which has a pseudo-random structure. This allows the code to have ... 03/15/07 - 20070061665 - Clock and data recovery system and method for clock and data recovery based on a forward error correction The forward error correction based clock and data recovery system according to the invention comprises a data latch (16) for intermediately storing received data, which is triggered by a sampling clock (sclk). The system further comprises an error determination unit (20, 21) for determining whether and which of the sampled ... 03/01/07 - 20070050695 - Error correction code transformation technique In one embodiment, a system comprises a source configured to provide data and a source error correction code (ECC) generated according to a source ECC scheme; a circuit comprising an ECC transform unit configured to generate a target ECC from the data, detect an error in the data responsive to ... 03/01/07 - 20070050694 - Modified branch metric calculator to reduce interleaver memory and improve performance in a fixed-point turbo decoder A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor ... 01/25/07 - 20070022353 - Utilizing variable-length inputs in an inter-sequence permutation turbo code system The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means ... 01/25/07 - 20070022352 - Code design and implementation improvements for low density parity check codes for wireless routers using 802.11n protocol Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM ... 01/11/07 - 20070011557 - Inter-sequence permutation turbo code system and operation methods thereof A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce ... 01/11/07 - 20070011556 - Media packet structure for real time trasnmission via packet switched networks The present invention proposes a media packet structure comprising an insensitive part (ISP) comprising a block of media data (BMD) and a sensitive part (SP), said sensitive part being protected by a checksum (CS), said sensitive part comprising error correction codes (FEC) for correcting the block of media data (BMD) ... 12/28/06 - 20060294447 - Apparatus and method for parity generation in a data-packing device A data-packing device, such as a direct memory access controller (DMA), aligns data at a granularity smaller than an error protected unit (EPU) encoded by an error correction code (ECC) in the memory. For example, the data alignment is at a double-word level or a byte level. The data-packing device ... 12/28/06 - 20060294446 - Techniques for reconfigurable decoder for a wireless system A system, apparatus, method, and article including a decoder having multiple connections defined between multiple check nodes and multiple symbol nodes. The connections between the multiple check nodes and the multiple symbol nodes are reconfigurable to enable the decoder to decode multiple codes. Other embodiments are described and claimed. The ... 12/28/06 - 20060294445 - Ara type protograph codes An apparatus and method for encoding low-density parity check codes. Together with a repeater, an interleaver and an accumulator, the apparatus comprises a precoder, thus forming accumulate-repeat-accumulate (ARA codes). Protographs representing various types of ARA codes, including AR3A, AR4A and ARJA codes, are described. High performance is obtained when compared ... 10/26/06 - 20060242530 - Method for constructing finite-length low density parity check codes A technique for construction of finite-length low-density parity check (LDPC) codes is herein disclosed which advantageously provides a flexible tradeoff of low decoding thresholds and low error-floors. ... 10/19/06 - 20060236191 - Method and apparatus for generating block-based low-density parity check matrix and recording medium having recorded thereon code for implementing the method A method of and an apparatus for generating a block-based low density parity check (LDPC) matrix, where calculation of an inverse matrix is not necessary and back-substitution is possible over the entire matrix area, and a recording medium having recorded thereon code for implementing the method. An area of the ... 10/05/06 - 20060224935 - System correcting random and/or burst errors using rs (reed-solomon) code, turbo/ldpc (low density parity check) code and convolutional interleave System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed ... 10/05/06 - 20060224934 - System correcting random and/or burst errors using rs (reed-solomon) code, turbo/ldpc (low density parity check) code and convolutional interleave System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed ... 09/28/06 - 20060218459 - Coding systems and methods Disclosed herein are various embodiments of coding systems and methods. In one method embodiment, among others, a coding method comprises receiving input parameters, and providing a packet comprising variable FEC code block sizes throughout the packet structure based on the input parameters. ... 09/28/06 - 20060218458 - Efficient decoding Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first ... 09/21/06 - 20060212772 - Method and apparatus for data encoding A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addition (e.g. to a common store) ... 09/14/06 - 20060206775 - Encoder based error resilience method in a video codec Improved error resiliency of an encoding device, such as a video codec or encoder, operating in a compressed data transmission system, is achieved by enabling the encoding device to “shadow” or mimic the error conditions of a decoding device that receives and decodes compressed data sent by the encoding device. ... 08/31/06 - 20060195754 - Amp (accelerated message passing) decoder adapted for ldpc (low density parity check) codes AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes. A novel approach is presented by which the LDPC coded signals may be decoded in a more efficient, faster, and less computationally intensive manner. Soft bit information, generated from decoding a higher layer square sub-matrix of a ... 07/27/06 - 20060168493 - Data detection and decoding system and method A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity. ... 07/13/06 - 20060156170 - Methods for the generation of s-random interleavers for turbo decoders with a parallel structure The method allows to obtain, starting from an initial S-random interleaver permutation, stored in memory devices and having a spread S, a size K and a degree of parallelism M<K, and collision-free, an interleaver permutation having an increased size, which is also collision-free, by an expansion technique which is carried ... 07/13/06 - 20060156169 - Ldpc (low density parity check) coding and interleaving implemented in mimo communication systems LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. Initially, a novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than regular LDPC codes ... 07/13/06 - 20060156168 - Construction of irregular ldpc (low density parity check) codes using rs (reed-solomon) codes or grs (generalized reed-solomon) code Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. A novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than ... 07/13/06 - 20060156167 - Running minimum message passing ldpc decoding The invention relates to a decoding method for decoding Low-Density Parity Check codes in transmission and recording systems. The method comprises a running minimum loop comprising the following iterative sub-steps:—reading a reliability value from the input sequence of input reliability values,—comparing said reliability value with a stored value,—overwriting the stored ... 07/06/06 - 20060150055 - Adaptive information delivery system using fec feedback A method and apparatus for optimizing the data transfer rate over a transport layer (i.e., communication link) such as the Internet is provided. Initially the data is prepared for transmission by a transfer rate controller, then the data is encoded by a Forward Error Correction (FEC) encoder. After the data ... 07/06/06 - 20060150054 - Decoding device for decoding product code and decoding method using the same A decoding device for decoding a product code and a decoding method using the same are provided. The decoding device comprises an erasure flag processor, a decoder and a confidence flag processor. The erasure flag processor determines to set a particular value or a non-particular value for each erasure flag ... 07/06/06 - 20060150053 - Switching method for mdc/scalable coding A system and method is provided for switching between multiple description coding and scalable coding that is dependent on the network characteristics and uses forward error correction (FEC) and scalable or prioritized video. ... 07/06/06 - 20060150052 - Accepting a set of data in a computer unit A method for transferring at least one data record from an external data source into a processor unit, e.g., and a suitably designed processor unit are described. In such a method for transcribing at least one data record from the external data source to a processor unit, the at least ... 06/29/06 - 20060143553 - Error correction processing unit and error correction processing method The present invention comprises generating sections which generate intermediate information for error correction processing in units of surfaces from an error correction block stored in a first storage section, the error correction block having A/B surfaces, second storage sections which store intermediate information, a processing section which generates correction information ... 06/22/06 - 20060136799 - Ldpc decoding apparatus and method with low computational complexity algorithm Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a ... 06/22/06 - 20060136798 - Method and apparatus for decision threshold control in an optical signal receiver An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and zeros. ... 06/22/06 - 20060136797 - System and method for forward error correction decoding using soft information A system and method for soft decision forward error correction (FEC) decoding may be used to determine a possible error in a differential detection signal, for example, in a DPSK system. The system and method uses the constructive and destructive signals from a demodulator to provide an error locating signal. ... 06/15/06 - 20060129901 - Method of writing data and channel adapter A method of writing data includes receiving a record of a variable-length data format, creating a field-checking code for each field of the record received, creating a block-checking code in units of the fixed-length data for the data received, and writing data by reading the record, assembling fixed length data ... 05/18/06 - 20060107173 - Data processing method, data recording apparatus and data transmission apparatus The present invention provides a data processing method that can reduce the number of data blocks belonging to a same error-correcting code word for two-dimensional error bursts that give rise to errors over a plurality of transmission channels. There is provided a data processing method for coding digital data by ... 05/18/06 - 20060107172 - Apparatus for accessing and transferring optical data An accessing/transferring apparatus has a first memory having multiple memory banks, each of the memory banks having multiple logical memory sections, each of the logical memory sections forming a memory matrix; a memory controller that uses the page-mode function or alternate-bank-access function of the first memory to write the data ... 05/18/06 - 20060107171 - Interleaver and de-interleaver systems This invention relates to bit interleaver and de-interleaver apparatus, methods and processor control code for use in MIMO (Multiple-input multiple-output) communications systems, in particular MIMO systems employing OFDM (orthogonal frequency division multiplexing). We describe a block interleaver for a MIMO communications system, said interleaver being configured to interleave a block ... 05/18/06 - 20060107170 - Methods for the determination of fec parameters in dmt based xdsl systems in the presence of system imposed constraints The present invention provides procedures for computing Forward Error Correction (FEC) parameters given a set of constraints on maximum interleaver memory, maximum interleaver depth, maximum codeword size, maximum number of check bytes, maximum number of FEC codewords per Discrete Multi-Tone (DMT) symbol, and minimum number of DMT symbols that the ... 05/18/06 - 20060107169 - Support of a forward error correction To support a forward error correction scheme, in which a code of the forward error correction scheme is employed at a transmitting end for encoding data for a transmission to a receiving end, the transmitting end compresses at least one binary parity check matrix associated to the employed code of ... 05/11/06 - 20060101318 - Method and device for building a variable-length error code The invention relates to a variable-length error-correcting (VLEC) code technique, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1−tuples distant of the minimum diverging distance d[min] from the codewords ... 05/04/06 - 20060095827 - Method and apparatus of turbo encoder Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to transmit a data sub-block of the encoded data block in a time slot of a physical channel of the wireless ... 04/20/06 - 20060085718 - Interleaved recording of separated error correction encoded information An error correction code system, e.g. of a magnetic tape drive, applies error correction redundancy to data, separates it, or interleaves it, and records it into separate groups. An error correction encoder applies an outer error correction code to one of the separate groups of information, forming one set of ... 04/13/06 - 20060080587 - Error detection using codes targeted to prescribed error types Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that corresponds to one or more dominant error events for the communication system. The invention develops a class of error detection codes ... 04/06/06 - 20060075319 - Packet transmission redundancy selection apparatus and method A high speed downlink packet access communication system method that supports a plurality of redundancy variations that are characterized by at least a first parameter that comprises an indicator regarding self-decodability of a corresponding packet and a second parameter that comprises a selection of a particular redundancy version from amongst ... 03/30/06 - 20060069977 - Error correction device In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector ... 03/16/06 - 20060059401 - Design of rate-compatible ldpc codes using optimal extending Provided is a technique of encoding and decoding an LDPC code having a plurality of code rate using a single codec in a wired and wireless communication channel coding, and a method of designing a rate compatible low density parity check (LDPC) code including a step of successively adding new ... 03/16/06 - 20060059400 - System and method for in-line consistency checking of packetized data A system and method for efficiently detecting and correcting transmission errors in packet-based communications by using cumulative error detection codes. The system may comprise a transmitting unit, which transmits one or more data packets. Each of the transmitted packets may comprise a plurality of transmission subunits. The transmitting unit preferably ... 03/09/06 - 20060053359 - Encoder using low density parity check codes and encoding method thereof An encoder using LDPC (low density parity check) codes, and an encoding method. The encoder comprises a parity check matrix generator for generating a parity check matrix H; and a codeword generator for processing the parity check matrix H to generate a codeword, and the codeword generator comprises: an AB ... 02/23/06 - 20060041817 - Accounting for error carryover in error correction on m-bit encoded links 64/66b encoding (IEEE 802.3ae Standard for 10 Gigabit Ethernet) is based on a self-synchronous scrambler which inherently duplicates errors occurring in the transmission line. An error carryover indicator ECI vector is used to correct duplicated errors crossing the codeword boundary and entering into the next codeword. The ECI vector is ... 02/16/06 - 20060036923 - Systems and methods for decreasing latency in a digital transmission system Disclosed herein are various embodiments of methods, systems, and apparatus for encoding OFDM packets in a digital communication system. In one exemplary method embodiment, LDPC codewords in an IEEE 802.11 wireless transmission are shortened, decreasing the iterations necessary to insure accurate communications. The codewords are shortened by adding known bits ... 02/09/06 - 20060031735 - Method and circuit for correcting power amplifier distortion An equalizing and error correcting section includes an equalizing section, an error processing sections, and a select section. The equalizing section outputs the received data subjected only to channel compensation and phase rotation compensation and the received data subjected not only to those compensations but also to power amplifier distortion ... 02/09/06 - 20060031734 - Irregularly structured, low density parity check codes An error correction codeword. In one embodiment, an irregularly structured LDPC code ensemble possessing strong overall error performance and attractive storage requirements for a large set of codeword lengths. Embodiments of the invention can offer communication systems with better performance and lower terminal costs due to possible reductions in mandatory ... 01/26/06 - 20060020870 - Layered decoding of low density parity check (pdpc) codes A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. ... 01/26/06 - 20060020869 - Decoding block codes This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder (910) receiving a length n soft input vector, creating a binary vector ... 01/26/06 - 20060020868 - Ldpc decoding methods and apparatus A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code ... 01/19/06 - 20060015790 - Low overhead coding techniques A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first symbol in the encoded ... 12/29/05 - 20050289431 - Efficient address generation for forney's modular periodic interleavers An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and ... 12/29/05 - 20050289430 - Expanding architecture for error correction code and method for the same An expanding error correction architecture groups the output data of a data end to several parts, and each grouped output data of the data end is connected to one of a plurality of error correction circuit to be processed for a check sum. One part of the output data of ... 12/22/05 - 20050283703 - Ldpc decoder An LDPC decoder comprising a determined number of processing units operating in parallel, a storage means capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each ... 12/22/05 - 20050283702 - Soft-decision decoding using selective bit flipping A method or apparatus that can form and test a data block variant by flipping a selected potentially bad bit that is consecutive with 1 or 2 sequences of several potentially good bits of a received block. The variant correctability test is optionally repeated several times before receiving another data ... 12/15/05 - 20050278602 - Data transmitting apparatus, data receiving apparatus, data transmitting method, and data receiving method A data transmitting apparatus that transmits a plurality of bits in parallel in synchronization with clocks includes a code generating unit that divides transmission data into a plurality of partial data, and generates an error correction code for each of the partial data; a data dividing unit that divides the ... 12/08/05 - 20050273687 - Apparatus and method for turbo decoding using a variable window size An apparatus and method for turbo decoding using a variable window size. A control logic block receives information about a code rate of received data bits and a data block size, adjusts a window size according to the code rate information, and computes an initial delay. Delta metric blocks compute ... 12/08/05 - 20050273686 - Arrangement in a network node for secure storage and retrieval of encoded data distributed among multiple network nodes Data is stored using multiple selected network nodes in a network based on encoding of the data into multiple distinct encoded data units according to a prescribed encoding operation. The secure encoding operation generates a first prescribed number of encoded data units, whereas merely a second prescribed number of the ... 12/01/05 - 20050268202 - Quasi-block diagonal low-density parity-check code for mimo systems A method codes multiple data streams in multiple-input, multiple-output communications systems. In a transmitter, an input bitstream is encoded as codewords b in multiple layers. Each layer is modulated. A quasi-block diagonal, low-density parity-check code is applied to each layer, the quasi-block diagonal, parity-check code being a matrix H, the ... 12/01/05 - 20050268201 - Method and system for tracking sequence numbers The invention concerns a method (500) for tracking sequence numbers. The method includes the steps of detecting (512) an error in a first set of data (120), determining (514) a range (144) of possible sequence numbers (122) for a second set of data (120) and using the range of possible ... 11/24/05 - 20050262417 - Circuit and method for encoding data and data recorder To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), ... 11/24/05 - 20050262416 - Circuit and method for encoding data and data recorder To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), ... 11/24/05 - 20050262415 - Method and apparatus for convolutional interleaving/de-interleaving technique The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates ... 11/17/05 - 20050257115 - Decoding for algebraic geometric code associated with a fiber product The present invention concerns a method of decoding a one-point algebraic geometric code defined on an algebraic curve represented by an equation in X and Z of degree 2μφ in Z, where φ is a strictly positive integer and μ an integer greater than 1, obtained by taking the fiber ... 11/10/05 - 20050251725 - Signal processing methods and systems Signal processing systems and methods, illustratively for communication signals such as video communication signals, are provided. Adaptive interleaving systems and methods enable interleaving of information using different interleaving lengths. Encryption may also be combined with interleaving to control the position of information in an interleaved information stream. Corresponding de-interleaving and ... 11/10/05 - 20050251724 - Method and apparatus for generating check matrix A method of generating a check matrix for an LDPC code includes determining a coding rate, generating a basic matrix that satisfies predetermined conditions, determining a number of columns of a check matrix, substituting rows of the basic matrix based on a specific relational equation, provisionally searching an ensemble of ... 11/10/05 - 20050251723 - Flexible forward error correction A forward error correction method including inserting at least one filler symbol into an input data stream at a pre-determined position, thereby generating a precoded symbol group, FEC encoding the precoded symbol group, thereby generating a code word, removing at least one of the filler symbols from the code word, ... 11/03/05 - 20050246610 - Coding device and communication system using the same A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved ... 11/03/05 - 20050246609 - Coding device and communication system using the same A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved ... 11/03/05 - 20050246608 - Coding device and communication system using the same A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved ... 11/03/05 - 20050246607 - Coding device and communication system using the same A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved ... 11/03/05 - 20050246606 - Decoding ldpc (low density parity check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A novel approach of decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various ... 10/27/05 - 20050240853 - Decoding device, decoding method, and program The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a ... 10/20/05 - 20050235191 - Method of converting parity check matrix for low density parity check coding A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information can be reduced by using the converted parity ... 10/06/05 - 20050223305 - Method and apparatus for efficient computation of check equations in periodical low density parity check (ldpc) codes A periodic Low Density Parity Check (LPDC) coding apparatus and method allows reference to an LDPC code parity check matrix, where such reference is accomplished row by row. A specially configured memory and cyclical shift operation are used by the apparatus to efficiently compute check equations of the periodic LDPC ... 09/29/05 - 20050216813 - Fixed content distributed data storage using permutation ring encoding A file protection scheme for fixed content in a distributed data archive uses computations that leverage permutation operators of a cyclic code. In an illustrative embodiment, an N+K coding technique is described for use to protect data that is being distributed in a redundant array of independent nodes (RAIN). The ... 09/22/05 - 20050210357 - Channel encoding adapted to error bursts A method of encoding information symbols comprises a step in which a word v, orthogonal to a matrix H, the element Hαβ of which is equal to the value taken by some monomial hα=YjXi at the point Pβ of some locating set, is associated with every block of k information ... 09/22/05 - 20050210356 - Layered multiple description coding A data sequence may be encoded in a plurality of layers of multiple description coding. The layers of multiple description coding may include a first and a second layer of multiple description coding. The first layer of multiple description coding may include an initial part of a data sequence as ... 09/15/05 - 20050204253 - Algebraic low-density parity check code design for variable block sizes and code rates A higher code rate Low-Density Parity Check (LDPC) matrix may be designed by concatenating additional matrices to a π-rotation parity check matrix. The concatenated matrix may be selected such that the resultant LDPC matrix exhibits good expansion characteristics to enable the LDPC matrix to be used with variable block length ... 09/08/05 - 20050198557 - Integrated circuit In one embodiment, a method is provided that may include generating, at least in part by first circuitry comprised in an integrated circuit, check data based at least in part upon other data, and/or determining at least in part by the first circuitry, one or more locations of the check ... 09/01/05 - 20050193310 - Method and apparatus for controlling transmitting, receiving, and re-transmission The present invention relates to a method and apparatus that are capable of executing the error correction decoding process while controlling the increase in the amount of data that is stored in the receiving apparatus. There is provided a transmitting apparatus for transmitting the data to a receiving apparatus to ... 09/01/05 - 20050193309 - Methods for forward error correction coding above a radio link control layer and related apparatus Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by transitions that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from a Point-to-Point (PTP) connection to a Point-to-Multipoint ... 09/01/05 - 20050193308 - Turbo decoder and turbo interleaver A processor on which software interleaver is run is provided. The interleaver generation is split into two parts to reduce the overhead time of interleaver changing. First preprocessing prepares seed variables requiring a small memory. Second on-the-fly address generation generates interleaved address through simple adding and subtracting operations using the ... 08/25/05 - 20050188291 - Error locating methods and devices for algebraic geometric codes In a method of decoding a one-point algebraic geometric code of dimension k and length n, in order to identify the position of the errors in a received word, the syndromes matrix S, of dimension (n−k)×(n−k) is defined, of which the elements Sij of each line i are calculated, for ... 08/18/05 - 20050182996 - Channel signal concealment in multi-channel audio systems A parametric model is used for error concealment. The model filter allows for recovering signal components of original audio channel signals that now are lost or erroneous from signal components of at least one other audio channel. During error-free reception of valid frames, the parameters of that model will be ... 07/14/05 - 20050154958 - Method and apparatus for varying lengths of low density party check codewords A method and apparatus for encoding/decoding information using low density parity check (LDPC) codewords of varying lengths. In one implementation, an encoder/decoder uses a parity check matrix having a size that corresponds to a length of information for each codeword. In one example, the size of the parity check matrix ... 07/14/05 - 20050154957 - Method and apparatus for decoding forward error correction codes A method for decoding information received at a network device may include a first decoding process which applies a first algorithm iteratively until a stopping criterion is reached and a second decoding process which may flip a logic state of one or more bits. In one implementation using low density ... 07/14/05 - 20050154956 - Detection of errors A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but ... 06/30/05 - 20050144549 - Methods for coding and decoding ldpc codes, and method for forming ldpc parity check matrix where ak, C, and γ mean parameters. The present invention may significantly decrease a time to discover an optimal code by using a power-law distribution with less parameters in designing the LDPC codes, as compared with numerical optimization in a global parameter space. ... // - 2 - ... // - 1 - ... // - 2 - ... 06/30/05 - 20050144548 - Communicating using a partial block in a frame A method according to one embodiment may include: at least one of transmitting and receiving a first portion of a first protected data block within a first frame; and at least one of transmitting and receiving a second portion of the first protected data block within a second frame. Of ... 06/23/05 - 20050138519 - Ldpc decoder, corresponding method, system and computer program A decoder of LDPC codewords on GF(rq), using the iterative belief propagation algorithm comprises at least storing means to store a posteriori information on variables. Updating means updates the a posteriori information on variables, and computation means computes variables to constrain messages from a posteriori information on variables and variable ... 06/23/05 - 20050138518 - Data storage systems A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to ... 06/16/05 - 20050132260 - Apparatus and method for coding and decoding irregular repeat accumulate codes An apparatus and method for coding an irregular Repeat Accumulate (RA) code. A repeater repeats a received information word such that the information word corresponds to weights of a first information part and a second information part of a parity check matrix in which permutation matrixes are arranged in the ... 06/16/05 - 20050132259 - Error correction method and system An error correction code method comprises examining a validator of one of a plurality of data in a data stream at a first processing stage and directing the one of the plurality of data through at least one subsequent processing stage to a corrected output if the validator indicates an ... ### FreshPatents.com Support |