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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Including Test Pattern Generator > Testing Specific Device Testing Specific DeviceTesting Specific Device patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266290 - Test apparatus, test method, and program There is provided a test apparatus that tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the ... 11/15/07 - 20070266289 - Testing mobile wireless devices during device production A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or application usage when the device is ... 10/18/07 - 20070245198 - Method and apparatus for interactive generation of device response templates and analysis A device response template generator software program includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses. The GUI allows patternization of the command response to that the information contained in the response can be read, in the form of ... 10/04/07 - 20070234169 - Generating masking control circuits for test response compactors Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about ... 10/04/07 - 20070234168 - Semiconductor integrated circuit device and inspection method therefor A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected ... 09/27/07 - 20070226574 - Automated high voltage defibrillator tester The present invention is directed to an automated high voltage (HV) defibrillator tester system that is able to asynchronously test a plurality of devices (e.g. defribillators etc.). The HV defibrillator tester system includes a first field programmable gate array (FPGA) connected to a set of tester modules. Each tester module ... 09/27/07 - 20070226572 - Soft error rate analysis system A method for improving reliability of an electronic system by evaluating a soft error rate is disclosed. A gate-level representation of the electronic system is converted to a graph, the graph having vertices and edges that correspond to nodes and gates of the electronic system. Input vectors are generated, which ... 09/20/07 - 20070220392 - Method and apparatus for automatic generation of system test libraries The present invention provides an apparatus to generate system test libraries for solution testing involving heterogeneous devices from different vendors. It provides a unified user interface, which can use the information input by the user to execute the tests based on provided device and network topology libraries to generate the ... 09/20/07 - 20070220391 - Integrated circuit with scan-based debugging and debugging method thereof An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the ... 09/06/07 - 20070208985 - Multi-stream interface for parallel test processing Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates ... 09/06/07 - 20070208984 - Methods and apparatus using a service to launch and/or monitor data formatting processes In one embodiment, a method of operating a number of data formatters 1) blocks execution of a tester's test processes that generate test results, the test results pertaining to test of at least one device under test (DUT); 2) launches a number of data formatters, operable to format the test ... 07/19/07 - 20070168817 - Data capture in automatic test equipment A method for use with automatic test equipment (ATE) having a site that holds a device under test (DUT) includes receiving data from the DUT at a first rate, storing the data in a buffer, moving the data out of the buffer at a second rate, where the second rate ... 07/12/07 - 20070162808 - Semiconductor device testing An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical ... 06/28/07 - 20070150783 - Methods and apparatus to abstract events in software applications or services According to some embodiments, a system may be monitored to detect change events. A sequence associated with the detected change events may then be stored. The sequence may then be modified by deleting information associated with a detected change event. The sequence might also (or instead) be modified by adding ... 05/31/07 - 20070124638 - Test apparatus and test method The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every ... 04/19/07 - 20070089014 - Semiconductor integrated circuit and method of fabricating the same To provide a semiconductor integrated circuit device in which an occupied area is suppressed from increasing and a high-performance test circuit is included, There is provided a semiconductor integrated circuit having a test circuit, by determining arrangement positions of cells forming a circuit to be tested and non-connected cells prepared ... 04/19/07 - 20070089013 - System and method for testing ports of a computer The present invention provides a method for testing ports of a computer. The method includes steps of: connecting the testing ports and the non-testing ports of the computer according to a configuration document; creating virtual devices corresponding to the non-testing ports; analyzing corresponding relations between the virtual devices, the non-testing ... 04/19/07 - 20070089012 - System and method for testing a light emitting diode panel An exemplary system for testing light emitting diode (LED) panel is disclosed. The system includes: a symbol arranging module (12) for arranging a group of symbols; an input/output module (14) for outputting a symbol and corresponding number of lightening LEDs displayed on the LED panel, and receiving a symbol and ... 04/19/07 - 20070089011 - Method and apparatus to monitor stress conditions in a system Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error ... 03/22/07 - 20070067693 - Method of testing driving circuit and driving circuit for display device A test signal is supplied to a test switch provided between a D/A converter for selecting and outputting a gray scale voltage of the driving circuit and an amplifier for amplifying and supplying an output voltage at the D/A converter to set a test mode, and an output voltage of ... 03/15/07 - 20070061659 - Methods for testing a plurality of semiconductor devices in parallel and related apparatus A method for testing a semiconductor device includes generating chip identification data for each of a plurality of devices under test to collect a plurality of chip identification data respectively corresponding to the plurality of devices under test. The plurality of chip identification data for the plurality of devices under ... 03/15/07 - 20070061658 - Testing circuit and related method of injecting a time jitter A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection ... 03/15/07 - 20070061657 - Delay fault testing apparatus A delay fault testing apparatus includes a scan device having a first input for receiving a data to the core under test, an update device including an input electrically connected to a first output of the scan device, a first multiplexer including a first input electrically connected to the output ... 02/22/07 - 20070043994 - Obtaining test data for a device Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining a second part of the test data by testing the device at second points of the ... 02/08/07 - 20070033474 - Production test technique for rf circuits using embedded test sensors A single test stimulus and a simple test configuration with embedded envelope detectors are used to estimate all the specification values of interest for an RF circuit under test in an integrated circuit chip. Envelope detectors are deployed as sensors inside the circuit under test. Where more than one circuit ... 01/25/07 - 20070022350 - Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system Although various embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without ... 01/11/07 - 20070011546 - Ic output signal path with switch, bus holder, and buffer An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19). ... 01/11/07 - 20070011545 - System and method for testing a nas A system for testing a NAS includes: a data storage device (3) connected with a NAS (6) for storing function test program and test data; a host computer (1) connected with the NAS being used to issue commands for the NAS to self-test itself via the function test program and ... 01/11/07 - 20070011544 - Reprogramming of tester resource assignments A method including creating a mapping file and a package test program for testing an electronic package. The package comprises a device. The package test program comprises source code for a device test program for testing the device and source code from the mapping file. The device test program source ... 12/28/06 - 20060294444 - Apparatus and method for testing ps/2 interface An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock pin of the PS/2 interface. The LEDs coupled to the micro controller unit simulate ... 12/14/06 - 20060282736 - Test device with test parameter adaptation A test device for testing a device under test, wherein the test device is adapted for providing a connection to a central controller, the test device comprising a first interface for receiving a test procedure activation signal from the central controller, and a processor for performing a test procedure on ... 12/14/06 - 20060282735 - Fasttest module In a method and system for testing a device, a tester provides a first plurality of test signals to the device. A test module includes a plurality of logic circuits operable to concurrently execute a plurality of test programs. The concurrent execution of the plurality of test programs generates a ... 12/14/06 - 20060282734 - Test access control for secure integrated circuits Test access to an integrated circuit 2 is controlled by the use of test access enabling keys. A plurality of different test access enabling levels may be supported corresponding to different keys. The test access control may be performed by dedicated hardware or software executing a secure privilege mode. ... 11/09/06 - 20060253762 - Fpga emulation system This invention features an FPGA emulation system including an FPGA device under test having a plurality of pins. A bus functional model circuit responsive to signals representing predetermined input characteristics of the FPGA device under test and configured to apply one or more signals to the FPGA device under test ... 11/09/06 - 20060253761 - Method of making tissue simulating analog materials and models made from same Disclosed herein are synthetic anatomical models, and methods of making and using same, that are designed to enable simulated use testing by medical device companies, medical device designers, individual inventors, or any other entity interested in the performance of medical devices. These models are unique in possessing a level of ... 10/26/06 - 20060242525 - Method and apparatus for functionally verifying a physical device under test Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT using a constraint-based random test generation process. For example, the architecture, structure, and/or content of the verification test data may be ... 09/28/06 - 20060218456 - Automatic test equipment operating architecture An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms ... 09/21/06 - 20060212770 - Error detection in compressed data A device under test—DUT—, comprising the steps of receiving a first data sequence from the DUT in response to a first stimulus signal, wherein the data of a plurality of internal data sequences of the DUT is compressed into the first data sequence, comparing the first data sequence with expected ... 09/14/06 - 20060206773 - Tester simulation system and tester simulation method using same It is an object of the invention to implement a tester simulation system capable of checking timing margins of an input pattern in a short time, and a tester simulation method using the same. The invention is an improvement of a tester simulation system for simulating a test by a ... 08/31/06 - 20060195749 - Calibration control for pin electronics An integrated circuit for automatic calibration control of pin electronics is disclosed. The integrated circuit includes a substrate, and both pin electronics and a calibration circuit integral with the substrate. The calibration circuit is dedicated to a single channel of automatic testing equipment for a single pin of a device ... 08/31/06 - 20060195748 - Electronic product testing procedure supervising method and system An electronic product testing procedure supervising method and system is proposed, which is designed for use in conjunction with a testing platform and a supervising platform in a factory, and which is characterized by the capability of recording a set of data related to the performance of each step in ... 08/31/06 - 20060195747 - Method and system for scheduling tests in a parallel test system An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a ... 08/24/06 - 20060190794 - Test apparatus and testing method There is provided a testing apparatus that tests a device under test. The testing apparatus includes: a command executing unit operable to sequentially execute commands included in a test program for the device under test every command cycle; a test pattern memory operable to store pattern length identifying information identifying ... 08/10/06 - 20060179386 - Metadata-facilitated software testing Described herein are one or more implementations for facilitation of computer software testing. One or more implementations, described herein, determine logical type of one or more test input-parameters based upon metadata placed on a function under test (FUT) of software. Using that determined logical type, an implementation generates data values. ... 08/03/06 - 20060174178 - Programmable scan shift speed control for lbist Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate ... 08/03/06 - 20060174177 - Apparatus and method for using mems filters to test electronic circuits A mixed-signal integrated circuit testing device includes test electronics for generating a test signal for input to a device under test and receiving a response signal from the device under test, and an interface connected between the test electronics and the device under test. The interface includes at least one ... 07/13/06 - 20060156147 - Method and apparatus for measuring group delay of a device under test A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined period to the device under test to obtain a delayed output signal from the device under test, converting the analog input signal and ... 07/13/06 - 20060156146 - Simplified high speed test system A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter ... 07/13/06 - 20060156145 - Using patterns for high-level modeling and specification of properties for hardware systems This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as ... 07/13/06 - 20060156144 - Removing the effects of unknown test values from compacted test responses Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the ... 07/13/06 - 20060156143 - Method for testing drive circuit, testing device and display device A method of testing a drive circuit including a scan line drive circuit and a data line drive circuit for driving a display is disclosed. The display may include a plurality of scan lines and a plurality of data lines, each of said scan lines including an initial terminal coupled ... 07/13/06 - 20060156142 - Automatic test pin assignment A tool for facilitating automatic test pin assignment for a programmable platform device comprising: a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a ... 07/13/06 - 20060156141 - Defect symptom repair system and methods The present invention is related to the repair of defective items where the defect symptom does not readily suggest the action to repair the item. Test and repair technicians isolate and repair defects. The defect symptom repair system provides a means for the technicians to pool their experience without extensive ... 07/06/06 - 20060150047 - Apparatus and method for generating a high-frequency signal An apparatus for generating an output signal having a higher frequency than a first signal received from a first external connector of a test equipment associated to a first channel and a second signal received on a second external connector of the test equipment associated to a second channel, having ... 06/08/06 - 20060123304 - Enhanced loopback testing of serial devices A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to ... 06/08/06 - 20060123303 - Integrating time measurement circuit for a channel of a test card In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card that is ... 06/08/06 - 20060123302 - Remote diagnosis device, remote diagnosis system and program product In a remote diagnosis system, characteristics data, including at least information indicating characteristics of a terminal device is obtained. Then, a filter based on the obtained characteristics data from a filter group including a plurality of types of filters in which a diagnostic item for outputting is set according to ... 06/08/06 - 20060123301 - Transconductance stage operating as an active load for pin electronics A circuit operating as a bridgeless current load in pin testing equipment for testing a pin of a device under test is disclosed. The circuit includes a transconductance stage having at least a first input and a second input and at least one output capable of being coupled to a ... 06/01/06 - 20060117237 - Systems and methods of test case generation with feedback Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test values for a device under test. A plurality of buckets is each associated with at least one of the test values, each ... 05/18/06 - 20060107160 - Method and apparatus for optimized parallel testing and access of electronic circuits A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local ... 05/18/06 - 20060107159 - Intelligent storage of device state in response to error condition An algorithm helps ensure recordation of the state corresponding to an error or a catastrophic failure that requires a failing device to be sent to the manufacturer, rather than just the state of a byproduct error or failure or the state of an unrelated error or failure. ... 04/20/06 - 20060085715 - Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same A test board for a semiconductor device tester having a modified input/output printed circuit pattern and a testing method using the same are provided. In an embodiment, a modified input/output printed circuit pattern is formed and controlled by a test program, wherein the modified input/output printed circuit pattern is divided ... 04/20/06 - 20060085714 - Method and circuit for measuring capacitance and capacitance mismatch A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit comprises a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and ... 03/23/06 - 20060064620 - Self test for the phase angle of the data read clock signal dqs The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting ... 03/16/06 - 20060059398 - Generation of test mode signals in memory device with minimized wiring A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the ... 03/09/06 - 20060053358 - Method and apparatus for enabling and disabling a test mode of operation of an electronic memory device without additional interconnects or commands A method and apparatus allows an electronic device to operate, first, in a test mode and, second, in a functional mode, the functional mode being the normal operating mode of the device. In the test mode, input stimulus is processed by test circuitry to control device outputs according to a ... 03/09/06 - 20060053357 - Integrated circuit yield and quality analysis methods and systems Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit ... 03/02/06 - 20060048033 - Accessing test modes using command sequences Apparatus and methods are provided. An integrated circuit device receives a sequence of commands and enables a test mode of the integrated circuit device in response to the command sequence when all of the commands of the sequence are correct. The integrated circuit device disables the test mode upon receiving ... 02/23/06 - 20060041814 - Fault diagnosis of compressed test responses having one or more unknown states Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs ... 02/23/06 - 20060041813 - Adaptive fault diagnosis of compressed test responses Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the ... 02/23/06 - 20060041812 - Fault diagnosis of compressed test responses Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. ... 02/23/06 - 20060041811 - Circuit for testing power down reset function of an electronic device A circuit for testing a power down reset function of an electronic device includes a reference power source (Vref), a first variable resistor (R1) with one end connected to the reference power source, a second variable resistor (R2), and a jumper (10). One end of the second variable resistor is ... 02/02/06 - 20060026482 - Test apparatus An inventive test apparatus has a pattern generator for generating an address signal and a test signal to be fed to a device-under-test and an expected value signal to be outputted from the device-under-test to which the test signal has been fed, a logical comparator for comparing an output value ... 01/26/06 - 20060020867 - Method for automated at-speed testing of high serial pin count multiple gigabit per second devices A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path ... 01/05/06 - 20060005096 - Scan stream sequencing for testing integrated circuits A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan ... 12/29/05 - 20050289428 - Architecture and method for testing of an integrated circuit device In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards ... 12/29/05 - 20050289427 - Per-pin clock synthesis A method and system for synthesizing digital clock signals for an electronic device under test having a plurality of pins, said method including generating centrally a reference clock, and distributing said reference clock to a number of electronic circuits, each of said electronic circuit having a test signal processor controlling ... 12/22/05 - 20050283697 - Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation boards, a DUT board, a backplane board, and a power supply unit. The pattern generation boards receive a test program, generate a test pattern signal ... 12/22/05 - 20050283696 - Integrated circuit An integrated circuit including functional circuitry; test circuitry connected to the functional circuitry, wherein the test circuitry is arranged to control the testing of the functional circuitry; and clock signal generating circuitry connected to both the functional circuitry and the test circuitry. The test circuitry is arranged to use the ... 12/15/05 - 20050278599 - Testing device A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a ... 12/15/05 - 20050278598 - Test apparatus There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply and receive signals to/from the electronic device; a plurality of return circuits operable to receive fail timing signals indicating timing at which a fail occurs on output ... 12/08/05 - 20050273685 - Automated and customizable generation of efficient test programs for multiple electrical test equipment platforms Automating techniques provide a way to create efficient test programs for characterizing semiconductor devices, such as those on a silicon die sample. Typically, test program creation is a drawn out process involving data entry for every test to be run as part of the test program. The described techniques improve ... 12/01/05 - 20050268196 - Multiple sweep point testing of circuit devices An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit ... 11/24/05 - 20050262412 - Method and system for simulating a modular test system A method for simulating a modular test system is disclosed. The method includes providing a controller, where the controller controls at least one vendor module and its corresponding device under test (DUT) model, creating a simulation framework for establishing standard interfaces between the at least one vendor module and its ... 11/17/05 - 20050257110 - Method and apparatus for evaluating susceptibility to common mode noise in a computer system A system for injecting noise signals onto power generated by a power source comprising: a voltage source; a device under test having a power input in operable communication with the noise introduction apparatus; and a noise introduction apparatus interposed between the power source and device under test in operable communication ... 11/10/05 - 20050251720 - Single-ended transmission for direct access test mode within a differential input and output circuit An integrated circuit, such as an integrated circuit memory device, includes an output circuit capable to provide a differential signal on first and second contacts during a first mode of operation, such as in a read or write mode of operation, and a single-ended signal on the first contact during ... 11/10/05 - 20050251719 - Test case inheritance controlled via attributes The present invention is directed towards a test case inheritance behavior that can be controlled via attributes. A base test class from which test objects are derived are useful for reducing test case code and management. For example, base test classes and their derived objects can be used to implement ... 11/03/05 - 20050246604 - Office information system having a device which provides an operational message of the system when a specific event occurs An office information system having a device which provides a user with an operational message of the system is disclosed. In an embodiment of the office information system, a path record storage device stores a plurality of path records related to components of the system, each path record indicating a ... 11/03/05 - 20050246603 - Pin coupler for an integrated circuit tester A coupling unit that couples at least two pins of an ATE (Automated Test Equipment) to a pin of a device under test includes an ATE interface for receiving a plurality of first stimulus signals from selected ATE-pins and/or for sending a plurality of first response signals to the selected ... 10/13/05 - 20050229065 - Semiconductor integrated ciruit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one ... 10/13/05 - 20050229064 - Methods and systems for digital testing on automatic test equipment (ate) Methods and systems for digital testing of semiconductor devices are disclosed. The inventions include testing modules (10) for use with automatic test equipment (ATE) 20 and device interface boards (32) in order to extend their capabilities to perform digital testing of semiconductor devices (18). Testing modules (10) disclosed include memory ... 09/29/05 - 20050216811 - Apparatus for testing usb memory and method thereof The present invention discloses a handler of a USB memory device, comprising a tray horizontally moving by a tray loader/unloader, a loading/unloading picking means transferring a case of a plurality of USB memory devices, a shuttle means horizontally moving by a shuttle transfer in a state where the upper surface ... 09/15/05 - 20050204243 - Method and testing system for storage devices under test A testing system for storage devices under test (SDUT) is provided. The system comprises a storage device testing subsystem configured to send testing commands, to process feedback data from said SDUT, and to send power management commands to SDUT power supply systems, a bus, and an application designed to generate ... 07/07/05 - 20050149807 - Parallel source/capture architecture A test system includes a signal source coupled to one or more capture/source channels. The signal source provides a cancellation signal to the one or more channels, which may be utilized by a channel to reduce a portion of the received signal. The resulting signal is then amplified so that ... ### FreshPatents.com Support |