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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Including Test Pattern Generator Including Test Pattern GeneratorIncluding Test Pattern Generator patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266288 - Re-configurable architecture for automated test equipment An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, ... 11/15/07 - 20070266287 - Spatial frequency response measurement method A spatial frequency response (SFE) measurement method applied for measuring an SFR of a specific area of an image module is disclosed. The method includes: utilizing the image module to obtain an image of a test pattern, wherein the test pattern includes a plurality of test areas, each test area ... 10/25/07 - 20070250749 - Test generation methods for reducing power dissipation and supply currents Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state ... 10/04/07 - 20070234165 - Input circuit of semiconductor memory device and test system having the same An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled ... 09/27/07 - 20070226569 - Film-type semiconductor package and method using test pads shared by output channels, and test device, semiconductor device and method using patterns shared by test channels Provided are a film-type semiconductor package and method using test pads shared by output channels, a test device, and a semiconductor device and method using patterns shared by test channels. The semiconductor device includes a film-type semiconductor package and a test device. The film-type semiconductor package outputs test signals through ... 08/30/07 - 20070204194 - Testing of multiple asynchronous logic domains A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator circuits. The first test pulse generator circuit is electrically coupled to the first pin and ... 08/02/07 - 20070180342 - System, method and apparatus for completing the generation of test records after an abort event In one embodiment, a system for formatting test data is provided with at least one data formatter to i) upon receiving notifications of test events, retrieve test data from a data store, and ii) generate a number of test records based on the test data. The system is also provided ... 07/19/07 - 20070168815 - Compositions and methods for use in three dimensional model printing Compositions for use in the manufacture of three-dimensional objects including compositions for use as a support and/or release material in the manufacture of the three-dimensional objects are provided. There is thus provided, in accordance with an embodiment of the present invention, a composition suitable for building a three-dimensional object. The ... 07/19/07 - 20070168814 - Device and method for testing and for diagnosing digital circuits A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for ... 07/19/07 - 20070168813 - System and methods for authoring domain specific rule-driven data generators An automated data generation system and methods are provided to facilitate generation of test data sets for computerized platforms while mitigating the need to store massive quantities of potentially invalid test data. In one aspect, a computerized test system is provided. A rules component is provided to specify one or ... 07/12/07 - 20070162807 - High-speed serial transfer device test method, program, and device A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are successively transferred to each of a plurality of serial transfer channels that a high-speed serial transfer ... 06/14/07 - 20070136631 - Method and system for testing backplanes utilizing a boundary scan protocol A system is provided for testing connectivity of a backplane having card slots with multiple nets in each card slot. The system includes a processor module that generates test vectors based on a net connectivity configuration for a predetermined backplane architecture. A master control card includes a card slot interconnect ... 05/31/07 - 20070124637 - Method and an integrated circuit for performing a test A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated ... 05/17/07 - 20070113136 - Detection rate calculation method of test pattern, recording medium, and detection rate calculation apparatus of test pattern To provide a detection rate calculation method of a test pattern for calculating how much a test pattern can detect short-out generated between the adjacent lines in an integrated circuit. A layout creating program 12 creates layout data 25 from circuit data 21, and creates the information of the adjacent ... 05/17/07 - 20070113135 - Modular compaction of test responses Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain implementations, the compactors are able to detect errors commonly observed from real defects, ... 05/17/07 - 20070113134 - Test data reporting and analyzing using data array and related data analysis Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array is disclosed. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data ... 04/26/07 - 20070094561 - Methods for distribution of test generation programs As described herein, circuit testing algorithms, or portions thereof, can be executed in a distributed manner so that their execution can be over a network of processors. In one aspect, the results that are obtained by such distributed execution are ensured to be consistent with the results that would be ... 04/19/07 - 20070089010 - Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device A test apparatus for testing digitized test responses has a generator (2) and a signal extractor (3). The generator (2) uses direct digital synthesis to generate a set of n digital reference signals (xk, yk) which are orthogonal to one another. In this case, n is a natural number greater ... 04/19/07 - 20070089009 - Semiconductor device Disclosed is a semiconductor device with which test is carried out as two chips A and B arranged facing each other. Each chip includes, for every channel, an input buffer, a serial-to-parallel converter for converting input serial data into parallel data, a frame synchronization circuit for detecting a frame for ... 04/19/07 - 20070089008 - Method and apparatus for performing test pattern autograding A method, computer program product, and data processing system for minimizing the number of test sequences needed to achieve a desired level of coverage of events in testing a semiconductor design is disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to ... 04/19/07 - 20070089007 - Method and apparatus for measuring test coverage A method, computer program product, and data processing system for determining test sequences' coverage of events in testing a semiconductor design are disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the design under test are transmitted to a “backend” computer ... 04/19/07 - 20070089006 - Io self test method and apparatus for memory An embodiment may comprise a memory with a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with ... 04/05/07 - 20070079204 - Integrated circuit testing module including signal shaping interface Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which ... 03/22/07 - 20070067692 - Random number generation including skewness control Random numbers can be generated in a statistically independent manner and with identical probability if the bits generated by a controlled bit generator are stored by a storage in a plurality of memory regions, wherein the bits are each stored in such memory regions associated with a difference of the ... 03/15/07 - 20070061656 - Test data generator, test system and method thereof A test data generator, test system and method thereof are provided. In the example method, parallel test data may be received at a first data rate. The received parallel test data may be converted into serial test data at a second data rate. Noise (e.g., jitter noise, level noise, etc.) ... 03/15/07 - 20070061655 - Path data transmission unit A path data transmission unit in which, if one of a normal path for handling normal data and a test path for handling test data is selected, the other path is disabled to reduce power consumption ;includes an edge detector, a first path data transmission block, and a second path ... 02/08/07 - 20070033473 - Lsi inspection module, control method for lsi inspection module, communication method between lsi inspection module and inspection apparatus, and lsi inspection method In an LSI inspection module, an I/O interface compatible with the I/O interface of an LSI as an inspection target is provided and testing data is stored in a memory for test data. During inspection, an LSI inspection apparatus controls the interface control circuit of the inspection module by setting ... 01/11/07 - 20070011543 - Test pattern generation method A high-quality test pattern for testing a delay fault is generated at a high speed. In order that a second test pattern provided at a test cycle that follows a test cycle should be generated, a fault value set up in a circuit is propagated to an observation point. At ... 01/11/07 - 20070011542 - Reduced-pin-count-testing architectures for applying test patterns Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed ... 12/28/06 - 20060294443 - On-chip address generation Methods and apparatus for internally generating addresses for use in accessing elements of an integrated circuit (IC) device are provided. In response to detecting a current command, an internal address for use in executing a subsequent command may be generated. By generating the address ahead of time, before the next ... 12/14/06 - 20060282732 - Multi-test method for using compare misr Systems and methods for performing logic built-in-self-tests (LBISTs) where data comparisons are performed in the MISR. In one embodiment, a STUMPS-type LBIST architecture includes scan chains interposed between portions of the functional logic of the logic circuit. Test bit patterns are scanned into the scan chains, propagated through the functional ... 11/23/06 - 20060265632 - Chip capable of testing itself and testing method thereof A chip capable of testing itself and a testing method thereof. The chip capable of testing itself is electrically connected to a processor. The chip tests itself with a testing mode. The chip comprises a first circuit, a pattern generator, a circuit to be tested, and a result generator. The ... 11/16/06 - 20060259842 - Automatic test pattern generation A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From ... 11/09/06 - 20060253759 - 3d fast fault restoration Solutions to the problem of reversing seismic fault movements are formulated using a model based on elasticity theory, and using finite element and boundary element methods for generating a solution. The solution involves defining slip vectors from known formations in the fault and applying a space constraint restriction to traction ... 11/09/06 - 20060253758 - Semiconductor device with test circuit and test method of the same A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test ... 11/09/06 - 20060253757 - Offset test pattern apparatus and method Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern ... 11/02/06 - 20060248424 - Methods and apparatus for incorporating iddq testing into logic bist Built-in self test (BIST) capabilities are expanded to provide IDDQ testing of semiconductor chips. Conventional BIST modules generate vectors from a set of pseudo-random pattern generator (PRPG) values. The pseudo-random vectors generated by the set of PRPG values are simulated, and those vectors best suited for an IDDQ test are ... 11/02/06 - 20060248423 - Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based bist A method and system for built-in self-testing for high-performance circuits, configured to generate and apply a test pattern to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test seeds from a plurality of original test seeds, the ... 10/19/06 - 20060236186 - Test output compaction with improved blocking of unknown values A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to ... 10/19/06 - 20060236185 - Multiple function results using single pattern and method A testing system for testing a manufactured semiconductor component includes a main processor and a pattern generator. The main processor is configured to run a main program. The pattern generator is configured to generate a plurality of functional test patterns, and each test pattern is assembled to test the manufactured ... 09/14/06 - 20060206772 - Method and apparatus for supporting test pattern generation, and computer product In an apparatus for supporting test pattern generation, when an acquiring unit acquires connection information of a target circuit to be tested and an untested path, a detecting unit detects paths between all flip-flop cells in the target circuit to create an untested path list. A path extracting unit extracts ... 09/07/06 - 20060200720 - Generating and verifying read and write cycles in a pci bus system A peripheral device to generate read and write cycles on a PCI bus comprises a PCI bus interface. A control unit has a data pattern generator to source a data pattern to a target via the interface during a write operation and to verify an incoming data pattern from the ... 08/31/06 - 20060195743 - Semiconductor memory device In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to ... 08/24/06 - 20060190793 - Establishing a reference bit in a bit pattern A method establishes a reference bit in a bit pattern. The method includes (a) identifying a series of bit sequences in the bit pattern including all bit sequences having the largest number of consecutive bits with a common logic state and (b) assigning a reference bit based on one bit ... 08/17/06 - 20060184849 - Test pattern generator and test pattern generation method for onboard memory devices A test pattern generator generating a test pattern for performance testing of an onboard memory is provided for a device having a memory macro, a serial input interface, and a latch circuit latching the serial input signal and outputting the result to the memory macro in parallel format. This test ... 08/10/06 - 20060179383 - Extending test sequences to accepting states State spaces are traversed to produce test cases, or test coverage. Test coverage is a test suite of sequences. Accepting states are defined. Expected costs are assigned to the test graph states. Strategies are created providing transitions to states with lower expected costs. Linear programs and other approximations are discussed ... 07/20/06 - 20060161829 - Test apparatus and test method A test apparatus includes: an instruction execution unit for sequentially executing instructions in a test program for a DUT in each instruction cycle; a default pattern memory for storing default pattern sequence to be associated with default pattern identification information for identifying that default pattern sequence, the default pattern sequence ... 07/20/06 - 20060161828 - Digital logic test method to systematically approach functional coverage completely and related apparatus and system A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ... 07/13/06 - 20060156139 - Systems and methods for facilitating testing of integrated circuits Systems and methods for testing integrated circuits (ICs) are provided. In this regard, a representative method involves an IC having a first pad configured as a signal interface for components external to the IC, the first pad having a first receiver configured to receive an input signal from a component ... 07/13/06 - 20060156138 - Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into test pattern generating object blocks and test pattern copying object blocks ... 07/13/06 - 20060156137 - Test program set generation tool A test specification and test program set for a given unit under test and a given automated test equipment platform is generated in an automated manner using information stored in a repository. ... 07/06/06 - 20060150046 - Integrated circuit testing module Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment ... 06/29/06 - 20060143552 - Circuit test pattern edition apparatus, circuit test pattern editing method, and signal-bearing medium embodying a program of circuit test pattern edition An apparatus that edits a test pattern used in a circuit function test includes a generator that generates a regular pattern that includes a plurality of unit patterns, by inserting a redundant pattern into a test pattern, and a pattern number reduction editor that defines the regular pattern as one ... 06/01/06 - 20060117236 - High frequency circuit capable of error detection and correction of code patterns running at full speed A method, an apparatus, and a computer program are provided for generating an error detection state and correction of code patterns. Generally, conducting full speed testing of the dI/dt circuit in a low bandwidth lab environment is difficult. A circuit, however, can be employed that periodically detects the functionality of ... 05/25/06 - 20060112320 - Test pattern compression with pattern-independent design-independent seed compression The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set. ... 05/18/06 - 20060107154 - Through-core self-test with multiple loopbacks An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured ... 05/04/06 - 20060095823 - Test apparatus There is provided a test having a pattern generating section for generating a test pattern, an expected value generating section for generating an expected value, an inversion cycle generating section for generating an expected value pattern of an output signal in which bits in a cycle of the expected value ... 05/04/06 - 20060095822 - Generation of test vectors for testing electronic circuits taking into account of defect probability A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The ... 04/06/06 - 20060075318 - Self verifying communications testing A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a test analyzer, generating a second predetermined data pattern within the test analyzer, and simultaneously transmitting the second test pattern to the device where the second ... 03/30/06 - 20060069975 - Format control circuit and semiconductor test device There is provided a semiconductor test apparatus which assuredly detects an opened edge only which affects a test pattern and truly requires an error warning or the like. This semiconductor test apparatus comprises: a real time selector 40 which receives a plurality of sets of waveform data output from a ... 02/23/06 - 20060041810 - Generating test patterns used in testing semiconductor integrated circuit A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur ... 02/23/06 - 20060041809 - Method for optimizing a pattern generation program, a program, and a signal generator A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, ... 02/23/06 - 20060041808 - Test-pattern generation system, test-pattern analysis system, test-pattern generation method, test-pattern analysis method, and computer product An activation test sequence: 11XX0 with a test sequence ID: 8 is input to an ATPG to generate an activation test sequence: 11000. A propagation test sequence: 11XX1 with a test sequence ID: 8 is input to the ATPG to generate a propagation test sequence: 11011 with a test sequence ... 02/09/06 - 20060031732 - Generating test patterns used in testing semiconductor integrated circuit A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur ... 02/09/06 - 20060031731 - Generating test patterns used in testing semiconductor integrated circuit A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur ... 02/09/06 - 20060031730 - Decision selection and associated learning for computing all solutions in automatic test pattern generation (atpg) and satisfiability An all solutions automatic test pattern generation (ATPG) engine method uses a decision selection heuristic that makes use of the “connectivity of gates” in the circuit in order to obtain a compact solution-set. The “symmetry in search-states” is analyzed using a “Success-Driven Learning” technique which is extended to prune conflict ... 02/02/06 - 20060026480 - Method and apparatus for generating test signals generating the test signal (TS) with the respective signal edges at the allocated instants (TS1U, . . . TSND) and applying the corresponding test signal (TS) to the component (6) to be tested. ... 02/02/06 - 20060026479 - Verification vector creating method, and electronic circuit verifying method using the former method To realize an equivalence verification between an analog circuit and its function model unit. From a circuit topology and a functional description, there is extracted contained in the circuit. A test circuit capable of inputting a verification vector according to the extracted circuit function is created, and a verification is ... 01/26/06 - 20060020865 - Automatic analog test & compensation with built-in pattern generator & analyzer A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone ... 01/19/06 - 20060015788 - Semiconductor device A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test ... 01/12/06 - 20060010360 - Semiconductor testing apparatus and method of testing semiconductor A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test ... 01/05/06 - 20060005095 - Semiconductor integrated circuit and memory test method The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the ... 01/05/06 - 20060005094 - Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured ... 12/29/05 - 20050289426 - Functional pattern logic diagnostic method A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, ... 12/29/05 - 20050289425 - Test pattern generating method, test pattern generating apparatus and storing medium stored with test pattern generating program being readable by computer The present invention is a test pattern generating method. And the test pattern generating method provides a counting step for counting the number of faults becoming undetectable respectively, at each of states 0 and 1 that are able to be given to each of input pins of EOR gates when ... 12/15/05 - 20050278597 - Methods and apparatus for data analysis A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically identify a characteristic of a component fabrication process guided by characteristics of the test data for the components. ... 11/24/05 - 20050262410 - Tool for generating a re-generative functional test A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to ... 11/24/05 - 20050262409 - Smart capture for atpg (automatic test pattern generation) and fault simulation of scan-based integrated circuits A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan ... 11/10/05 - 20050251718 - Method for localization and generation of short critical sequence A method for localization and generation of short critical sequence uses an automatic test equipment to test an electronic device (e.g., memory device) by circuit simulation to localize and re-generate a very short critical sequence from a set of long worst-case pattern. The method includes defining a failure mechanism condition ... 10/27/05 - 20050240851 - Rom-based controller monitor in a memory device A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to ... 10/27/05 - 20050240850 - Multicore processor test method In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently. A processor comprises a plurality of ... 10/20/05 - 20050235188 - Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF fault, wherein the companion fault ... 10/13/05 - 20050229063 - Fault position identification system for a semiconductor device and method of identifying a fault position of a semiconductor device A fault position identification system for a semiconductor device includes: a storage unit storing test data of the semiconductor device; a test result analyzer generating test parameters of the semiconductor device, based on failure information of a failure occurred in the semiconductor device; an emission controller controlling the semiconductor device ... 10/13/05 - 20050229062 - Systems and methods for processing automatically generated test patterns Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of occurrence of linear dependencies associated with compression ... 10/13/05 - 20050229061 - Method of efficiently compressing and decompressing test data using input reduction A new test data compression method and decompression apparatus is invented for SoC (System-on-a-Chip) architecture. The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and input reduction (IR) ... 09/29/05 - 20050216810 - Semiconductor integrated circuit and memory test method The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated ... 09/29/05 - 20050216809 - Memory module with parallel testing Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison ... 09/29/05 - 20050216808 - Method and circuit arrangement for testing electrical modules The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated ... 09/15/05 - 20050204240 - Test data generating system and method to test high-speed actual operation A test data generating system and method to conduct high-speed operation (actual operation) test of an LSI using a tester. The system converts existing simulation data to high-speed operation verifying test data which is formed to obtain a predetermined output expectation value after a clock signal is stopped for a ... 09/15/05 - 20050204239 - Method for testing semiconductor integrated circuit An inventive method is a method for testing a semiconductor integrated circuit that includes a memory circuit provided between a first storage element and a second storage element. The inventive method includes the steps of: (a) initializing the memory circuit; (b) supplying a test pattern to the first storage element; ... 09/01/05 - 20050193304 - Circuit modeling apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may perform operations including selecting a monitor associated with a property of a circuit module, augmenting the circuit module with the monitor to provide an augmented circuit, searching for a test for an output of the augmented circuit to find a ... 09/01/05 - 20050193303 - Implementation of test patterns in automated test equipment An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles ... 07/28/05 - 20050166114 - Single-pass methods for generating test patterns for sequential circuits A single-pass method for generating test patterns for sequential circuits operates upon an iterative array of time-frames representing the circuit. A mapping function is inserted at the end of each time-frame. Fault objects arriving at circuit next-state lines are mapped into good next-state fault objects and are placed onto corresponding ... 07/14/05 - 20050154953 - Multiple function pattern generator and comparator having self-seeding test function A multiple function pattern generator for a serializer/deserializer circuit located on an integrated circuit (IC), comprises a pattern generator in a communications channel, the pattern generator configured to develop a plurality of test patterns and configured to receive the output of the communications channel and user data based on pattern ... 07/07/05 - 20050149804 - Device and method for testing integrated circuit The present invention provides an integrated circuit test device and method which creates a pattern for minimizing a difference from a pattern generated by a pattern generation device. In the invention, a list of all failures assumed to be in the circuit is created, and, for example, a random number ... 07/07/05 - 20050149803 - Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from ... 06/30/05 - 20050144547 - Test pattern generation Apparatus and method for testing a CDMA integrated circuit including a demodulator for correlating input data with one of a set of codes and a test data pattern generator for spreading input test data with one of the set of codes to form a spread test data and providing the ... ### FreshPatents.com Support |