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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Device Response Compared To Input Pattern Device Response Compared To Input PatternDevice Response Compared To Input Pattern patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/11/07 - 20070240026 - method evaluating threshold level of a data cell in a memory device A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; ... 08/23/07 - 20070198885 - Semiconductor integrated circuit and test system for testing the same A semiconductor integrated circuit includes a pin section, internal circuits, an interface section, an expectation value generation circuit, a comparison circuit and a waveform generation circuit. In a first test mode, the expectation value generation circuit generates expectation values of operation signals to be generated by the interface section when ... 07/26/07 - 20070174751 - Method of using virtual inputs and outputs to automate testing of application software and hardware The invention relates to automated hardware in the loop testing. A method of automated diagnostic testing is described as monitoring, modifying, overwriting, providing and/or providing read-only access to input data given to a tested application and output data provided by a tested application to compare a desired relationship between input ... 06/07/07 - 20070130491 - Error detection of digital logic circuits using hierarchical neural networks An artificial neural network for detecting and identifying errors in digital circuits is provided. Data from digital circuits are received and organized into current data set patterns by a supervisory control and data acquisition system. The supervisory control and data acquisition system transmits the current data set patterns to an ... 01/25/07 - 20070022348 - Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core ... 01/25/07 - 20070022347 - Systems, methods and computer programs for calibrating an automated circuit test system In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A ... 01/11/07 - 20070011540 - Telecommunications network testing On a test apparatus for a telecommunication network a plurality of quality rules are defined as a function of the results of counts of events for a plurality of test parameters. The events relating to the plurality of test parameters during the performance of a test are counted. A plurality ... 08/24/06 - 20060190791 - Enabling special modes within a digital device A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test ... 07/13/06 - 20060156135 - Tabbed form with error indicators An improved graphical user interface having a tab feature. In addition to conventional tabs, each one containing a specific field to be filled, an image is added to all tab captions to indicate if each tab is correctly filled. If the tab is not correctly filled, there is an error ... 01/05/06 - 20060005093 - Comparator for circuit testing There is provided a test circuit comprising a test signal input for receiving a test signal, a hysteretic comparator having first and second comparison inputs and an output indicating the result of the comparison, and a delay circuit. The first comparison input is connected to the test signal input and ... 12/08/05 - 20050273684 - Timing generator and semiconductor testing device Pattern-dependent jitters are reduced, and timing errors of timing pulse signals are decreased in a timing generator. In a timing generator 20, a delaying circuit (variable delaying means, clock signal delaying circuit) 32 is disposed on an input terminal side of a clock signal, not an output terminal side of ... 10/27/05 - 20050240849 - Method of testing apparatus having master logic unit and slave logic unit An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual ... 07/28/05 - 20050166112 - Method and system for efficiently verifying optical proximity correction A method of verifying optical proximity correction includes the steps of generating first mask pattern data from design data under first condition, generating first corrected pattern data by applying optical proximity correction to the first mask pattern data, generating second mask pattern data from the design data under second condition, ... 07/14/05 - 20050154952 - Apparatus for fault detection for parallelly transmitted audio signals and apparatus for delay difference detection and adjustment for parallelly transmitted audio signals Characteristic amounts in each small region of audio signals transmitted in the working system and the standby system are extracted by characteristic amount calculators 6-1, 6-2. A characteristic amount comparator 7 compares the characteristic amounts and judges occurrence of a fault. Characteristic amount difference calculators 9-1, 9-2, ∥D∥ comparator 10, ... 06/30/05 - 20050144546 - Semiconductor integrated circuit and evaluation method of wiring in the same An input circuit writes an expected value to one end of an evaluation wiring. A latch circuit latches a logic level of the other end of the evaluation wiring. A first switch circuit connects an output of the input circuit to the input of the latch circuit. A second switch ... ### FreshPatents.com Support |