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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Built-in Testing Circuit (bilbo) Built-in Testing Circuit (bilbo)Built-in Testing Circuit (bilbo) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070260954 - Integrated circuit with low-power built-in self-test logic An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational logic of the IC-LPBIST, wherein the shift test pattern of data is ... 11/01/07 - 20070255991 - Monitoring a thermal processing system A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table to detect, diagnose and/or predict fault conditions and/or degraded performance. The method includes positioning a plurality of wafers in a processing chamber in the thermal processing system, performing a self test process, determining ... 10/18/07 - 20070245195 - Method, system and program product for boundary i/o testing employing a logic built-in self-test of an integrated circuit A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being ... 10/11/07 - 20070240025 - Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's ... 10/04/07 - 20070234159 - Method and apparatus for testing a ring of non-scan latches with logic built-in self-test A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable ... 09/27/07 - 20070226568 - Semiconductor integrated circuit and design apparatus thereof According to the present invention, there is provided a semiconductor integrated circuit comprising: a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates ... 09/27/07 - 20070226567 - High speed bist utilizing clock multiplication A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester, comprising: a built-in self test (BIST) engine coupled to the integrated circuit; a clock multiplier adapted to derive a ... 09/20/07 - 20070220389 - Integrated circuit device, diagnosis method and diagnosis circuit for the same A logical circuit 18 and a self-diagnosis circuit 22 are mounted on an LSI 10. When a test program is loaded to a RAM 28 and a diagnosis command is input to a CPU 26 before shipment, a pattern generation circuit 24 generates a pattern and expected value pattern data ... 08/30/07 - 20070204193 - Microcontroller for logic built-in self test (lbist) Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store ... 07/19/07 - 20070168809 - Systems and methods for lbist testing using commonly controlled lbist satellites Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different functional blocks of the device under test, such as processor cores in a multiprocessor integrated circuit. Because the data paths for each satellite are ... 07/05/07 - 20070157059 - Apparatus and method for integrated functional built-in self test for an asic We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips. ... 06/07/07 - 20070130489 - Systems and methods for lbist testing using isolatable scan chains Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed ... 05/24/07 - 20070118784 - Self test circuit for a semiconductor intergrated circuit A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. ... 05/24/07 - 20070118783 - Runtime reconfiguration of reconfigurable circuits A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein. ... 04/19/07 - 20070089004 - Method and apparatus for accelerating through-the pins lbist simulation The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock ... 04/05/07 - 20070079203 - Testing a multibank memory module A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of integrated circuit (IC) devices for storing data and the IC devices have a plurality of control lines coupled thereto. A first ... 04/05/07 - 20070079202 - Integrated circuit arrangement and method of operating such a circuit arrangement An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at ... 04/05/07 - 20070079201 - Power-saving apparatus according to the operating mode of an embedded memory A power-saving apparatus according to the operating mode of an embedded memory is provided for solving the problems of the prior art, such as the embedded memory only being able to reduce power consumption in a normal operating mode and being unable to save power in other operating modes. The ... 04/05/07 - 20070079200 - Input-output device testing Integrated circuit test circuits may include at least an instruction processor and input-output subsystems. Input-output subsystems are segmented together into input-output subsystem segments. Each input-output subsystem includes an analog wrapper circuit (IW-A) operable to connect an input-output port to analog buses and further operable to isolate the input-output port from ... 04/05/07 - 20070079199 - User data driven test control software application that requires no software maintenance Methods and apparatus for performing a data driven test on a circuit including at least one built-in-self-test compatible device. In one embodiment, the method includes describing the device using a descriptive language including setting at least one default value associated with the device. The method also includes defining a scan ... 04/05/07 - 20070079198 - Semiconductor integrated circuit apparatus and interface test method An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an ... 04/05/07 - 20070079197 - Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty ... 03/22/07 - 20070067689 - In-circuit testing system and method An in-circuit testing system comprises an integrated circuit having a tri-state control pin used for inducing a tri-state mode in the integrated circuit during a scan test of the integrated circuit for controlling a time period for outputting a value associated with the scan test. ... 03/22/07 - 20070067688 - Method and system for selectively masking test responses An apparatus for testing an integrated circuit (10) that comprises a compactor (22) to compress test responses from a circuit-under-test (14) that is part of an integrated circuit (10), and masking circuitry (18) coupled between the circuit-under-rest and the compactor (22) for masking one or more of the test responses ... 03/15/07 - 20070061654 - Semiconductor integrated circuit and test method A semiconductor integrated circuit includes a memory that operates in synchronization with a first clock and a built-in self-test (BIST) circuit for testing the memory. The BIST circuit includes a test data output circuit for outputting test data as input test data to the memory in synchronization with a second ... 03/15/07 - 20070061653 - Built-in self-repairable memory The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number of fuses to actually make a repair ... 03/15/07 - 20070061652 - Built-in self test for a thermal processing system A method of creating and/or modifying a built-in self test (BIST) table for monitoring a thermal processing system in real-time that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response; creating a ... 03/01/07 - 20070050693 - Systems and methods for diagnosing rate dependent errors using lbist Systems and methods for performing logic built-in self-tests (LBISTs) to detect “at-speed” errors in a digital circuit. In one embodiment, an input bit pattern is propagated through target logic of the digital circuit and captured in scan chains at a normal operating speed to produce a first output bit pattern. ... 02/08/07 - 20070033472 - Vlct programmation/read protocol An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. ... 02/08/07 - 20070033471 - Hardware configuration of pbist This invention is a method of constructing an integrated circuit with built-in self test. The built-in self test includes a built-in self test unit a read only memory storing test algorithms and test data. The built-in self test unit of a particular integrated circuit includes a subset of all test ... 02/08/07 - 20070033470 - Emulation cache access for tag view reads A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. ... 02/08/07 - 20070033469 - Rom-based memory testing This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration ... 02/08/07 - 20070033468 - System, apparatus and method of improving logical built-in self test (lbist) ac fault isolations A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged ... 01/11/07 - 20070011539 - Self test structure for interconnect and logic element testing in programmable devices A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and ... 01/11/07 - 20070011538 - Circuit and method for performing built-in self test and computer readable recording medium for storing program thereof A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple ... 01/11/07 - 20070011537 - Systems and methods for self-diagnosing lbist Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits. In one embodiment, a system has first and second target logic, each of which has LBIST circuitry incorporated therein. The system also includes comparison circuitry which is coupled to the first and second LBIST circuitry. The comparison circuitry ... 01/11/07 - 20070011536 - Automated bist execution scheme for a link Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, ... 01/11/07 - 20070011535 - Semiconductor integrated circuit A semiconductor integrated circuit includes a plurality of memories; a BIST circuit configured to test at least one of the memories; and a plurality of shift circuits connected to each of the memories, each of the shift circuits shifts one of first data bits obtained from at least one of ... 12/28/06 - 20060294442 - Bist to provide phase interpolator data and associated methods of operation In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to under-sample the PI output clock signal from the signal source. In a method of operation, a PI output clock signal is ... 11/16/06 - 20060259841 - Relocatable built-in self test (bist) elements for relocatable mixed-signal elements An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused ... 11/16/06 - 20060259840 - Self-test circuitry to determine minimum operating voltage A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test ... 11/02/06 - 20060248422 - Sequential scan based techniques to test interface between modules designed to operate at different frequencies According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at ... 10/26/06 - 20060242521 - Built-in self-test arrangement for integrated circuit memory devices An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the ... 10/26/06 - 20060242520 - Adapting scan-bist architectures for low power operation A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan ... 10/26/06 - 20060242519 - Multiple uses for bist test latches A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though, ... 10/19/06 - 20060236181 - Systems and methods for lbist testing using multiple functional subphases Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between ... 09/21/06 - 20060212768 - Verification circuitry for master-slave system Operation of a system including master and slave devices is verified through the use of system verification circuitry including a test master circuit that outputs test patterns on the system bus to emulate the operation of all master devices in the system, a built-in self-test and memory circuit that stores ... 09/14/06 - 20060206771 - Read-only memory and operational control method thereof A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area ... 08/31/06 - 20060195742 - Semiconductor memory device and method of testing the same A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test ... 08/24/06 - 20060190789 - Synchronization point across different memory bist controllers A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates ... 08/24/06 - 20060190788 - Method and apparatus for verifying memory testing software A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. ... 08/10/06 - 20060179378 - Semiconductor integrated circuit and method of testing the same In this semiconductor integrated circuit, outputs of a fuse for power supply level adjustment and an internal register are selectively switched by a selector, and a selected output is inputted to a reference voltage generating circuit. Hence, the same reference voltage can be generated before and after blowing the fuse. ... 08/10/06 - 20060179377 - Abist data compression and serialization for memory built-in self test of sram with redundancy A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the ... 07/27/06 - 20060168491 - Automated tests for built-in self test A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the ... 07/13/06 - 20060156134 - Programmable memory built-in-self-test (mbist) method and apparatus Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... 07/13/06 - 20060156133 - Flexible memory built-in-self-test (mbist) method and apparatus Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... 07/13/06 - 20060156132 - Semiconductor device with built-in scan test circuit The clock cycle during the shift operation is set shorter than the clock cycle during the capture operation in the scan test circuit. For example, the clock cycle during the shift operation is set to 20 nano second, while the clock cycle during the capture operation is set to 100 ... 07/13/06 - 20060156131 - Method of reducing hardware overhead upon generation of test pattern in built-in sef test A method of reducing hardware overhead upon the generation of a test pattern in a built-in self test is introduced, in which two pieces of hardware perform a lot of functions even prior to generation of deterministic patterns, thereby reducing the amount of hardware required for conventional pseudo-random pattern generation ... 07/13/06 - 20060156130 - Self test method and apparatus for identifying partially defective memory A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the ... 06/08/06 - 20060123298 - Pci express physical layer built-in self test architecture A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern ... 06/01/06 - 20060117235 - System and method for conducting bist operations Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit ... 05/18/06 - 20060107151 - Automatic fault-testing of logic blocks using internal at-speed logic-bist System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The ... 05/18/06 - 20060107150 - Semiconductor device and test method thereof A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same ... 05/18/06 - 20060107149 - Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's ... 05/18/06 - 20060107148 - Automatic self-testing of an internal device in a closed system A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from an external device. In addition, a closed system including automatic, ... 05/04/06 - 20060095820 - Method, system, and program product for boundary i/o testing employing a logic built-in self-test of an integrated circuit A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being ... 04/13/06 - 20060080585 - Systems and methods for circuit testing using lbist Systems and methods for performing logic built-in-self-tests (LBISTS) in digital circuits. In one embodiment, the operation of LBIST circuitry is suspended at the end of each test cycle so that the bit patterns generated by the functional logic of the device under test can be examined to determine if any ... 04/13/06 - 20060080584 - Built-in self-test system and method for an integrated circuit An integrated circuit comprises random logic communicatively coupled to a non-scannable memory array. The integrated circuit also comprises a built-in self-test (BIST) controller adapted to apply test data to the random logic and propagate the test data through the random logic to test the memory array. ... 03/23/06 - 20060064618 - Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based ... 03/09/06 - 20060053356 - Integrated circuit An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a parallel access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block ... 03/02/06 - 20060048031 - Built-in self test for memory arrays using error correction coding A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test ... 03/02/06 - 20060048030 - Eye width characterization mechanism An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from the pass setting until the sampling phase is outside the eye width of the received data. The sampling phase ... 02/23/06 - 20060041807 - Integrated circuit An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a serial access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block ... 02/16/06 - 20060036920 - Built-in self-test (bist) for high performance circuits Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that ... 02/09/06 - 20060031729 - Apparatus with self-test circuit An apparatus is adapted for self-test. The apparatus includes a microcontroller and a number of relay drivers having outputs electrically connected to form a single input for self-test monitoring. The microcontroller is electrically connected to each of the relay drivers and is adapted to energize each of the relay drivers ... 02/02/06 - 20060026478 - Built-in self-test emulator Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST ... 12/29/05 - 20050289424 - Error correction in rom embedded dram Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM). ... 12/29/05 - 20050289423 - Built-in self test systems and methods for multiple memories A built-in self-test architecture for multiple memories in a chip is proposes in the present invention. In this architecture, a memory testing circuit includes a data generator for generating expected-value data, registers connected in parallel to a plurality of memories respectively so as to be able to transfer, in parallel, ... 12/22/05 - 20050283694 - Built-in-test diagnostic and maintenance support system and process A diagnostic and maintenance support system and process to that performs tests on systems, collects Built-In-Test (BIT) log data, analyzes fault data, and recommends Shop Replaceable Units (SRUs). The system hardware may include a computer, an interface test adapter, and a cable set. A process performs a Discrete Fault Mask ... 12/15/05 - 20050278595 - Built-in self test circuit and test method for storage device A built-in self test circuit includes a capture register storing data transmitted from a memory device, an operation controller controlling operation of the memory device and the capture register, a hold controller executing a hold operation to stop a read operation and a write operation of the memory device by ... 12/01/05 - 20050268194 - Method and apparatus for multi-level scan compression A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising ... 11/17/05 - 20050257109 - Built-in self-test (bist) architecture having distributed interpretation and generalized command protocol A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without ... 11/10/05 - 20050251714 - Test apparatus for semiconductor devices built-in self-test function A test apparatus for semiconductor devices comprises a self-test circuit carried on the semiconductor device and for test the semiconductor device. A tester supplies data signals, clock signals, and expected value data to the self-test circuit. A comparing and judging circuit compares the result of test with the expected-value data ... 11/03/05 - 20050246602 - On-chip and at-speed tester for testing and characterization of different types of memories An on-chip and at-speed testerfor testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for ... 10/20/05 - 20050235187 - Apparatus and method for testing motherboard having pci express devices This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from ... 10/13/05 - 20050229060 - Method and apparatus for detecting array degradation and logic degradation A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including, for example, application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine is provided. At least one monitor element is coupled to the MBIST engine and is defined ... 09/22/05 - 20050210352 - Method and apparatus for embedded built-in self-test (bist) of electronic circuits and systems An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST ... 09/22/05 - 20050210351 - Test circuit and circuit test method The test circuit tests a test target circuit and outputs a test result to a tester. The test circuit includes a first clock generator, a second clock generator, a test target circuit, a BIST circuit for performing the test, and a tester synchronous circuit. The BIST circuit repeats the test ... 09/15/05 - 20050204235 - Automatic method and system for instantiating built-in-test (bist) modules in asic memory designs A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method ... 09/15/05 - 20050204234 - Method and apparatus for the memory self-test of embedded memories in semiconductor chips Method for the memory self-test of embedded memories (2, 3, 4) in semiconductor chips (1), a memory address range (8) being assigned to a memory (2) to be tested and addresses from the same memory address range of the memory to be tested being allocated to at least one memory ... 09/15/05 - 20050204233 - System-on-chip (soc) having built-in-self-test circuits and a self-test method of the soc A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response ... 09/15/05 - 20050204232 - Technique for combining scan test and memory built-in self test Semiconductor devices including logic circuitry and embedded memories may be more efficiently tested in that one or more flip-flops in a scan chain are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. ... 09/15/05 - 20050204231 - Testing memories using algorithm selection A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit is disclosed. In a specific example, a determination is made during running of a BIST whether one or more algorithms are to be run. If any algorithm is not designated for running, the particular ... 09/01/05 - 20050193302 - Test switching circuit for a high speed data interface Test switching circuit for a high speed data interface (1) of an integrated circuit comprising switching transistors (T1-T6) which switch in a test mode a termination resistor output stage (15) of a data transmission signal path (17) to a termination resistor input stage (18) of a data reception signal path ... 08/25/05 - 20050188290 - Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of ... 08/25/05 - 20050188289 - Method for system performance testing and self correcting action Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrated circuit device throughout the integrated circuit devices useful life. The invention also evaluates whether results from ... 08/04/05 - 20050172194 - Remote bist high speed test and redundancy calculation Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction ... 07/28/05 - 20050166111 - Memory built-in self test circuit with full error mapping capability A new built-in self-test circuit device for testing an embedded memory array is achieved. The device comprises a pattern generator unit that executes a testing sequence to automatically write and read locations in an embedded memory. A comparison unit compares data read from the embedded memory and expected data provided ... 07/21/05 - 20050160339 - Automated bist test pattern sequence generator software system and method Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Rather than store the entire set of test parameters for each of a plurality of test sequences to be performed, ... 07/21/05 - 20050160338 - Integrated circuit with test circuit Integrated circuit with an application circuit (1) to be tested, and a self-test circuit (5-16) which is provided for testing the application circuit (1) and comprises an arrangement (5-9) for generating desired test patterns which are applied to the application circuit (1) for test purposes, wherein the output signals occurring ... 07/14/05 - 20050154951 - Saving self-test output to both flash and media A hard disk drive includes a flash memory and a rotatable disk. During self-test, self-test data is written first to flash and then later written to the rotatable disk. Since the self-test data is stored in the flash, if there is a power failure the hard disk drive can recover ... 07/14/05 - 20050154950 - Method for saving self-test output to both flash and media A hard disk drive includes a flash memory and a rotatable disk. During self-test, self-test data is written first to flash and then later written to the rotatable disk. Since the self-test data is stored in the flash, if there is a power failure the hard disk drive can recover ... 06/23/05 - 20050138514 - Abist-assisted detection of scan chain defects An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by ... 06/23/05 - 20050138513 - Multiple on-chip test runs and repairs for memories A structure and method for performing on-chip test runs and repairs of a memory chip. In the first test run and repair, a BIST circuit obtains the original combined repair solution from a fuse bay on the memory chip, runs the first test run for the memory chip, obtains a ... ### FreshPatents.com Support |