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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) > Clock Or Synchronization Clock Or SynchronizationClock Or Synchronization patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266286 - Test semiconductor device in full frequency with half frequency tester An integrated circuit includes a double frequency clock generator and a double input generator to test semiconductor devices at full frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock signals and test data signals at a normal rate (1× mode) ... 11/15/07 - 20070266285 - Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock ... 11/01/07 - 20070255990 - Test access port switch A Test Access Port (TAP) switch provides a centralized serial test interface between an electronic system and a resource external to the electronic system. The electronic system includes the TAP switch and a plurality of electronic circuit components, each electronic circuit component having a TAP coupled to the TAP switch. ... 09/20/07 - 20070220388 - Apparatus and method for adjusting an operating parameter of an integrated circuit A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter ... 09/20/07 - 20070220387 - Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The ... 09/06/07 - 20070208982 - Semiconductor device A semiconductor integrated circuit apparatus of the present invention includes a periodical signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodical signal. The periodic signal generation circuit includes a reset circuit outputting a reset signal initializing according to outputs from a ... 09/06/07 - 20070208981 - Systems, devices, and methods for arc fault detection Certain exemplary embodiments comprise a system that comprises an application specific integrated circuit configured to provide an output signal. The output signal can be configured to trip a device in an electrical circuit responsive to a detected fault. The application specific integrated circuit can comprise a temperature sensor. The application ... 09/06/07 - 20070208979 - Split clock scan flip-flop A split clock flip-flop (SC-SFF) includes a latch having a scan input terminal, a data input terminal, a clock input terminal and at least one output terminal for generating an output signal in response to a scan input signal received at the scan input terminal or a data input signal ... 07/19/07 - 20070168808 - Integrated circuit testing module including data compression Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is ... 07/19/07 - 20070168807 - Start/stop circuit for performance counter A circuit for tracking a number of clock cycles between occurrences of an event of interest is described. The circuit comprises logic for asserting a run signal responsive to a first occurrence of the event of interest; logic for deasserting the run signal responsive to a second occurrence of the ... 05/31/07 - 20070124636 - Phase synchronization for wide area integrated circuits A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of ... 05/31/07 - 20070124635 - Integration circuit and test method of the same An object of the present invention is to realize an at-speed test on a latch-to-latch path (a cross domain path) between different clock domains. In order to achieve the object, the present invention provides an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates ... 05/31/07 - 20070124634 - Test circuit, method and apparatus for supporting circuit design, and computer product A first FF outputs a first signal. A second FF captures the first signal and outputs a second signal. Each of the first and the second FF has a clock terminal to capture a clock signal. A third FF captures the first signal in parallel with the second FF. The ... 05/17/07 - 20070113132 - Method and device for verifying timing in a semiconductor integrated circuit A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a coefficient of variation for each cell based on conditions of the manufacturing process of a semiconductor integrated circuit. The timing verification device receives a ... 05/03/07 - 20070101224 - Circuit for generating data strobe signal in ddr memory device, and method therefor The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input ... 05/03/07 - 20070101223 - Electronic test apparatus and method for testing at least one circuit unit An electronic test apparatus for testing at least one circuit unit comprises a clock signal generator for generating a clock signal, a driver device comprising a plurality of driver subunits each generating a phase-shifted driver signal in response to said clock signal, a processing device for processing the phase-shifted driver ... 04/05/07 - 20070079196 - Information terminal device Detection as to the reproduction expiration time of contents is executed, using the measured time of a system clock managed based on system time data from a base station BS. If the reproduction expiration time of the contents is not exceeded, the contents can be reproduced, whereas if it is ... 04/05/07 - 20070079195 - Time-series data analyzing apparatus A time-series data analyzing apparatus which extracts a composite factor time-series pattern from time-series data. The apparatus includes a dividing device which divides the time-series data into pattern generation time-series data and pattern inspection time-series data which do not include pattern generation time-series data. A first generating device generates a ... 04/05/07 - 20070079194 - Apparatus and method for controlling frequency of an i/o clock for an integrated circuit during test A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core ... 03/22/07 - 20070067687 - Integrated circuit testing module configured for set-up and hold time testing Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating ... 03/22/07 - 20070067686 - Method and apparatus for testing an integrated device's input/output (i/o) A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for delay cells in strobe pads and a clock generation that facilitates varying the duty cycle for ... 03/15/07 - 20070061651 - Shift register circuit A shift register circuit which having a plurality of stages, a signal of the timing controller is conveyed to the shift register circuit for generating and transferring a sample signal to data latch circuit. The first stage of the shift register, comprising a disable circuit and a sample circuit, receives ... 03/15/07 - 20070061650 - Semiconductor device with test interface A semiconductor device with test interface, as well as to a method for operating a semiconductor device is disclosed. In one embodiment, in a test operating mode, the semiconductor device is, via a first pin, supplied with a work cycle signal synchronized with a test environment and, via at least ... 03/15/07 - 20070061649 - Semiconductor devices including test circuits and related methods of testing A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control ... 03/15/07 - 20070061648 - Shift register, scanning line driving circuit, matrix type device, electro-optic device, and electronic device The invention provides a shifter register comprising: a plurality of shift circuit blocks connected in series, each of which includes a predetermined even-number of shift unit circuits; a plurality of clock decision circuit, each of which is provided for each of a plurality of the shift circuit blocks and receives ... 02/22/07 - 20070043991 - Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable ... 02/22/07 - 20070043990 - Providing precise timing control within a standardized test instrumentation chassis Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system ... 02/08/07 - 20070033466 - Method and apparatus for handling of clock information in serial link ports A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a ... 02/08/07 - 20070033465 - Apparatus and method for a single wire interface between a intergated circuit and jtag test and emulation apparatus A single conducting path provides communication between a JTAG unit and a JTAG TAP controller. The data is communicated between the two units using time-division multiplexing. Three time slots are allocated to data-in, to data-out and to JTAG control signals. Two of the time-division multiplexing slots exchange data by having ... 02/08/07 - 20070033464 - Efficient clocking scheme for ultra high-speed systems There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the ... 01/25/07 - 20070022344 - Digital storage element architecture comprising dual scan clocks and gated scan output A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional ... 01/11/07 - 20070011532 - Semiconductor chip and semiconductor integrated circuit device A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to ... 01/11/07 - 20070011531 - Methods and apparatus for managing clock skew between clock domain boundaries Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the given stage of combinational logic to a next of ... 12/14/06 - 20060282731 - Semiconductor integrated circuit and method of testing same A semiconductor integrated circuit includes an MISR (Multiple-Input Signature Register) for generating and storing compressed code based upon code from a ROM, and for reading out and outputting the compressed data that has been stored. The MISR has a clock change-over unit for changing over a clock in such a ... 11/16/06 - 20060259839 - Method and system for evaluating a constraint of a sequential cell The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the ramp of a second signal. The method includes a characterization phase including a first ... 11/02/06 - 20060248421 - Scan driver, organic light emitting display using the same, and method of driving the organic light emitting display A scan driver capable of freely setting the width of emission control signals and of dividing the emission control signals at least twice in one frame to apply the emission control signals is disclosed. Embodiments of the scan driver include a shift register, receiving at least two start pulses in ... 10/26/06 - 20060242517 - Monitoring a data processor to detect abnormal operation Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or ... 10/26/06 - 20060242516 - Methods and systems for generating an accurate adaptive clock A method for generating an accurate adaptive clock is disclosed. The method includes accessing data at a first clock rate, generating an adaptive clock that has an adaptive clock rate that is based on the arrival rate of said data, accessing data related to the first clock rate and the ... 10/19/06 - 20060236180 - Integrated circuit testing module including command driver Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment ... 09/21/06 - 20060212767 - Production plant A production plant having a number of machine tools, a number of tools/instruments, and a computer system having a number of first memory cells containing work cycle descriptions, a number of second memory cells containing operation descriptions, a number of third memory cells containing step descriptions, a number of fourth ... 08/31/06 - 20060195741 - Shift clock generator, timing generator and test apparatus There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect ... 08/31/06 - 20060195740 - Clock duty cycle based access timer combined with standard stage clocked output register An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. ... 08/24/06 - 20060190787 - Target system, debugging system, integrated circuit device, microcomputer and electronic apparatus A debugging system that includes a debugging tool in a small pin count package and a target system that is a debugging object of the debugging tool, wherein the substrate of the target system includes an integrated circuit device with a built-in CPU and a communicator for generating and outputting ... 08/10/06 - 20060179376 - Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional ... 08/10/06 - 20060179375 - Split l2 latch with glitch free programmable delay A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the ... 07/13/06 - 20060156126 - Semiconductor test instrument Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator ... 07/06/06 - 20060150043 - Method for clock synchronization validation in integrated circuit design Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains. ... 07/06/06 - 20060150042 - Testing of electronic circuits A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information ... 06/08/06 - 20060123297 - Automatic test system with synchronized instruments A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately ... 06/08/06 - 20060123296 - Instrument with interface for synchronization in automatic test equipment A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately ... 05/18/06 - 20060107147 - Semiconductor device with timing correction circuit A semiconductor device includes a timing correction circuit coupled to an external terminal for receiving an input data signal to change a relative timing between the input data signal and an internal clock signal to generate a plurality of relative latch timings to latch one of the input data signal ... 04/27/06 - 20060090111 - Circuit for recursively calculating data The invention relates to a circuit for calculating a second data set based on a first data set calculated by at least a calculation device (31) that is capable of calculating a data in a predefined number of clock cycles. The calculation device has an input (311) and an output ... 04/20/06 - 20060085711 - Memory test circuit and method To test memories operating with different operational clocks and deal with a delay involved in testing a memory at a physically remote location. A memory test circuit of the present invention tests a processor core memory and a function-specific core memory with a processor core, and includes a clock selector ... 03/23/06 - 20060064617 - Internal clock generator An internal clock generator comprises delay units adapted and configured to delay a first clock outputted from a clock buffer for predetermined delay times to output a plurality of second clocks, respectively, clock pulse generating units adapted and configured to generate clock pulses depending on the plurality of second clocks, ... 12/15/05 - 20050278594 - Semiconductor memory device having ecc circuit A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wiring intervals as bit ... 07/07/05 - 20050149801 - Semiconductor test device A recovery clock synchronized with an internal clock faster than a system clock is obtained with an edge timing of the system clock output from a DUT. The present invention is configured to comprise: a time interpolator 20 which includes flip-flops 21a to 21n which receive system clocks of the ... ### FreshPatents.com Support |