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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) > Plural Scan Paths Plural Scan PathsPlural Scan Paths patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/27/07 - 20070226564 - Efficient scan chain insertion using broadcast scan for reduced bit collisions Disclosed is a method of inserting scan elements onto scan chains of broadcast scan structures to minimize the number of collisions in a plurality of logic cones. Each logic cone is selected and evaluated to identify all of the scan elements that provide inputs thereto. The identified scan elements are ... 05/24/07 - 20070118782 - Removable and replaceable tap domain selection circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore ... 10/26/06 - 20060242515 - Systematic scan reconfiguration Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for ... 07/13/06 - 20060156125 - Shift register system, method and driving circuit An exemplary shift register system (31) includes a shift register (311), and four switches (312-315). The shift register includes input pins, output pins, a start pin, a reset pin, a first controlling pin, and a second controlling pin. Each switch includes input pins according to the output pins of the ... ### FreshPatents.com Support |