REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) > Random Pattern Generation (includes Pseudorandom Pattern) Random Pattern Generation (includes Pseudorandom Pattern)Random Pattern Generation (includes Pseudorandom Pattern) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070255989 - Systems, methods and apparatus for synthesizing state events for a test data stream In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state events; B) upon accessing one of the data events, determining if the ... 10/04/07 - 20070234157 - Multi-stage test response compactors Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about ... 10/04/07 - 20070234156 - Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit An electronic circuit includes configurable cells with a test input and an output. The configurable cells are capable of being connected to one another in a chain in a predefined order via the test inputs and the outputs to form a test shift register if they receive a chaining command ... 09/13/07 - 20070214398 - Electronic device testing system A method and system for testing an electronic device is disclosed. The method includes loading a first test into a test pattern generator of a first device and generating a first test pattern at the test pattern generator. A second test seed is loaded into the test pattern generator while ... 09/06/07 - 20070208978 - Dvi link with circuit and method for test An embodiment includes encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a ... 09/06/07 - 20070208977 - Methods and apparatus for error injection In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is ... 07/12/07 - 20070162806 - Random number test circuit The random number test circuit includes a shift register which operates based on a clock and which successively stores serial random numbers generated by a random number generation element, a first random number being output from a predetermined stage of the shift register; a comparison circuit which compares the first ... 01/18/07 - 20070016836 - Test pattern compression for an integrated circuit test environment A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the ... 01/11/07 - 20070011530 - Decompressor/prpg for applying pseudo-random and deterministic test patterns A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under ... 11/09/06 - 20060253756 - Semi-conductor component test device with shift register, and semi-conductor component test procedure The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at ... 04/20/06 - 20060085710 - Testing memories Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, ... 02/02/06 - 20060026474 - System and program product for displaying error handling information When an emission pattern of LEDs of an operation panel of a printer is merely pseudo-displayed on display portions of a local computer and a server computer, a piece of error handling information corresponding to a pseudo pattern of the emission pattern can be acquired. Accordingly, a user can easily ... 10/20/05 - 20050235186 - Multiple-capture dft system for scan-based integrated circuits A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The ... 08/04/05 - 20050172193 - Tap time division multiplexing An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions ... 07/28/05 - 20050166110 - Generation of memory test patterns for dll calibration A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate ... ### FreshPatents.com Support |