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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) > Boundary Scan Boundary ScanBoundary Scan patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266284 - System and method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device A system and method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two ... 11/08/07 - 20070260953 - Scan test An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated ... 10/04/07 - 20070234155 - Probeless testing of pad buffers on wafer The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. ... 10/04/07 - 20070234154 - Scan testing using scan frames with embedded commands Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan ... 09/27/07 - 20070226563 - Test method and test device for testing an integrated circuit A test method and a test device for testing an integrated circuit are configured to allow for a test device which dispenses with the hardware provision of the boundary scan cells in the device. For this purpose, the boundary scan cells are reproduced by way of a boundary scan program. ... 09/06/07 - 20070208976 - Low overhead input and output boundary scan cells A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic ... 09/06/07 - 20070208975 - Parallel architecture for low power linear feedback shift registers The present invention provides an apparatus and method for implementing low-power linear feedback shift registers (LFSR) that efficiently produce single or multiple outputs. In one case of single output generation the gates are permanently connected to the respective flip-flops reducing the number of switches necessary. In the case of multiple ... 08/02/07 - 20070180341 - Tap and linking module for scan access of multiple cores with ieee 1149.1 test access ports An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response ... 07/26/07 - 20070174749 - Diagnostics unit using boundary scan techniques for vehicles A test system including a diagnostics unit comprising a plurality of diagnostics-unit interfaces to communicatively couple the diagnostic unit to a plurality of units under test and a unit diagnostic communication port via which a unit diagnostic control device is communicatively coupled to the diagnostics unit. Each unit under test ... 07/26/07 - 20070174748 - Method and system for backplane testing using generic boundary-scan units A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively couple the adapter assembly to an application-specific port of a backplane and an adapter generic connector. The generic boundary-scan test unit includes a ... 07/19/07 - 20070168806 - Scan path circuit and semiconductor integrated circuit comprising the scan path circuit Each of D flip-flops (FFs) 13a to 13f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply ... 07/05/07 - 20070157058 - Interconnect delay fault test controller and test apparatus using the same An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores ... 05/24/07 - 20070118781 - Organic electroluminescent display device An organic electroluminescent display device employing a demultiplexer to reduce the number of output lines of a data driver. The display device uses the demultiplexer to store a data voltage in a data line, and supplies the stored data voltage to a pixel when a scan signal is applied, thereby ... 05/03/07 - 20070101222 - Shift registers free of timing race boundary scan registers with two-phase clock control A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. The two-phase clock generator locally generates ... 01/25/07 - 20070022343 - Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on ... 01/25/07 - 20070022342 - Parallel test mode for multi-core processors An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a ... 01/18/07 - 20070016835 - Method and apparatus for parameter adjustment, testing, and configuration A method and apparatus for parameter monitoring, adjustment, testing, and/or configuration of devices have been disclosed. ... 01/11/07 - 20070011529 - Semiconductor device and test method thereof An LSI has bidirectional buffers connected to a boundary scan circuit. The boundary scan circuit 12 has asynchronous setting circuits for setting each bidirectional buffer to input mode or output mode. The bidirectional buffers are asynchronously and uniformly set to output mode to detect a logic error. If there is ... 01/11/07 - 20070011528 - Method and apparatus for testing an ultrasound system A medical imaging system is provided that includes a plurality of circuit boards configured to be tested using boundary scan test vectors. A controller of the medical imaging system is configured to test the plurality of circuit boards. The controller is further configured to access test profiles to perform boundary ... 01/04/07 - 20070006056 - Method and apparatus for enabling multipoint bus access The invention includes a method and apparatus for enabling multipoint bus access. In one example, the open ring-architecture bus includes a boundary scan bus including a plurality of bus access points adapted for interfacing with a plurality of circuit packs, a first termination circuit coupled to a first end of ... 11/02/06 - 20060248420 - Pixel circuit, organic light emitting display using the pixel circuit and driving method for the display A pixel circuit and an organic light emitting display using the pixel circuit and a pixel circuit driving method capable of displaying an image of desired brightness are disclosed. The pixel provides a current for an organic light emitting diode which is not affected by a kickback voltage which occurs ... 11/02/06 - 20060248419 - Methods and apparatus for extending semiconductor chip testing with boundary scan registers Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip ... 10/26/06 - 20060242514 - Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first ... 10/26/06 - 20060242513 - Enhancements to data integrity verification mechanism A method and apparatus is provided for maintaining data integrity. According to the method, a physical checksum calculation is performed on a block of data. After performing the physical checksum calculation, a logical check is performed on the data contained with the block of data. If the block of data ... 10/26/06 - 20060242512 - Ip core design supporting user-added scan register option An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ... 10/26/06 - 20060242511 - High speed interconnect circuit test method and apparatus A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The ... 09/07/06 - 20060200718 - Boundary scan testing system A boundary scan testing system may include a baseboard (102, 202), a computing module (104, 204) coupled to the baseboard, and a boundary scan test module (106, 206, 306, 406) coupled to the computing module, where the boundary scan test module is coupled to execute a boundary scan test (120, ... 08/31/06 - 20060195739 - Multiple device scan chain emulation/debugging A method and system is provided for emulating individual JTAG devices in a multiple device boundary scan chain. The method includes coupling an emulator to the scan chain, and obtaining the topology of the scan chain. One device within the scan chain is then selected, and at least one other ... 08/17/06 - 20060184848 - Semiconductor integrated circuit having test function and manufacturing method The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching ... 08/10/06 - 20060179374 - Wireless hardware debugging Embodiments disclosed relate to wireless debugging of digital circuitry. A boundary scan system for debugging a digital circuit includes a boundary scan interface configured to couple to the digital circuit. The system further includes a first wireless port coupled to the boundary scan interface. The system further includes a second ... 08/10/06 - 20060179373 - Device and method for jtag test In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two devices such as a JTAG test supported device and a JTAG test unsupported device, boundary scan FFs are inserted between ... 07/13/06 - 20060156124 - Boundary scan apparatus and interconnect test method An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for ... 07/13/06 - 20060156123 - Fault free store data path for software implementation of redundant multithreading environments A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked reaches protected memory without any faults. The present ... 05/18/06 - 20060107146 - Demultiplexing circuit, light emitting display using the same, and driving method thereof A demultiplexing circuit, a light emitting display using the same, and a driving method thereof, in which the number of output lines provided in a data driver is reduced. The light emitting display includes: a scan driver for supplying scan signals to scan lines in sequence; a data driver provided ... 05/18/06 - 20060107145 - Combinatorial at-speed scan testing A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The ... 03/30/06 - 20060069974 - One-hot encoded instruction register for boundary scan test compliant devices An integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry comprised in the integrated circuit chip is tested is provided. The integrated circuit chip comprises a Boundary Scan register and an instruction register. The Boundary Scan register is ... 12/22/05 - 20050283693 - Multi-chip digital system signal identification method and apparatus The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller ... 12/01/05 - 20050268193 - Module, electronic device and evaluation tool The test controller further includes dedicated control circuitry including a plurality of logic gates (180) and a first logic gate (182). The plurality of logic gates is arranged to decode the content of the first register (142) and provide the first logic gate (182) with a resulting gating signal for ... 09/15/05 - 20050204230 - Method and a unit for programming a memory A unit and a method of programming mounted programmable memories by a programming boundary scan component/unit being directly coupled to the programmable memory and directly coupled to a boundary scan test system. Directly coupling the memory to the programming boundary scan component Thereby eliminates having to serially clock information to ... 09/15/05 - 20050204229 - Boundary scan tester for logic devices A boundary scan tester is provided for testing logic devices. The boundary scan tester includes a boundary scan register, a data decompressor, a data compressor, and a derived boundary scan register. The boundary scan register registers the applied test vectors and test responses of a logic device, and the data ... 09/01/05 - 20050193301 - Cdr-based clock synthesis A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous ... 07/14/05 - 20050154949 - System for flexible embedded boundary scan testing A flexible Boundary Scan test system is disclosed. The system includes an interpreter module operable to execute a program element selected from a plurality of program elements that include at least one instruction type having an interface to identify and execute selected functions wherein each of the selected functions has ... 06/23/05 - 20050138512 - Semiconductor integrated circuit A semiconductor integrated circuit has a plurality of signal paths and a plurality of scan separation circuits. Each scan separation circuit is provided on each signal path. Each scan separation includes a first selector and a second selector. The semiconductor integrated circuit also includes a first circuit block and a ... 06/23/05 - 20050138511 - Self-timed scan circuit for asic fault testing A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and ... ### FreshPatents.com Support |