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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing > Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) Scan Path Testing (e.g., Level Sensitive Scan Design (lssd))Scan Path Testing (e.g., Level Sensitive Scan Design (lssd)) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266282 - Fault-tolerant architecture of flip-flops for transient pulses and signal delays A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the ... 11/08/07 - 20070260951 - Uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit A method and/or system of uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit are disclosed. In one embodiment, a storage circuit includes a master latch coupled to a slave latch where each undergoes data transmission at an opposite transition edge of a ... 11/08/07 - 20070260950 - Method and apparatus for testing a data processing system A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if ... 11/08/07 - 20070260949 - Trading propensity-based clustering of circuit elements in a circuit design An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches ... 11/01/07 - 20070255988 - Computer-aided design (cad) multiple-capture dft system for detecting or locating crossing clock-domain faults A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method ... 11/01/07 - 20070255987 - Control signal synchronization of a scannable storage circuit A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a digital system includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include ... 10/18/07 - 20070245191 - At-speed transition fault testing with low speed scan enable A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of ... 10/11/07 - 20070240023 - Data shift capability for scannable register A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to ... 10/04/07 - 20070234152 - Data driver and flat panel display device using the same A flat panel display device including: a display region including pixels connected to scan lines and data lines; a dummy display region including dummy pixels connected to at least two dummy scan lines and the data lines; a scan driver for providing scan signals and dummy scan signals to the ... 10/04/07 - 20070234150 - Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving ... 09/27/07 - 20070226562 - Method and apparatus for secure scan testing A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan ... 09/27/07 - 20070226561 - Testing of data retention latches in circuit devices A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan ... 09/20/07 - 20070220385 - Semiconductor device provided with function for screening test regarding operating speed A semiconductor device includes one or more margin detecting circuits, each of which includes a first flip-flop having a first clock signal input node coupled to a clock supply node and a first data input node coupled to a data supply node, a second flip-flop having a second clock signal ... 09/20/07 - 20070220384 - Isolating the location of defects in scan chains Techniques for isolating defects in scan chains are disclosed. Diagnostics fault simulation is performed on chosen faults that are consistent with the nature of a scan chain defect, while keeping information about the failures that each fault predicts. Once this information is available, the effects of defects at specific locations ... 09/20/07 - 20070220383 - Systems and methods for identifying errors in lbist testing Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment, an LBIST controller enables continuous execution of LBIST test cycles (including functional and scan shift phases) prior to ... 09/20/07 - 20070220382 - Negative edge flip-flops for muxscan and edge clock compatible lssd A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to ... 09/06/07 - 20070208974 - Electronic circuit An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a ... 08/30/07 - 20070204192 - Method for detecting defects of a chip A method for detecting a defect of a chip includes: utilizing a plurality of scan patterns to scan a plurality of scan chains of the chip; for each of the scan patterns, obtaining a suspected defect set and an unsuspected defect set; obtaining an intersection of all suspected defect sets ... 08/09/07 - 20070186132 - Testing of circuits with multiple clock domains A circuit under test (24) has a scan chain comprising flip-flop cells (IOa-c) with inputs and outputs operationally connected to the logic circuits (12). Different clock domains each contain a respective part of the flip-flop cells (10a-c) that are clocked by a respective domain clock signal (CLKa, CLKb, CLKc). A ... 07/26/07 - 20070174747 - Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan ... 07/19/07 - 20070168805 - Scan chain diagnostics using logic paths A structure and method for optimzing scan chain fail disgnosis. First, logic paths from target latches in a target scan chain to observation latches in at least one other observation scan chain are identified. Then, the locations of the observation latches within the other scan chains are optimized. ... 07/19/07 - 20070168804 - Burn-in test circuit, burn-in test method, burn-in test apparatus, and a burn-in pattern generation program product A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being ... 07/19/07 - 20070168803 - Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug ... 07/19/07 - 20070168802 - Semiconductor integrated circuit with test circuit A semiconductor integrated circuit has a scan path that includes, between the output of the first logic section and the input of the functional block, a parallel path and a serial shift path for serially transferring data, and that includes first selectors for connecting the output of the first logic ... 07/19/07 - 20070168801 - Adapting scan architectures for low power operation Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional ... 07/19/07 - 20070168800 - Sequential scan technique providing enhanced fault coverage in an integrated circuit According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out operations. In an embodiment, a single clock signal drives the elements in ... 07/19/07 - 20070168799 - Dynamically configurable scan chain testing An integrated circuit comprises a circuit under test, a plurality of scan chains coupled to the circuit under test, and a dynamically configurable input selection logic. The dynamically configurable input selection logic couples to the scan chains, receives one or more scan input bit streams, and provides a scan input ... 07/19/07 - 20070168798 - Scan string segmentation for digital test compression A new technique to determine the placement of exclusive-ors in each scan string of a chip may be used to achieve improved test vector compression, and this may be used along with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, ... 07/19/07 - 20070168797 - Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan ... 07/12/07 - 20070162805 - Automatable scan partitioning for low power using external control Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional ... 07/12/07 - 20070162804 - Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault ... 07/12/07 - 20070162803 - Accelerated scan circuitry and method for reducing scan test data volume and execution time An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state ... 06/28/07 - 20070150781 - Apparatus with programmable scan chains for multiple chip modules and method for programming the same An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a ... 06/28/07 - 20070150780 - Semiconductor integrated circuit and method for controlling the same A semiconductor integrated circuit includes a target circuit with at least a scan chain having sub scan chains of stages to sequentially shift a test data in response to a clock signal in a scan path test mode, and each of the sub scan chains includes first flip-flops connected in ... 06/21/07 - 20070143653 - Reduced pin count scan chain implementation The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; ... 06/14/07 - 20070136629 - Method for testing semiconductor integrated circuit and method for verifying design rules Not only defects in DC characteristics and a degeneracy fault but defects in AC characteristics such as SI faults (a crosstalk faults and an IR-DROP fault) and a delay fault, which tend to increase as design rules become finer in recent years, are detected as a measure used when the ... 05/31/07 - 20070124633 - Scan driver and organic light emitting display device An organic light emitting display device includes a scan driver for supplying a first scan signal to a first scan line during a first period and a second period, a second scan signal to a second scan line during the second period, and a light emitting control signal to a ... 05/24/07 - 20070118780 - Hierarchical access of test access ports in embedded core integrated circuits An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one ... 05/17/07 - 20070113131 - Semiconductor integrated circuit, and designing method and testing method thereof A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for ... 05/17/07 - 20070113130 - Low power testing of very large circuits Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at ... 05/17/07 - 20070113129 - Method and apparatus for testing logic circuit designs Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor ... 05/17/07 - 20070113128 - Method and apparatus for synthesis of multimode x-tolerant compressor Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described. ... 05/03/07 - 20070101221 - Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes ... 04/26/07 - 20070094559 - Wiring structure and method of semiconductor integrated circuit To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention includes: a fixed layer where a common line ... 04/19/07 - 20070089003 - Method and apparatus for test connectivity, communication, and control Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and ... 04/19/07 - 20070089002 - Pc-connectivity for on-chip memory An interface for converting a traditional scan-chain interface into one where locations in the scan-chain can be read or written to from an addressed interface is provided. The interface of the invention includes a scratch pad memory into which the values at the locations in the scan-chain are copied. Those ... 04/19/07 - 20070089001 - System and method for defect-based scan analysis A method for defect-based scan analysis comprises, for each node in a first circuit, determining its neighborhood net, injecting defects and modeling the defects with stuck-at-0 and stuck-at-1 fault models, generating at least one test pattern and applying the at least one test pattern to the neighborhood net with the ... 04/19/07 - 20070089000 - Scan driving circuit and organic light emitting display using the same A scan driving circuit including an input terminal to receive an input signal or a voltage output from a previous stage; first and second clock terminals to receive first and second clock signals having phases inverted to each other and partially overlap at a high level, respectively; and a plurality ... 04/19/07 - 20070088999 - Test output compaction for responses with unknown values A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles. ... 04/05/07 - 20070079193 - Scannable latch A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving ... 04/05/07 - 20070079192 - Scan driver and organic light emitting display device having the same A scan driver having no shift register and an organic light emitting display device having the same are disclosed. The scan driver includes a latch unit and a NAND gate instead of a shift register, thereby reducing the area occupied by the driver in a display panel. The scan driver ... 04/05/07 - 20070079191 - Scan driving circuit and organic light emitting display using the same A scan driving circuit and an organic light emitting display using the same is disclosed. A first scan driver having a plurality of first stages sequentially outputs a selection signal, and a second scan driver having a plurality of second stages sequentially outputs an emission signal. Each of the first ... 03/15/07 - 20070061647 - Scan chain disable function for power saving An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the ... 03/15/07 - 20070061646 - Selectable jtag or trace access with data store and output An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a ... 03/15/07 - 20070061645 - Register file initialization to prevent unknown outputs during test A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to ... 03/15/07 - 20070061644 - Scan verification for a device under test Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of ... 02/22/07 - 20070043989 - Method for specifying failure position in scan chain It is judged whether or not a scan chin has a failure, an arbitrary data string is inputted to the malfunction scan chain judged that a failure is present by a capture action through a combination circuit, the data string is outputted from a scan-out terminal of the malfunction scan ... 02/15/07 - 20070038910 - Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method A semiconductor integrated circuit design method is a method for designing a semiconductor integrated circuit having a main circuit as well as the spare cell including a scan flip-flop. In the method, a net list is received, which indicates a connection relationship among circuits and their positions in a semiconductor ... 02/15/07 - 20070038909 - Scan driver, display device having the same and method of driving a display device A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having ... 02/08/07 - 20070033463 - Integrated circuit comprising a test mode secured by detection of the state of a control signal An electronic circuit comprises configurable cells driven by command signals to adopt either a standard mode of operation in which they are integrated into a logic circuit, or a test mode in which they provide information on this logic circuit. The circuit includes a spy circuit capable of detecting an ... 02/08/07 - 20070033462 - Test circuit and test method A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is completed. During the shift operation, a value for refresh operation is ... 02/08/07 - 20070033461 - Method and system for encryption-based design obfuscation for an integrated circuit Encryption-based design obfuscation for an integrated circuit includes creating multiple functional circuit paths for an integrated circuit design and selecting among the multiple functional circuit paths during scan testing. Encrypting selection data corresponding to an intended function of the integrated circuit design avoids revealing the intended function as a result ... 02/08/07 - 20070033460 - System and method for scan testing A scan system comprises a scan engine adapted to receive a scan request from a host system for performing a scan test on a system-under-test. The scan engine comprises dedicated logic where a state of the dedicated logic is adapted to control processing of the scan request on the system-under-test. ... 02/08/07 - 20070033459 - Method for enabling scan of defective ram prior to repair A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal ... 01/25/07 - 20070022341 - Method and system for protecting processors from unauthorized debug access A method for securing a scan test architecture by performing an authentication operation to authorize use of a protected scan chain. ... 01/25/07 - 20070022340 - Method and apparatus for determining stuck-at fault locations in cell chains using scan chains Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan chain. The first scan chain is operable to test digital circuitry within a first portion of the cell ... 01/25/07 - 20070022339 - Digital design component with scan clock generation A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of ... 01/25/07 - 20070022338 - Sequential scan technique for testing integrated circuits with reduced power, time and/or cost Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan chain containing (a) the memory elements in the fan-out of the inputs to each of said plurality of portions, (b) the memory ... 01/18/07 - 20070016834 - Reducing power dissipation during sequential scan tests A scan cell which provides two data outputs, one of use in scan mode and another in functional mode. The functional mode output is connected to functional portions, and transitions on the functional mode output are avoided by using an isolation circuit. As a result, the inputs in functional portions ... 01/11/07 - 20070011527 - Generating responses to patterns stimulating an electronic circuit with timing exception paths Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing ... 01/11/07 - 20070011526 - Position independent testing of circuits Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided ... 01/11/07 - 20070011525 - Semiconductor integrated circuit and control method thereof A semiconductor integrated circuit according to the present invention has a logical circuit network that implements predetermined processing, a plurality of scan chains that are penetrated through the logical circuit network and test the logical circuit network in a plurality of test modes, a plurality of shared terminals that share ... 01/11/07 - 20070011524 - Scan test circuit and method of arranging the same Replaced cell CELL1 is composed of clock buffer circuit CB1 and flip-flop circuit FF1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB1a-CB1d are cascade-connected to form a clock tree circuit. A scan circuit is composed of scan flip-flop circuits SFF1-SFF4. Replaced cell CELL1 ... 01/11/07 - 20070011523 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the ... 12/14/06 - 20060282730 - Semiconductor integrated circuit incorporating test configuration and test method for the same An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain ... 12/14/06 - 20060282729 - Pipelined scan structures for testing embedded cores A scan testing technique in which test data is pipelined to scan logic within an integrated circuit. In system on a programmable chip (SOPC) designs, pipelines are easily built in the programmable logic device (PLD) logic by configuring programmable interconnects to connect registers in a pipelined manner so that test ... 12/14/06 - 20060282728 - Methods for using checksums in x-tolerant test response compaction in scan-based testing of integrated circuits Methods for designing and using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines (e.g., a two-dimensional structure, or the like). Each point represents a MUXed flip-flop ... 12/14/06 - 20060282727 - Scan test design method, scan test circuit, scan test circuit insertion cad program, large-scale integrated circuit and mobile digital equipment In scan test circuit design, a plurality of flipflop circuits (102a, 102b or 102c) driven with each of final-stage elements 101f of a clock tree T are connected in series, to form a sub-scan chain. Also, sub-scan chains smallest in the relative difference in the number of stages of delay ... 11/16/06 - 20060259838 - Scan sequenced power-on initialization A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This invention supplies a predefined pattern to parallel scan chains following power-on reset. These parallel scan chains are already required for structural manufacturing test. Once the power-on ... 11/09/06 - 20060253755 - Display units A display unit comprising a first switch unit, a driving unit, a light-emitting unit, and a control circuit. The first switch unit has a control electrode coupled to a scan line, a first electrode coupled to a data line, and a second electrode coupled to a first node. The driving ... 11/09/06 - 20060253754 - System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal ... 11/09/06 - 20060253753 - System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) ... 11/02/06 - 20060248418 - Scan test expansion module An external scan test module that is adapted to act as an interface between an automated tester and a device under test. The external scan test module includes a scan pattern memory to hold scan patterns for at least one configuration of the device under test. A failure log memory ... 10/26/06 - 20060242510 - Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches ... 10/26/06 - 20060242509 - Method and system for an on-chip ac self-test controller An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at ... 10/26/06 - 20060242508 - Simultaneous scan testing for identical modules A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process scan input and produce a first scan output. The system 100 includes a second module 150 substantially ... 10/26/06 - 20060242507 - Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG)). ... 10/26/06 - 20060242506 - High-speed level sensitive scan design test scheme with pipelined test clocks This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system ... 10/26/06 - 20060242505 - Apparatus for performing stuck fault testings within an integrated circuit An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select ... 10/19/06 - 20060236179 - Delay test method for large-scale integrated circuits The propagation delay of a combinatorial circuit in a large-scale integrated circuit is tested by carrying out two scan tests. Both scan tests generate the same input signal transitions to the combinatorial circuit. One scan test scans the outputs of the combinatorial circuit after the transitions propagate through the combinatorial ... 10/19/06 - 20060236178 - Ram testing apparatus and method Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected value when a fault is detected. ... 10/19/06 - 20060236177 - Method for eliminating hold error in scan chain A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors ... 10/19/06 - 20060236176 - Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset ... 09/28/06 - 20060218455 - Integrated circuit margin stress test system Systems and methods are disclosed for testing a synchronous memory system by electrically stressing one or more electrical conditions of the component circuits; providing a Built-In Self-Test (BIST) controller to control the electrical stress during device testing; and providing a test stimuli during testing. In another aspect, the memory system ... 08/31/06 - 20060195738 - Merged misr and output register without performance impact for circuits under test The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit ... 08/31/06 - 20060195737 - System and method for characterization of certain operating characteristics of devices A system and method is provided for improving integrated circuit device characterization without requiring external tester hardware. On-chip circuitry is provided to measure the delay of a signal through a given scan chain when the scan chain latches have been placed in flush mode. A control signal generated by the ... 08/24/06 - 20060190786 - Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit ... 08/24/06 - 20060190785 - In-situ monitor of process and device parameters in integrated circuits In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing ... 08/24/06 - 20060190784 - Method and circuit using boundary scan cells for design library analysis A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan ... 08/03/06 - 20060174176 - Semiconductor integrated circuit and method for testing the same In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power ... 08/03/06 - 20060174175 - Array self repair using built-in self test techniques A soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Each arrays outputs are monitored by a different multiple input signature register (MISR) with ... 07/27/06 - 20060168490 - Apparatus and method of controlling test modes of a scannable latch in a test scan chain Apparatus for controlling an operational test mode of a scannable latch in a test scan chain, the scannable latch comprising a scan latch and a functional latch coupled thereto, comprises: first circuit for gating a clock signal to the functional latch, the functional latch being responsive to the gated clock ... 07/20/06 - 20060161826 - Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic ... 07/13/06 - 20060156122 - Mask network design for scan-based integrated circuits A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The ... 07/13/06 - 20060156121 - Emission control driver and organic light emitting display using the same An emission control driver compensates for the threshold voltages of transistors to provide uniform brightness using a plurality of emission control signal generating circuits. ... 07/13/06 - 20060156120 - Light emitting device and method of driving the same The present invention relates to a light emitting device for reducing consumption of an electric power in screen protecting mode. The light emitting device includes a plurality of data lines, a plurality of scan lines, a plurality of pixels, a controller, a data driving circuit and a scan driving circuit. ... 07/13/06 - 20060156119 - Semiconductor apparatus and clock generation unit A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input and output of data in the internal circuit, a clock generator for generating a launch clock signal for sending data to ... 07/13/06 - 20060156118 - Scan driver and organic light emitting display for selectively performing progressive scanning and interlaced scanning A scan driver and an organic light emitting display (OLED) for selectively performing progressive scanning and interlaced scanning. The scan driver includes a plurality of scan units. A scan unit generates an odd-number scan signal or an even-number scan signal and includes a flip-flop and a scan signal generator. The ... 07/13/06 - 20060156117 - Processor, its error analytical method and program A plurality of error holding latches built in CPU cores formed on a LSI chip are connected and constituted into a line of error collecting scan chain, and the interior of the error collecting scan chain is divided into CPU latch groups corresponding to the CPU cores, and mask circuits ... 07/13/06 - 20060156116 - Method and apparatus for controlling ac power during scan operations in scannable latches A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a functional data output and a scan data output. A switching control is provided with the functional data output. The switching control is driven to prevent switching ... 07/06/06 - 20060150041 - Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ate) The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a ... 06/29/06 - 20060143551 - Localizing error detection and recovery In one embodiment, the present invention includes a method of detecting and correcting an error by detecting the error in a circuit coupled to a first stage of a semiconductor device, and correcting the error in the circuit using valid data present in the circuit. The circuit may be a ... 06/22/06 - 20060136796 - Lsi device having scan separators provided in number reduced from signal lines of combinatorial circuits A scan separator in a large scale integration device is made intensive to suppress the circuit scale of the entire device from increasing. A scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks. Each scan separator includes one selector, a flip flop for constituting a ... 06/22/06 - 20060136795 - Method of testing scan chain integrity and tester setup for scan block testing A method of scan chain integrity testing for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) generating a partial shift test bench for the integrated circuit design wherein the partial shift test bench includes scan chains stitched together into shift registers and ... 06/15/06 - 20060129900 - Scan chain partition for reducing power in shift mode A scan chain partition includes a serial input coupled to a scan input signal pin of a module under test; a plurality of scan sub-chains coupled to the serial input; a scan sub-chain output multiplexer coupled to the plurality of scan sub-chains for sequentially selecting a scan shift output of ... 06/08/06 - 20060123295 - Register file and its storage device In response to an input of a first shift clock in the order of the last register to the head register in the scan connection configuration circuit and memory array, a scan control circuit first copies data from each first device in the last register in the memory array to ... 06/08/06 - 20060123294 - Method and test apparatus for testing integrated circuits using both valid and invalid test data A simplified boundary scan test method capable of performing boundary test scanning of semiconductor chips. The test method comprises providing valid test data to a first terminal of the semiconductor device and purposely providing invalid test data to a second terminal of the semiconductor device in a predetermined pattern algorithm. ... 05/18/06 - 20060107144 - Power reduction in module-based scan testing A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as ... 05/18/06 - 20060107143 - Organic light emitting display An organic light emitting display including a demultiplexer on each data line that splits and supplies each data signal to a plurality of data lines, thereby decreasing the number of output lines required and reducing production cost. Further, voltages corresponding to the data signals are sequentially charged in data capacitors, ... 05/18/06 - 20060107142 - Semiconductor integrated circuit A semiconductor integrated circuit for performing processing relating to a test of a plurality of memory units provided therein while suppressing an increase of a circuit area is provided, wherein testing input data generated in a testing circuit is shifted successively on registers of a first data shift circuit formed ... 05/11/06 - 20060101316 - Test output compaction using response shaper An improved test output compaction architecture and method is disclosed that takes advantage of a response shaper in order to minimize masking of faults during compaction. ... 05/11/06 - 20060101315 - Leakage current reduction system and method An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a ... 05/04/06 - 20060095819 - Method and system for clock skew independent scan register chains A method and system for system for clock skew independent scan chains are disclosed. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second ... 05/04/06 - 20060095818 - System and method for automatic masking of compressed scan chains with unbalanced lengths A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a ... 04/20/06 - 20060085709 - Flip flop circuit & same with scan function A pulse-based flip flop, which outputs a scan input signal and a data signal, may include: a pulse generator to generate a pulse signal for coordinating operation of the flip flop; a multiplexer to receive the data signal, the scan input signal, and a scan enable signal, and to selectively ... 04/20/06 - 20060085708 - Transition fault detection register with extended shift mode An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a ... 04/20/06 - 20060085707 - High speed energy conserving scan architecture A system comprising a tester and an integrated circuit, where the integrated circuit comprises a flip-flop, the flip-flop coupled to the tester and a circuit logic. The flip-flop comprises a scan input signal and a scan output signal, the signals coupled to the tester. The flip-flop also comprises multiple clock ... 04/13/06 - 20060080583 - Store scan data in trace arrays for on-board software access In the present invention, register values are obtained by scanning, and are then written to one or more trace arrays on the chip. The scan data in the trace arrays is then read out by software. The register scan data can be recirculated among the registers, and addition scans can ... 04/06/06 - 20060075317 - Methods and apparatus for programming and operating automated test equipment In one embodiment, an electronic device is tested using automated test equipment (ATE) by 1) storing different vectors of scan load data in memory of the ATE; 2) storing a scan unload subroutine in the memory of the ATE; 3) stimulating the electronic device by retrieving the different vectors of ... 04/06/06 - 20060075316 - Methods and apparatus for providing scan patterns to an electronic device In one embodiment, a method provides scan patterns to an electronic device having BIST hardware. The BIST hardware has production and diagnostic test modes, and the device outputs one or more response signatures in the production test mode and outputs raw response data in the diagnostic test mode. In production ... 04/06/06 - 20060075315 - Method and process for manufacturing test generation An improved method and process of verifying a digital logic design complies with certain manufacturing test rules or guidelines to ensure adequate manufacturing test data can be generated. A replacement is created for any portion of a design to make it usable by the manufacturing test tool set, without requiring ... 03/30/06 - 20060069973 - Combinatorial at-speed scan testing A combinatorial at-speed scan testing. A processor including a plurality of distributed slave counters. Each distributed slave counter coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop ... 03/30/06 - 20060069972 - Methods and computer program products for debugging clock-related scan testing failures of integrated circuits The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying good and bad scan paths among a set of scan paths. A scan path is bad if it is not producing any output. A scan path is good if it ... 03/23/06 - 20060064616 - Method and apparatus for at-speed testing of digital circuits A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the ... 03/23/06 - 20060064615 - On-chip service processor An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits ... 03/23/06 - 20060064614 - Method and apparatus for pipelined scan compression A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one ... 03/16/06 - 20060059396 - Semiconductor integrated circuit having bonding optional function Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test circuit is selectively set to an operable or disabled state by a control gate according to a ... 03/16/06 - 20060059395 - Ieee std. 1149.4 compatible analog bist methodology An analog built-in self-test (BIST) methodology based on the IEEE 1149.4 mixed signal test bus standard. The on-chip generated triangular stimuli are transmitted to the analog circuit under test (CUT) through the analog test buses, and their test responses are quantized by the dual comparators. The quantized results are then ... 03/02/06 - 20060048029 - Semiconductor integrated circuit The number of S-FFs in a scan-path is decreased by half and a test time needed is decreased. An I/O terminal 1A is connected to a scan-path 31-3m and a combination circuit 2 via a selector 5A and an output of the scan-path 31-3m is connected to an I/O terminal ... 03/02/06 - 20060048028 - Method and apparatus for selective scan chain diagnostics A method, apparatus and program product for testing at least one scan chain in an electronic chip in which the scan chain is formed by shift register latches arranged in the chain having a scan path with input pins and output pins. A flush test is executed for the scan ... 02/23/06 - 20060041806 - testing method for semiconductor device and testing circuit for semiconductor device There is provided a testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, the semiconductor device including a plurality of first scan chains configured ... 02/02/06 - 20060026473 - Inversion of scan clock for scan cells In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A ... 02/02/06 - 20060026472 - Designing scan chains with specific parameter sensitivities to identify process defects A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process ... 01/26/06 - 20060020864 - Method and system for blocking data in scan registers from being shifted out of a device Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said ... 01/26/06 - 20060020863 - Scanning latches using selecting array A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By ... 01/26/06 - 20060020862 - Apparatus for generating deterministic test pattern using phase shifter An apparatus for generating a deterministic test pattern is provided for a BIST having a scan chain, comprising the control bits storing devise for storing the number of a deterministic test pattern that is covered by a tap configuration; pattern counter devise for receiving the values stored in the control ... 01/19/06 - 20060015787 - Externally-loaded weighted random test pattern compression The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits. ... 01/05/06 - 20060005091 - Error detecting circuit In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal ... 12/29/05 - 20050289421 - Semiconductor chip A semiconductor chip has a multiplicity of flipflops which can be connected up to form one or more shift registers for the purpose of testing the semiconductor chip, and having a JTAG test access port based on IEEE 1149.1 which can be used to put the semiconductor chip into a ... 12/29/05 - 20050289420 - Serial burn-in monitor There is provided a burn-in monitor for testing modules on an Integrated Circuit (IC), and a corresponding method. The burn-in monitor comprises: a Serial Test and Configuration Interface STCI for controlling and observing modules through a scan chain; a scan-in pin for loading a prepared set of test vectors; and ... 12/29/05 - 20050289419 - Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output ... 12/29/05 - 20050289418 - Methods and apparatus for monitoring internal signals in an integrated circuit Apparatus and methods are provided for debugging an integrated circuit. Local multiplexer circuits are provided near first and second circuit blocks in the integrated circuit. Each multiplexer circuit includes input nodes, a control node, and an output node. A first input node of the first multiplexer circuit is coupled to ... 12/29/05 - 20050289417 - Scan enabled storage device A scan enabled storage device includes two storage elements and two input circuits. A data input circuit accepts a data signal, a clock signal, and a scan enable signal to inhibit the operation of the clock signal. A scan data input circuit accepts a scan data signal and a scan ... 12/22/05 - 20050283692 - Direct scan access jtag The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the ... 12/22/05 - 20050283691 - Scan flip-flop circuit with reduced power consumption A scan flip-flop circuit and related scan chain are disclosed. The scan flip flop comprises in one embodiment an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the scan flip-flop circuit. The scan flip-flop ... 12/22/05 - 20050283690 - Wrapper serial scan chain functional segmentation A wrapper serial scan chain used during test of an integrated circuit is provided for a first functional block of circuitry and is segmented to provide a separately accessible wrapper serial scan chain segment that can be used to apply test to a second functional block of circuitry whilst bypassing ... 12/08/05 - 20050273683 - Insertion of embedded test in rtl to gdsii flow A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of the circuit into an unmapped circuit description; extracting information from the unmapped circuit description for use in generating and inserting RTL ... 12/01/05 - 20050268192 - Scan driving apparatus, flat panel display having the same, and driving method thereof A scan driving apparatus having decreased size and power consumption, a flat panel display having the same, and a driving method thereof. The scan driving apparatus comprises a shift register generating output signals shifted in sequence in response to a clock signal, and a scan signal generator generating at least ... 12/01/05 - 20050268191 - Semiconductor integrated circuit device having scan flip-flop circuit Asemiconductor integrated circuit devices has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan ... 12/01/05 - 20050268190 - Dynamically reconfigurable shared scan-in test architecture A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume ... 10/27/05 - 20050240848 - Masking circuit and method of masking corrupted bits A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each ... 10/27/05 - 20050240847 - Clock controller for at-speed testing of scan circuits A test clock controller for generating a test clock signal for scan chains in integrated circuits having one or more clock domains, comprises a shift clock controller for generating a shift clock signal for use in loading test patterns into scan chains in the clock domains and for unloading a ... 10/27/05 - 20050240846 - Accurate generation of scan enable signal when testing integrated circuits using sequential scanning techniques An accurate scan enable signal may be generated from an external scan enable (e.g., generated by test equipment). The external scan enable signal may contain transitions from scan mode to capture mode, and vice versa. The accurate scan enable signal may be generated to time transitions from scan mode to ... 10/27/05 - 20050240845 - Reducing number of pins required to test integrated circuits Number of pins required to test integrated circuits are reduced by scanning in a sequence of bits sequentially on a pin. The scanned bits are shifted into a shift register, and then loaded into a select register. The bit values in the select register represent the set of tests desired ... 10/20/05 - 20050235185 - Scan interface A scan interface for an integrated circuit includes a scan clock and a scan mode signal. The scan mode signal is indicative of whether or not scan is active, and may be used by dedicated scan circuitry in integrated circuit. Such circuitry may be inactive if the scan mode indicates ... 10/20/05 - 20050235184 - Semiconductor integrated circuit device and test method thereof Disclosed is a semiconductor integrated circuit device using a scan path test in which propagation of an indefinite value to a test target path is inhibited while suppressing an increase in a circuit area, and a test method thereof. When a plurality of flip-flops within a logic circuit is serially ... 10/20/05 - 20050235183 - Restricted scan reordering technique to enhance delay fault coverage The present invention is directed to improved delay fault testing by optimizing the order of scan cells in a scan chain. ... 10/20/05 - 20050235182 - Method on scan chain reordering for lowering vlsi power consumption A method for reordering a scan chain so that the given constraints are met and the peak power dissipation is minimized and disclosed. The constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The developed tool can be embedded ... 10/13/05 - 20050229059 - Flip flop circuit and apparatus using a flip flop circuit A flip flop circuit comprises a first latch circuit which latches an input data at a leading edge of a clock signal, a second latch circuit which latches the input data at a trailing edge of the clock signal, and a selector which, during a period from the leading edge ... 10/13/05 - 20050229058 - Semiconductor intergrated circuit The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan thereof having functions to output the status ... 10/13/05 - 20050229057 - Method, apparatus, and computer program product for implementing deterministic based broken scan chain diagnostics A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is ... 10/13/05 - 20050229056 - Circuit and method for comparing circuit performance between functional and ac scan testing in an integrated circuit (ic) A circuit and method for determining operating speed of a clock associated with an integrated circuit (IC), comprises an IC logic element, a scan chain, and a calibration circuit comprising a first plurality of flip-flops and a combinational delay line. The calibration circuit operates in a functional test mode and ... 09/29/05 - 20050216807 - System and method for testing a circuit Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input ... 09/29/05 - 20050216806 - Edge-triggered master + lssd slave binary latch Disclosed is a binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable. The binary latch comprises an edge triggered master flip-flop (2), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design ... 09/29/05 - 20050216805 - Methods for debugging scan testing failures of integrated circuits The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying a bad scan path among a set of scan paths and segmenting the bad scan path into two segments. Once the bad scan path is segmented into two segments, scan ... 09/22/05 - 20050210350 - Sampling rate converter for both oversampling and undersampling operation A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The ... 09/22/05 - 20050210349 - Scan test tools, models and/or methods Tools, systems and/or methods for use in a test process of a circuit device. Such tools, systems and/or methods may provide for identifying respective parent and branch portions of a scan chain of a circuit device, the scan chain having at least one scan input and one or more scan ... 09/15/05 - 20050204228 - Low power scan & delay test method and apparatus Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used ... 09/15/05 - 20050204227 - Semiconductor circuit apparatus and scan test method for semiconductor circuit A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between ... 09/15/05 - 20050204226 - Core circuit test architecture A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each ... 09/15/05 - 20050204225 - Serial i/o using jtag tck and tms signals The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional ... 09/08/05 - 20050198556 - Computer support network with customer portal to monitor incident-handling status by vendor's computer service system Customer support personnel can access via a vendor's portal an automated support vendor website to view the status of a fault incident that is being handled by the vendor's automated support system. In an illustrated embodiment, the customer can actually alter the status of the fault incident while it is ... 09/01/05 - 20050193300 - Semiconductor integrated circuit detecting glitch noise and test method of the same A semiconductor integrated circuit having a plurality of wirings and a scan chain including a testing circuit configured to detect glitch noise caused by crosstalk between the wirings and a plurality of scan flip-flops connected in series, the semiconductor integrated circuit includes a retention circuit receiving a data signal propagating ... 09/01/05 - 20050193299 - Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a ... 09/01/05 - 20050193298 - Testing apparatus A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes operation order holding means for holding information indicating that a test operation by a first testing module among the plurality of testing modules ... 09/01/05 - 20050193297 - Methods and apparatus for defect isolation In a first aspect, a first method is provided for isolating a defect in a scan chain. The first method includes the steps of (1) modifying a first test mode of one or more of a plurality of latches included in the scan chain; (2) operating the one or more ... 08/04/05 - 20050172192 - Scan based automatic test pattern generation (atpg) test circuit, test method using the test circuit, and scan chain reordering method A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point ... 08/04/05 - 20050172191 - Method and apparatus for transferring hidden signals in a boundary scan test interface An apparatus and method for transferring hidden signals in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a ... 08/04/05 - 20050172190 - Method and apparatus for accessing hidden data in a boundary scan test interface An apparatus and method for accessing hidden data in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a ... 08/04/05 - 20050172189 - Test method for a semiconductor integrated circuit having a multi-cycle path and a semiconductor integrated circuit The test method for a semiconductor integrated circuit includes a multi-cycle test step and a single-cycle test step. In the multi-cycle test step, a data-read side flipflop holds data according to a clock enable signal to test a multi-cycle path. In the single-cycle test step, no data is captured for ... 08/04/05 - 20050172188 - Diagnostic method for detection of multiple defects in a level sensitive scan design (lssd) Methods of testing scan chains in integrated circuits are provided. One method may include steps of placing the scan chain circuit into an operating region, loading a scan test pattern into the scan chain, placing the scan chain circuit into a failing region, applying a shift clock pulse to the ... 07/28/05 - 20050166109 - Enhanced jtag interface An enhanced JTAG interface provides an additional clock output at any desired I/O port of a logic device during normal operation. The interface includes a boundary scan data cell associated with each I/O port that enables either input data to the I/O port in a normal mode or routes the ... 07/28/05 - 20050166108 - Segmented scan chains with dynamic reconfigurations A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially ... 07/21/05 - 20050160337 - Jtag bus communication method and apparatus Today the IEEE 1149.1 (JTAG) Tap port is used for many different applications. While initially designed to provide a serial test interface on ICs to facilitate board testing, the Tap port now serves as a serial interface for additional IEEE standards for such things as emulation and debug (IEEE 5001) ... 07/21/05 - 20050160336 - Semiconductor lsi circuit with scan circuit, scan circuit system, scanning test system and method A semiconductor LSI circuit provided with a scan circuit includes: to-be-tested combinational logic circuits; scan circuits adjacent to and disposed alternately with the combinational logic circuits; scan elements, which form the scan circuits; a first selector inserted in a first scan circuit scan and connects a first group of scan ... 07/14/05 - 20050154948 - Accelerated scan circuitry and method for reducing scan test data volume and execution time An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state ... 07/14/05 - 20050154947 - Microcomputer and method for debugging microcomputer The System on a Chip (SoC) according to the present invention provides debugging by reading or rewriting the contents of an arbitrary register within an SoC by a level-sensitive scan design (LSSD) scan test, and includes a scan chain for scan tests that connects a plurality of latch circuits in ... 07/07/05 - 20050149800 - Circuit testing with ring-connected test instrument modules Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to ... 07/07/05 - 20050149799 - Integrated circuit with leakage control and method for leakage control The present invention relates to integrated circuit with reduced leakage power and in particular to a methodology for retaining an operational state of at least a part of the integrated circuit while the part is in standby/low power mode. In detail, the inventive methodology is based on the use of ... 07/07/05 - 20050149798 - Semiconductor integrated circuit The present invention provides a LSI being capable of testing a signal path between two circuit blocks by a scan isolation test. A scan isolation circuit 30-1 includes a first selector 31 alternating a held signal S33 or a signal SA from circuit block 10A and outputting the alternated signal ... 07/07/05 - 20050149797 - Soc-based core scan chain linkage switch Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link ... 07/07/05 - 20050149796 - Removable and replaceable tap domain selection circuitry Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore ... 07/07/05 - 20050149795 - Inherently fail safe processing or control apparatus A processing/control apparatus has a first processing unit with a first data processor/controller; an input port for input data received from a remote unit; an output port for output data to be transmitted to a remote unit. The first unit comprising device for generating an unique code for functional control ... 06/23/05 - 20050138510 - Scan test circuit The scan test circuit according to one embodiment of the present invention comprises a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output ... 06/23/05 - 20050138509 - Systems and methods for circuit testing Systems and methods for improved performance of built-in-self-tests (BISTs) in integrated circuits, where variability is introduced into the self tests to improve the coverage of the tests. In one embodiment, an LBIST system includes scan chains interposed between levels of functional logic in a circuit under test. An exemplary method ... 06/23/05 - 20050138508 - Scan chain diagnostics using logic paths A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to a pre-specified criterion. The diagnosed scan chain is loaded ... ### FreshPatents.com Support - Terms & Conditions |