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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Digital Logic Testing Digital Logic TestingDigital Logic Testing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266281 - Integrated circuit chip packaging An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor. ... 11/15/07 - 20070266280 - Method and apparatus to test the power-on-reset trip point of an integrated circuit Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of ... 11/08/07 - 20070260948 - Driver ic and inspection method for driver ic and output device A driver IC including: a plurality of output pads; and a plurality of signal switch circuits, each of the signal circuits being provided on one of signal paths respectively connected to the output pads, wherein each of the signal switch circuits switches between a first state (or a use state) ... 11/01/07 - 20070255986 - Wrapper testing circuits and method thereof for system-on-a-chip A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a ... 11/01/07 - 20070255985 - Method and apparatus for disabling and swapping cores in a multi-core microprocessor In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is introduced to disable a core, to configure a mode, and to configure a site. Other embodiments are also disclosed and claimed. ... 11/01/07 - 20070255984 - Test mode for pin-limited devices A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control ... 11/01/07 - 20070255983 - Semiconductor integrated circuit and electronic device A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between ... 10/25/07 - 20070250748 - Logic circuit protected against transitory perturbations The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to ... 10/18/07 - 20070245190 - Intelligent binning for electrically repairable semiconductor chips The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures are determined. In the ... 10/18/07 - 20070245184 - Method and system for generating validation workflow Systems and methods are provided that relate to a platform, techniques, and processes for verifying the precision, sensitivity, accuracy, reproducibility, and other characteristics of biological tests, such as DNA identification or other tests or assays. According to various embodiments, a logic engine can guide a user to, arrange, conduct, and ... 10/18/07 - 20070245183 - Method and system for optimizing an integrated circuit A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or ... 10/04/07 - 20070234147 - Circuit analysis device A circuit analysis device comprises a first storing unit operable to store an execution object which can operate on a real processor and includes information of a logical circuit, an analyzing unit operable to analyze operation which is based on the function of the logical circuit and is coordinated with ... 10/04/07 - 20070234146 - Test method, test system and assist board A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory ; reading sequentially the written test ... 10/04/07 - 20070234145 - Reduced pattern memory in digital test equipment A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing ... 09/27/07 - 20070226558 - Semiconductor integrated circuit device The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of ... 09/27/07 - 20070226557 - Semiconductor integrated circuit and semiconductor integrated circuit device An LSI chip has an internal logic, power supply control circuit and module control circuits, mounted thereon. External modules are provided outside the LSI chip. A power supply circuit for supplying power to the internal logic is composed of the module control circuits and external modules, that is, the power ... 09/27/07 - 20070226556 - Methods and systems for repairing an integrated circuit device Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defective portion, and logic configured to identify an interface location. Also provided are methods for ... 09/27/07 - 20070226555 - Graphical presentation of semiconductor test results Methods and apparatus for graphically presenting test results of a circuit device under test are presented. Test results of a circuit device under test are acquired. Graphical diagrams comprising representations of at least a portion of the circuit device under test and having circuit components and associated circuit component terminals ... 09/27/07 - 20070226554 - High-efficiency time-series archival system for telemetry signals In one embodiment, a method and apparatus for high-efficiency time-series archiving for computer server telemetry signals is disclosed. The method includes selecting one or more telemetry signals of a plurality of telemetry signals by a sequential probability ratio test (SPRT) algorithm, the SPRT algorithm identifying the one or more telemetry ... 09/20/07 - 20070220380 - Message system for logical synchronization of multiple tester chips A message system for logically synchronizing a large number of tester chips includes a message pipeline for multiple sets of tester chips. Each set of tester chips includes a delay unit through which messages are communicated to the message pipeline from the set of tester chips and from the message ... 09/13/07 - 20070214397 - Method for testing non-deterministic device data A method for testing semiconductor devices that output non-deterministic entity information such as packet and control signals is disclosed. The method includes the steps generating test signals with a semiconductor tester and applying the generated test signals to the device-under-test. Actual output entities from the DUT in response to the ... 09/06/07 - 20070208973 - Pci-e debug card A PCI-E debug card includes an insertion part, a low-pin-count pin set, a power pin, a ground pin, a decoder and a display unit. The insertion part is for connecting to a PCI-E slot. The low-pin-count pin set includes a reset pin, a clock pin and a plurality of data ... 09/06/07 - 20070208972 - Method and machine-readable media for inferring relationships between test results In one embodiment, a method for inferring relationships between test results 1) receives sequential test data from a tester performing tests on a number of devices under test (DUTs); 2) upon receiving a DUT identifier, determines if a data structure exists for the DUT identified by the one of the ... 09/06/07 - 20070208971 - Test circuit and method for hierarchical core A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output ... 09/06/07 - 20070208970 - Test architecture and method According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test ... 08/30/07 - 20070204191 - Method for detecting a malfunction in a state machine A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. ... 08/23/07 - 20070198881 - Test system and method for testing electronic devices using a pipelined testing architecture A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or ... 08/16/07 - 20070192658 - Measuring the internal clock speed of an integrated circuit A system and methods to transfer data between a testing interface and an IC. The system may include a synchronization subsystem to monitor the transitions of the test interface clock and/or IC clock to determine a clock adjustment appropriate to substantially synchronize the clocks. In certain implementations, a synchronization unit ... 08/09/07 - 20070186131 - Low cost imbedded load board diagnostic test fixture In a method and system for testing an intermediary device, a tester provides a test signal to a device under test (DUT) via a first circuit path on the intermediary device. A first response is received from the DUT to verify that the DUT and the first circuit path are ... 08/02/07 - 20070180339 - Handling mixed-mode content in a stream of test results In one embodiment, a system for formatting test data is provided with at least one data formatter to i) upon receiving notifications of test events, retrieve test data from a data store, and ii) generate a number of test records based on the test data. The system is also provided ... 08/02/07 - 20070180338 - Antenna reconfiguration verification and validation A method of testing the electrical functionality of an optically controlled switch in a reconfigurable antenna is provided. The method includes configuring one or more conductive paths between one or more feed points and one or more test point with switches in the reconfigurable antenna. Applying one or more test ... 07/19/07 - 20070168796 - On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In ... 07/19/07 - 20070168795 - On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In ... 07/19/07 - 20070168794 - Memory with element redundancy A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one embodiment of the present invention has primary and redundant elements. A register is used for each redundant element to store the address of a ... 07/19/07 - 20070168792 - Method to reduce leakage within a sequential network and latch circuit A method to reduce leakage within a sequential network comprising at least one latch and a combinatorial logic proximate to said latch, by applying an input vector on said sequential network during idle mode is described, the method comprising the steps of: overriding a static feedback of a latch comprising ... 07/19/07 - 20070168791 - Circuit and method for testing embedded phase-locked loop circuit In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL ... 07/19/07 - 20070168790 - Apparatus and method for reducing test resources in testing drams An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. ... 07/19/07 - 20070168789 - Queuing methods for distributing programs for producing test data Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and ... 07/19/07 - 20070168788 - Detector in parallel with a logic component One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a ... 07/19/07 - 20070168787 - Interace circuit for using a low voltage logic tester to test a high voltage ic The present invention provides an interface circuit for using a low voltage logic tester to test a high voltage IC. The interface circuit is between the high voltage IC and the low voltage logic tester, and is used for converting each output of the high voltage IC to a voltage ... 07/19/07 - 20070168786 - Method and apparatus for soft-error immune and self-correcting latches A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit ... 07/19/07 - 20070168785 - Virtual concatenation sequence mismatch defect detection Methods and apparatus for identifying sequence mismatch defects associated with members of a virtual concatenation (VCAT) group are disclosed. According to one aspect of the present invention, a method for detecting sequence mismatch defects associated with a VCAT group that substantially terminates at a VCAT sink includes obtaining a first ... 07/12/07 - 20070162801 - Wireless radio frequency technique design and method for testing of integrated circuits and wafers Various embodiments are described herein for an apparatus and method for the wireless testing of Integrated Circuits and wafers. In one embodiment, the apparatus comprises a test unit external from the wafer and at least one test circuit that is fabricated on the wafer that contains the Integrated Circuit. The ... 07/12/07 - 20070162800 - Semiconductor test system There are included a mother board (11), which has therein a multiplexer and a test pass/fail determining part, and a daughter board (12) that has therein an A/D converting part and an averaging part. The mother board (11) multiplexes a plurality of analog signals outputted from a plurality of output ... 07/12/07 - 20070162799 - Burn-in test signal generating circuit and burn-in testing method A burn-in test signal path is provided in parallel with an ordinary signal path with respect to an analog circuit. A signal waveform converting circuit for converting a burn-in test signal of a digital waveform into a burn-in test signal of an analog waveform is provided in the burn-in test ... 07/12/07 - 20070162798 - Single event upset error detection within an integrated circuit An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the ... 07/12/07 - 20070162797 - Test device and method for testing electronic devices A method for testing electronic devices, and to a test device that is, for test purposes, configured to be connected to an electronic system instead of an electronic device is disclosed. In one embodiment, the device includes at least one means for supplying a signal supplied by the electronic system ... 07/12/07 - 20070162796 - Method and portable device for testing electronic device Portable device capable of testing an electronic device is disclosed. An embodiment of a portable device comprises a memory device and a processing unit. The memory device stores a test program describing a test flow including a series of test instructions. The processing unit, coupled to the memory device, acquires ... 07/05/07 - 20070157057 - Digital jitter detector In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic ... 07/05/07 - 20070157056 - Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits ... 07/05/07 - 20070157055 - Detection of tap register characteristics According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first data. Next, it is determined whether the ... 06/21/07 - 20070143651 - Systems and methods for providing output data in an lbist system having a limited number of output ports Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry coupled to target logic under test, where the test circuitry is configured to perform logic tests on the target logic ... 05/31/07 - 20070124632 - Touch sensing apparatus A touch sensing apparatus is provided. The apparatus includes a sensor (13), a flip-flop (16), and a microcontroller unit (17). The sensor is connected to one of input of the flip-flop for receiving electricity signals from an object that touches the sensor. The MCU respectively supplies two AC signals at ... 05/31/07 - 20070124631 - Bit field selection instruction A digital signal processor having a generalized bit field extraction instruction which can be used to perform a bit field selection operation, a rotate left operation, a rotate right operation, a shift left operation, a logical shift right operation, an arithmetic shift right operation, and so forth. ... 05/17/07 - 20070113127 - Circuit design system and circuit design program A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class Gi from the netlist; a judgment module configured to select a target node out of a plurality of nodes Ni1 to Niji included in the equivalent ... 05/17/07 - 20070113126 - Testing and recovery in a multilayer device Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within ... 05/17/07 - 20070113125 - System and method for testing a serial port An exemplary system for testing a serial port includes a serial port (106), a female cable connector (108) connected to the serial port, and an optical-coupled chip (110) connected to the female cable connector. The serial port, the female cable connector and the optical-coupled chip collectively form a circular loop. ... 05/17/07 - 20070113124 - Method of testing integrated circuit and apparatus therefor In a method of testing integrated circuit (IC), a personal computer host and related software and hardware are used to constitute a system for conducting and controlling IC test. The method includes the steps of: (a) starting the test and using the computer host to drive a loading-unloading device to ... 05/17/07 - 20070113123 - Method and system for network-on-chip and other integrated circuit architectures A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an ... 05/03/07 - 20070101220 - Systems and methods for accessing input/output devices Systems and methods are provided for a hardware access tool to access a computer input/output (I/O) device coupled to a standard I/O bus on a host computer system. Upon receiving a standard I/O bus command, the hardware access tool translates the bus command on-the-fly for operation on a selected I/O ... 05/03/07 - 20070101219 - Semiconductor testing apparatus and method of calibrating the same A calibration method and a semiconductor testing apparatus, including N drivers, N being a natural number no less than two, at least one transmission path coupled to at least one of the N drivers, at least one calibration board coupled to the at least one transmission path, N comparators, and ... 05/03/07 - 20070101218 - Shift register system and method for driving a shift register system An exemplary shift register system (200) includes a counter (270), a shift register (210), a level shifter (220), and a plurality of switches (231-234). The counter includes a signal receiving pin connecting to a first external circuit, a pulse output pin, and a number of signal output pins. The shift ... 05/03/07 - 20070101217 - Serial data input/output method and apparatus A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively ... 05/03/07 - 20070101216 - Method to locate logic errors and defects in digital circuits When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more ... 05/03/07 - 20070101215 - Automated device testing using intertwined stimulus-generation and response validation specifications for managing dut's that generate out-of-order responses An intertwined test specification (ITTS) is used for controlling Automated Test Equipment (ATE) to apply a sequence of stimulus signals to a device under test (DUT) during a stimulus run and to validate returned response signals during a validation run. The ITTS has response validation scripts intertwined with stimulus invoking ... 05/03/07 - 20070101214 - Self-testing apparatus with controllable environmental stress screening (ess) Systems and methods associated with a self-testing module are described. The module may self control an environmental stress screen (ESS) apparatus and a self-test. One exemplary system includes a substitution test apparatus configured to hold a unit under test (UUT) configured with a self-test logic. The substitution test apparatus facilitates ... 04/26/07 - 20070094558 - Apparatus and method for testing an ieee1394 port An apparatus for testing an IEEE1394 port of a motherboard test device includes an IEEE1394 connector, a cable transceiver arbiter connected to the IEEE1394 connector, a first converting chip connected to the cable transceiver arbiter, a second converting chip connected to the first converting chip, and a flash chip connected ... 04/26/07 - 20070094557 - Semiconductor integrated circuit tester A semiconductor integrated circuit tester includes a host computer having a parallel data bus segment, a test head including at least one instrument having a parallel data bus segment, a first network bridge interfacing the data bus segment of the host computer to a switched serial network, and a second ... 04/26/07 - 20070094556 - Methods for distributing programs for generating test data Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. ... 04/19/07 - 20070088998 - Serializer/deserializer circuit for jitter sensitivity characterization Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, ... 04/19/07 - 20070088997 - Generation and self-synchronizing detection of sequences using addressable memories Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can ... 04/19/07 - 20070088996 - Test device and method for circuit device and manufacturing method for the same A test device that makes a test of a circuit device including a plurality of modules being substitutable in terms of function for one another, and in which a function change can be made for assignment to each of the modules based on an incoming control signal. The test device ... 04/19/07 - 20070088995 - System including a buffered memory module According to embodiments, a system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory ... 04/19/07 - 20070088994 - Electronic device testing system, method, and control device utilized in same An exemplary testing system (10) for testing an electronic device (300) under test includes a testing device (100) and a control device (200). The electronic device under test includes a transmitting element (320) and a keyboard (340). The testing device generates and sends instructions. The control device is connected to ... 04/12/07 - 20070083801 - Test apparatus, program and recording medium There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of the corresponding output pin and a slave channel provided in correspondence to a different output pin from that of ... 04/05/07 - 20070079190 - Product reliability analysis In one embodiment, a first set of inputs which describe aspects of a device may be received. A second set of inputs may be automatically provided for a group of assessments, included in an analysis, based on the first set of inputs and information in at least one database. An ... 04/05/07 - 20070079189 - Method and system for generating a global test plan and identifying test requirements in a storage system environment The present invention is directed to a system and method for a quality assurance tool generating test plans and identifying new test requirements for a new version of a product. Old versions of the product may be previously tested and test plan documents associated with previously tested versions of the ... 04/05/07 - 20070079188 - Signal integrity self-test architecture A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module, wherein the at least one module incorporates at least one associated module monitor suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module. ... 03/15/07 - 20070061643 - Substrate and testing method thereof The present invention relates to a substrate and testing method thereof. The method of the invention comprises: (a) providing a substrate, the substrate having a first surface and a second surface, the first surface having a plurality of first testing pads and the second surface having a plurality of second ... 03/15/07 - 20070061642 - System and method of uncorrelated code hopping in a communications system A system and method are used to provide uncorrelated code hopping in a communications system. A multi-bit linear shift register receives data and clocks the data fifteen times. A word assembler receives the shifted data and outputs a fifteen bit word. A mixer mixes the fifteen bit word with an ... 03/15/07 - 20070061641 - Apparatus and method for generating test driver Provided are an apparatus and method for generating a test driver, capable of reducing errors caused in component development early on by enabling immediate checking as to whether architecture design requirements are satisfied during component development. Specific snapshot information is input to the interface for the individual component of the ... 03/15/07 - 20070061640 - Integrated circuit tester with software-scaleable channels An integrated circuit (IC) tester for testing an IC device under test (DUT) includes a set of scaleable channels and a pattern generator for supplying control data to each scaleable channel prior to each test cycle. Under software control, each scaleable channel can implement one or more tester channels by ... 03/01/07 - 20070050692 - Test mode control circuit Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test ... 03/01/07 - 20070050691 - Single event functional interrupt detection system A method for detecting a single event functional interrupt for an electronic circuit is provided. The method involves periodically generating a refresh signal for the electronic circuit, and generating a single event functional interrupt indicator signal in the electronic circuit that is responsive to the refresh signal. The method also ... 02/22/07 - 20070043988 - Configurable voltage regulator A production testing system for testing an integrated circuit comprises a control module that generates a setpoint and a setpoint range. A configurable integrated circuit receives the setpoint and the setpoint range, that has M predetermined configurations, and generates N successive output signals by sequentially selecting N ones of M ... 02/22/07 - 20070043987 - Configurable voltage regulator A testing system comprises a configurable integrated circuit that has M predetermined configurations that are selected based upon an input signal. The configurable integrated circuit generates a selected one of M discrete values of an output characteristic of the configurable integrated circuit based on the selected one of the M ... 02/22/07 - 20070043986 - Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit An electronic circuit comprises a plurality of configurable cells configured according to a chaining command signal. These configurable cells are configured either in a chained state in which the configurable cells are functionally connected in a chain to form a shift register, if the chaining command signal is in a ... 02/22/07 - 20070043985 - Memory control method and memory controller In order to provide a memory control method and a memory controller, which can prevent an extra access even when a transfer frequency is uncertain, a memory access control method according to the invention is a method of controlling continuous transfers from a master connected to a system bus to ... 02/15/07 - 20070038908 - Design data structure for semiconductor integrated circuit and apparatus and method for designing the same Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of ... 02/08/07 - 20070033458 - Diagnostic method and apparatus for non-destructively observing latch data The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for ... 02/08/07 - 20070033457 - Circuit board and method for manufacturing the same A circuit board and a method of manufacturing the same are disclosed. Embodiments of the circuit board may include a dielectric substrate, a first via structure comprising a first via-hole, which is defined through the dielectric substrate, and a plurality of first vias that are formed on an inner wall ... 02/08/07 - 20070033456 - Integrated circuit test system and associated methods An integrated circuit chip test system comprises a reference chip adapted to generate original test data, and a test target chip adapted to receive and process the original test data to produce processed test data. The test target chip returns the processed test data to the reference chip, and the ... 02/08/07 - 20070033455 - Load testing of a telecommunication network A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with the load test being divided into several test phases and on the graphical user interface functionalities being ... 02/08/07 - 20070033454 - Method and apparatus for securing communications ports in an electronic device An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode. ... 02/08/07 - 20070033453 - Test of ram address decoder for resistive open defects A new test pattern which consists of performing “very small jumps” and “very big jumps” within the matrix. The “very small jumps” are controlled by the row decoder, and have the effect of sensitizing the resistive open defects which lead to slow-to-fall behavior in the word line. A “very small ... 01/25/07 - 20070022337 - Method and apparatus to verify non-deterministic results in an efficient random manner The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a device under test. Such random accesses may more closely resemble actual accesses to the registers of a device during ... 01/25/07 - 20070022336 - Digital storage element with enable signal gating A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional ... 01/18/07 - 20070016833 - Method for performing built-in and at-speed test in system-on-chip A method for performing a built-in and at-speed test in a system-on-chip includes receiving a statistic timing analysis report of the system-on-chip, determining a plurality of critical paths for an at-speed test in the system-on-chip according to the statistic timing analysis report, analyzing signals at observe control points and capture ... 01/11/07 - 20070011522 - System and methods for functional testing of embedded processor-based systems Functional testing of an embedded system is performed by a test control system that implements a peripheral emulation module to interface with an externally accessible port of the embedded system. The test control system implements a test generation processor that operates to autonomously resolve abstracted component templates and embedded system ... 01/11/07 - 20070011521 - Integrated scannable interface for testing memory An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal ... 01/11/07 - 20070011520 - Element substrate, test method for element substrate, and manufacturing method for semiconductor device A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a ... 01/11/07 - 20070011519 - Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an ... 01/11/07 - 20070011518 - Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a ... 01/11/07 - 20070011517 - Debug system for data tracking Some embodiments provide configuration of an internal monitoring mechanism of a processing device to output first data associated with a predetermined operational state of the processing device, and loading of control code into the processing device. The control code may be executable by the processing device to output second data ... 01/11/07 - 20070011516 - Method and apparatus to launch write queue read data in a microprocessor recovery unit A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The ... 01/11/07 - 20070011515 - System and method for evaluating an expression in a debugger When an expression is first entered into a debugger, the expression may be automatically evaluated. Later, when the debugger detects an action that causes the value of the expression to become stale, the expression may be reevaluated with a setting to disable the automatic reevaluation of certain designated disabled expressions. ... 01/11/07 - 20070011514 - Data compression A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including “care” bits and “don't care” bits. The test vector data is then compressed by comparing corresponding ... 12/14/06 - 20060282726 - Semiconductor device, and apparatus and method for supporting design of semiconductor device A semiconductor device includes a logic circuit section having a plurality of logic circuits and configured to achieve a predetermined logical function; and a probing circuit connected with the logic circuit section. The probing circuit is not related to the predetermined logical function and comprises a diffusion layer used in ... 12/14/06 - 20060282725 - Electronic switching circuit, switching circuit test arrangement and method for determining the operativiness of an electronic switching circuit The invention relates to an electronic switching circuit in which a plurality of test circuit blocks is provided, whereby every test circuit block comprises a first sub-circuit block and at least one second sub-circuit block. A field effect transistor in the first sub-circuit block has a gate insulation layer that ... 12/14/06 - 20060282724 - Programmatically switched hot-plug pci slots Electrically decoupling circuit boards, such as PCI cards, from a backplane bus without physically removing the circuit boards from backplane connectors is disclosed. A microprocessor controls the state of electrically controlled switches that control the application of power to the power terminals of backplane connectors. Optionally, manually operated switches also ... 12/14/06 - 20060282723 - Topology-independent calibration system A topology-independent calibration system (“TICS”) within a test system is disclosed. The TICS may include a netlist, a path correction module, and a processor in signal communication with the path correction module. ... 12/14/06 - 20060282722 - Loop-back memory-module extender card for self-testing fully-buffered memory modules A loop-back extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. An Advanced Memory Buffer (AMB) on the memory module fully buffers DRAM chips on the memory module. The AMB ... 12/14/06 - 20060282721 - Semiconductor integrated circuit, and semiconductor system including that semiconductor integrated circuit For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination ... 11/16/06 - 20060259837 - Safety device A safety device of the invention includes at least one of an input unit having one or more input terminals and an output unit having one or more output terminals, a testing unit having one or more test terminals, a rewritable nonvolatile memory configured to store setting information of a ... 11/16/06 - 20060259836 - Method for validating an integrated circuit and related semiconductor product thereof A method for converting an integrated circuit into a test circuit for validating functionality of the integrated circuit is disclosed. The integrated circuit is formed on a wafer, and includes a first inner node and a second inner node, wherein the first and second nodes are not floating. The method ... 11/16/06 - 20060259835 - Automatic test pattern generation A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From ... 11/09/06 - 20060253752 - Parallel input/output self-test circuit and method A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-0 to 104-N) that provide a received test data to logic adjust circuits (106-0 to 106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to ... 11/09/06 - 20060253751 - Method and system for improving quality of a circuit through non-functional test pattern identification The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected ... 11/02/06 - 20060248417 - Clock control circuit for test that facilitates an at speed structural test A clock selection circuit selectively passes one or more clocks into portions of an integrated circuit for testing. In one mode, the selection circuit passes a functional clock into a section of logic for an at speed test under test program control. In another mode, the selection circuit passes a ... 10/26/06 - 20060242503 - Integrated circuit test system A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by ... 10/26/06 - 20060242502 - Method and apparatus for broadcasting scan patterns in a random access scan based integrated circuit A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network ... 10/26/06 - 20060242501 - Communication interface for diagnostic circuits of an integrated circuit An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals. ... 10/26/06 - 20060242500 - 1149.1tap linking modules IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 ... 10/26/06 - 20060242499 - Remote integrated circuit testing method and apparatus A method and system for remotely testing an integrated circuit installed in an integrated circuit system is presented. The integrated circuit is equipped with test structures for testing functional blocks within the integrated circuit, and a test access mechanism configured to receive test vectors for controlling the test structures. Test ... 10/26/06 - 20060242498 - Digital system and method for testing analogue and mixed-signal circuits or systems A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied ... 10/19/06 - 20060236175 - Semiconductor integrated circuit device and i/o cell for the same In a semiconductor integrated circuit device in which a plurality of I/O cells having level shift circuits are placed in an I/O region, two input/output cells respectively have four level shift circuits 11, 12a to 12c. A power supply cell, originally including only wiring for supply of a power supply ... 10/19/06 - 20060236174 - Optimized jtag interface An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used ... 10/19/06 - 20060236173 - Method and system for configuring registers in microcontrollers, and corresponding computer-program product A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the ... 10/19/06 - 20060236172 - Semiconductor device and method for testing the same On a semiconductor wafer 10, semiconductor chip regions 12 including a semiconductor integrated circuit, a scribe line 14 formed adjacent to the semiconductor chip region 12, a test device 18 formed in the scribe line 14, electrically separated from the semiconductor circuit in the semiconductor chip region 12, for controlling ... 10/19/06 - 20060236171 - Method for detecting and correcting errors of electronic apparatus A method for detecting and correcting the error of an electronic apparatus is provided. An embedded controller whose power is independently supplied is used to detect and store the error code from the internal devices of the electronic apparatus. First, the error status of the electronic apparatus is detected to ... 10/19/06 - 20060236170 - On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In ... 10/19/06 - 20060236169 - Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second ... 10/19/06 - 20060236168 - System and method for dynamically optimizing performance and reliability of redundant processing systems An improved system and method for dynamically optimizing the performance and reliability of redundant processing systems (e.g., for use in space applications) are disclosed. As one example, a Field Programmable Gate Array (FPGA) that includes a plurality of processors is disclosed. Based on mission specific modes or environmental conditions, the ... 10/19/06 - 20060236167 - Compilation of calibration information for plural testflows In one embodiment, a selection of plural testflows is first obtained. Each testflow specifies how automated test equipment (ATE) should test at least one device. Calibration information is then identified for each of the testflows, and redundancies in the identified calibration information are eliminated to compile a set of non-redundant ... 09/28/06 - 20060218454 - Circuit automatic generation apparatus and method A circuit automatic generation apparatus includes storage means 4 for retaining input/output information of each function circuit and circuit information to which the function circuit is connected, test mode generation specifications for generating a test mode signal, test specifications added to the function circuit, terminal test specifications for specifying the ... 09/21/06 - 20060212766 - Display device and driving method thereof A display device includes an insulating substrate, a plurality of gate lines formed on the insulating substrate, a plurality of data lines across the gate lines, a plurality of pixels connected to the gate lines and the data lines, a data driver providing data voltages to the pixels, a first ... 09/21/06 - 20060212765 - Integrated circuit with a control input that can be disabled An integrated circuit comprises a control unit, a plurality of control inputs for the provision of control signals to said control unit and a deactivation circuit for disabling the provision of at least one of said control signals. After reception of a first coded message by said integrated circuit the ... 09/07/06 - 20060200717 - Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a second test operation is ... 09/07/06 - 20060200716 - Skewed inverter delay line for use in measuring critical paths in an integrated circuit An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay ... 09/07/06 - 20060200715 - Automatically detecting and routing of test signals A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths (240, 242, 244). According to an example embodiment of the present invention, a microcontroller (205) is programmed to monitor input nodes (210) using an interrupt routine for automatically ... 08/31/06 - 20060195736 - Electro-optical device An electro-optical device includes a substrate, a plurality of unit circuits that includes a plurality of scanning lines, a plurality of data lines and electro-optical elements provided corresponding to intersecting regions of the scanning lines and the data lines and is formed in a display region of the substrate, a ... 08/31/06 - 20060195735 - Circuit for distributing a test signal applied to a pad of an electronic device The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the ... 08/31/06 - 20060195734 - Semiconductor memory device and stress testing method thereof A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power ... 08/31/06 - 20060195733 - Arc fault and ground fault circuit interrupter tester apparatus and method A circuit tester comprising an AFCI (FIGS. 1 and 2) having two pairs of leads connected to the opposite end of each circuit tester in series for connecting an AFCI with ground fault circuit technology capabilities between an electrical circuit load and a power source to indicate electrical circuit and/or ... 08/31/06 - 20060195732 - Method and system for executing test cases for a device under verification The present invention relates to a method and system for executing test cases for a device by mapping sequences of instructions and/or operation into a data flow graph, which data flow graph includes a plurality of nodes (20) and a plurality of arcs (22) connecting the nodes (20). The method ... 08/24/06 - 20060190783 - On-chip high-speed serial data analyzers, systems, and associated methods In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined voltage to produce analysis data, and capturing the ... 08/24/06 - 20060190782 - Mechanism to provide test access to third-party macro circuits embedded in an asic (application-specific integrated circuit) Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the ... 08/24/06 - 20060190781 - Clock control circuit for test that facilitates an at speed structural test When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a ... 08/17/06 - 20060184847 - Semiconductor device tested using minimum pins and methods of testing the same The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in ... 08/10/06 - 20060179372 - Signal drive de-emphasis control for serial bus Transmitting a transition between high and low states across a lengthy conductor with a main transmitter to transmit data, providing emphasis with an emphasis transmitter to strengthen the transmission of the transition, transmitting a low-to-high transition to test for the absence of an electronic device coupled to the lengthy conductor, ... 08/03/06 - 20060174174 - Method, system, and storage medium for estimating and improving test case generation A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions ... 08/03/06 - 20060174173 - Built-in test circuit for an integrated circuit device An integrated circuit device can be tested using a built-in test circuit, in the IC device, that tests the operation of an I/O cell. The built-in test circuit includes a pattern generator for generating a series of simulation signals. The built-in test circuit successively stores and retrieves the simulation signals ... 07/27/06 - 20060168489 - System and shadow circuits with output joining circuit In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal ... 07/13/06 - 20060156115 - Device, system, and method for providing error information in xht network A device, a system, and a method for displaying error information within an expandable Home Theater (XHT) network, and more particularly, to a device, a system, and a method for providing error information within the XHT network by displaying error information of slave devices in the XHT network to a ... 07/13/06 - 20060156114 - Semiconductor device for accurate measurement of time parameters in operation A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit, which includes an input/output selector with test function. A test clock signal, TCLK, directly supplied in the test mode, is used to selectively take in one of input signals DI<k:0>, COM<i:0> and ... 07/13/06 - 20060156113 - Reduced signaling interface method & apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a ... 07/13/06 - 20060156112 - Reduced signaling interface method & apparatus This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a ... 07/13/06 - 20060156111 - Test circuit and display device having the same A test circuit and a test method capable of easily and accurately determining the presence or absence of a defect as well as defective points. The test circuit of the invention has a plurality of shift registers, a plurality of latch circuits, a plurality of first NOR circuits, a plurality ... 07/13/06 - 20060156110 - Method for testing semiconductor chips using register sets A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register ... 07/13/06 - 20060156109 - Test mode circuit and reset control method therefor A power control circuit is provided in a vehicle control ECU mounted in a vehicle. The control circuit, when making a shift to a test mode by a test mode circuit, closes a relay to supply a power voltage from a battery to a power line in the similar manner ... 07/13/06 - 20060156108 - Method for testing semiconductor chips using check bits A method for testing semiconductor chips is disclosed. A chip to be tested has a test logic, at least one test mode is set in the form of a serial first bit string, the test modes are executed in the chip and test results or the status of the test ... 07/13/06 - 20060156107 - Method for testing semiconductor chips by means of bit masks A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the ... 07/13/06 - 20060156106 - Test system A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test target system such as a logic circuit is tested, data of the ... 07/13/06 - 20060156105 - Data receiving apparatus capable of compensating for reduced timing margin caused by inter-symbol interference and method thereof Provided are a data receiving apparatus that can determine data by adjusting a reference level for determining a logic value of inputted data based on Inter-Symbol Interference in a data signal inputted through a transmission line, and receive the data without errors by compensating for timing margin decrease caused by ... 07/13/06 - 20060156104 - Wrapper testing circuits and method thereof for system-on-a-chip A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; ... 07/13/06 - 20060156103 - Apparatus and method for bit pattern learning and computer product A computer calculates bit patterns of syndromes for all candidate bit patterns of reception words that are input in ECC-EOR circuits of a logic circuit. The bit patterns of the syndromes are stored as possible bit patterns. Request bit patterns are propagated when an error occurs, and are allocated to ... 07/13/06 - 20060156102 - System and method to control data capture One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store ... 07/13/06 - 20060156101 - Method and system for testing distributed logic circuitry A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing procedure utilizes enabling one of a plurality of independent programmable ... 07/13/06 - 20060156100 - Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is ... 07/13/06 - 20060156099 - Method and system of using a single ejtag interface for multiple tap controllers Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single ... 07/13/06 - 20060156098 - Method and apparatus for testing an electronic device An apparatus for testing an electronic device is provided. More specifically, there is provided a method comprising placing a first integrated circuit into a test mode, wherein the first integrated circuit is coupled to a conductive interconnect, causing a register assembly located on the first integrated circuit to transmit a ... 07/13/06 - 20060156097 - Analog counter using memory cell A non-volatile memory may include at least one cell that functions as an analog counter. In one embodiment, the counter may count the number of cycles experienced by the memory and provide an indication when a predetermined number of cycles have been completed. The completion of the given number of ... 07/13/06 - 20060156096 - Voltage converting device, computer readable recording medium with program recorded thereon for causing computer to execute failure processing, and failure processing method A control device detects whether or not an up-converter fails, based on a DC voltage from a voltage sensor, an output voltage from a voltage sensor, and a duty ratio in controlling switching of NPN transistors. If a failure in the up-converter is detected, the control device then controls an ... 07/06/06 - 20060150040 - Systems and methods for reconfiguring scan chains Systems and methods for reconfiguring scan chains are provided. A representative system incorporates a first scan chain of flip-flops operative in either a normal mode or a rotate mode such that, if the first scan chain is operative in the normal mode, inputs are provided to the flip-flops in sequential ... 07/06/06 - 20060150039 - Input circuit for an integrated circuit The invention relates to an integrated circuit comprising: a functional circuit; a setting memory for storing a setting data item; an input circuit for receiving signals via an input terminal, the input circuit comprising a first receiving circuit having first hysteresis and a second receiving circuit having second hysteresis; the ... 06/22/06 - 20060136794 - Computer peripheral connecting interface system configuration debugging method and system A computer peripheral connecting interface system configuration debugging method and system is proposed, which is designed for use in conjunction with a computer platform that is equipped with a particular type of peripheral connecting interface, such as a PCI (Peripheral Component Interconnect) interface, for automatically finding errors in the PCI ... 06/08/06 - 20060123293 - Organic light emitting display Disclosed is an organic light emitting display which has a scan driver to supply scan signals to a plurality of scan lines, a data driver to supply data signal to output lines, with a demultiplexer on each output line to supply the data signal to a plurality of data lines ... 06/08/06 - 20060123292 - Method and apparatus for multiplexing an integrated circuit pin A system and method for multiplexing an integrated circuit pin include a plurality of registers for storing bit values; a plurality of functions to be multiplexed on receiving the bit values; a decoding logic for decoding the bit values for selecting at least one of the functions; a plurality of ... 06/08/06 - 20060123291 - Parallel compression test circuit of memory device A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input/output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input/output amplification control unit for activating a plurality of input/output amplifiers connected to a selected ... 06/08/06 - 20060123290 - Serial data preservation method A timer circuit for tracking an elapsed time of an electronic device is provided. The timer circuit compares differences in elapsed times written to memory addresses of a memory chip with a periodic interval to determine whether any elapsed times written to the memory chip is corrupt. If so, then ... 06/08/06 - 20060123289 - Method and apparatus for testing a transmission path One embodiment of the invention provides apparatus and a method for testing a transmission path across one or more printed circuit boards. According to the method, a test signal is presented at a first location on the transmission path. The test signal is generally low frequency compared to normal data ... 06/08/06 - 20060123288 - Generation of test vectors for testing electronic circuits taking into account of defect probability A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The ... 06/08/06 - 20060123287 - Curve tracing device and method A curve tracing method comprising simultaneously connecting a test IC sample and a reference IC sample to a switchboard; and selectively connecting a scanning voltage output or a sensing input of a curve tracer unit to each of the pins of the test IC sample and the reference IC sample ... 06/01/06 - 20060117233 - System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both ... 06/01/06 - 20060117232 - Testing device and method for an integrated circuit An apparatus and method are provided for testing integrated circuits. An integrated circuit arrangement is provided having first and second dice. Each die has circuitry for diagnostic testing in response to a diagnostic test signal. The circuitry further defines an input for receiving the diagnostic test signal and an output ... 05/18/06 - 20060107141 - Database mining system and method for coverage analysis of functional verification of integrated circuit designs Database mining, analysis and optimization techniques in conjunction with the model-based functional coverage analysis are used to turn raw verification and coverage data into design intelligence (DI) and verification intelligence (VI). The required data and attributes are automatically extracted from verification, simulation and coverage analysis databases. Design finite state machine ... 05/18/06 - 20060107140 - Semiconductor device with termination resistor circuit A semiconductor device includes a signal line, a test load circuit and a termination circuit. The signal line is connected with an input/output node of the semiconductor device. The test load circuit has a test resistor and is provided between the signal line and a first one of power lines ... 05/18/06 - 20060107139 - Sequential control circuit A sequential control circuit operates according to an input signal. When the input signal is determined at a first state, the sequential control circuit asserts a plurality of control signals in a predetermined sequence. When the input signal is determined at a second state, the sequential control circuit de-asserts the ... 05/18/06 - 20060107138 - Transceiver module A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC ... 05/18/06 - 20060107137 - Chip testing methods and chips Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second operating frequency. The first operating frequency is ... 04/27/06 - 20060090110 - Connecting multiple test access port controllers on a single test access port Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along ... 04/27/06 - 20060090109 - On the fly configuration of electronic device with attachable sub-modules Electronic device (10) comprising a control unit (11), a plurality of slots (15) for attaching/connecting sub-modules (12, 13), and means (15, 16, 17) for interconnecting the control unit (11) with those sub-modules (12, 13) that are attached/connected to the slots (15). The control unit (11) is capable of issuing commands ... 04/20/06 - 20060085706 - High speed on chip testing A selectively enabled clock doubler. An XOR gate receives a first signal on a first input and a second signal on a second input, and provides a third signal on an output. The first signal is a clock signal having a first frequency. A delay circuit receives the clock signal ... 04/13/06 - 20060080582 - Semiconductor test management system and method A system and method thereof for semiconductor test management. A first computer generates a new gating rule and transmits the new gating rule. A second computer receives the new gating rule via a network, acquires a test result, carries the test result into the new gating rule to generate an ... 03/30/06 - 20060069971 - Method and apparatus for deferred decision signal quality analysis A signal analysis circuit includes a sampling circuit operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal ... 03/30/06 - 20060069970 - Method and system for computer based testing using an amalgamated resource file A system for computer-based testing for producing a test and delivering the test to an examinee includes a storage device that has a first storage location, which stores a first segment of a test definition language, and a second storage location, which stores a second segment of the test definition ... 03/30/06 - 20060069969 - Inversion based stimulus generation for device testing A device testing apparatus and method for testing a semiconductor device is provided. For device testing, stimulus data is generated and provided to the semiconductor device, and output data of the semiconductor device is then evaluated to verify proper operation of the semiconductor device. Further, data in the semiconductor device ... 03/30/06 - 20060069968 - Built-in self test circuitry for process monitor circuit for rapidchip and asic devices A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured ... 03/30/06 - 20060069967 - System for measuring characteristics of a digital signal An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response ... 03/23/06 - 20060064613 - Dual mode test access port method and apparatus Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal ... 03/23/06 - 20060064612 - Integrated circuit arrangement, integrated circuit, matrix array of circuits and electronic device An IC arrangement (200) has a plurality of IC modules (220a, 220b), the individual IC modules (220a, 220b) being coupled between a first power line (202) and a second power line (204) via a voltage generator (240a, 240b). The voltage generators (240a, 240b) are powered via the first power line ... 03/09/06 - 20060053355 - Semiconductor integrated circuit device A semiconductor integrated circuit device has: a plurality of macro circuits; and a plurality of decoders configured to supply a test enable signal to the plurality of macro circuits. Each decoder is provided with respect to a corresponding predetermined number of macro circuits of the plurality of macro circuits. ... 03/02/06 - 20060048027 - Semiconductor device A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit ... 03/02/06 - 20060048026 - Clustering-based approach for coverage-directed test generation A coverage-directed test generation technique for functional design verification relies on events that are clustered according to similarities in the way that the events are stimulated in a simulation environment, not necessarily related to the semantics of the events. The set of directives generated by a coverage-directed test generation engine ... 03/02/06 - 20060048025 - Diagnostic data gathering apparatus and method Process data and video data as pertains to the operation of an item of equipment is received and temporarily captured and stored in a rolling window that includes a plurality of different points in time. Upon detecting a predetermined operating condition of interest with respect to the item of equipment, ... 03/02/06 - 20060048024 - Pattern types as constraints on generic type parameters A system and method for constraining generic types is disclosed. In brief, the subject invention provides a pattern type for defining a set of one or more parameter constraints. Rather than being confined to a predetermined set of hard-coded constraints in an execution engine, a pattern type can be specified ... 02/23/06 - 20060041805 - Array substrate, display device having the same, driving unit for driving the same and method of driving the same An array substrate of an N-line inversion type includes data lines, scan lines and pixels. A number of the data lines is ‘m’, and the data lines are extended in a first direction. A number of the scan lines is ‘n’, and the scan lines are extended in a second ... 02/23/06 - 20060041804 - Apparatus and method for testing semiconductor memory device A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local ... 02/23/06 - 20060041803 - Apparatus and method for dynamic in-circuit probing of field programmable gate arrays A dynamic probe system for probing a FPGA with at least one core. A trace core is added to the FPGA, the trace core in communication with a plurality of signal banks, each signal bank comprising a plurality of signals in the at least one core. A logic analyzer, in ... 02/23/06 - 20060041802 - Functional frequency testing of integrated circuits A method and circuits for testing an integrated circuit at functional lock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency. ... 02/23/06 - 20060041801 - Acceleration of the programming of a memory module with the aid of a boundary scan (bscan) register In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the ... 02/16/06 - 20060036919 - Embedded logic analyzer A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation ... 02/09/06 - 20060031728 - Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage elements, e.g., flip/flops, are coupled to combinational logic and are configured to have an additional port for receiving a scan mode signal. ... 02/09/06 - 20060031727 - Segmented algorithmic pattern generator A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in ... 02/02/06 - 20060026471 - Loop status monitoring apparatus A loop status monitoring apparatus monitors a status of an arbitration loop that includes a plurality of devices and a switch that controls connections between the devices, has at least one of loop status detection data, primitive detection data, and frame count data, and includes a failure detecting unit that ... 02/02/06 - 20060026470 - Processor debugging apparatus and processor debugging method A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register. ... 01/26/06 - 20060020861 - Method, system, and apparatus for loopback entry and exit A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback ... 01/26/06 - 20060020860 - Digital signature generation for hardware functional test A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each ... 01/19/06 - 20060015786 - System and shadow bistable circuits coupled to output joining circuit In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable ... 01/19/06 - 20060015785 - Test apparatus for mixed-signal semiconductor device A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture including a connection means, an option circuit for ... 01/05/06 - 20060005089 - Device and a process for the calibration of a semiconductor component test system, in particular of a probe card and/or of a semiconductor component test apparatus A device and a process for the calibration of a semi-conductor component test system The invention relates to a process and a device for the calibration of a probe card and/or of a semi-conductor component test apparatus, including a first connection, at which a corresponding signal, in particular a calibration ... 01/05/06 - 20060005088 - System and method for testing artificial memory A system for testing an artificial memory includes a monitor (10), a driver (20), and an executing means (30). The monitor includes a command line interface (101) for inputting commands and parameters. The driver includes a command line editor (201), which is adapted to be activated before the command line ... 12/29/05 - 20050289416 - Method and apparatus for performing multi-site integrated circuit device testing Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data ... 12/29/05 - 20050289415 - Intelligent probe chips/heads An intelligent probe chip or probe head can include design-for-test (DFT) circuitry that would otherwise be required in a device being tested and/or implement testing functions so that less-expensive automated test equipment (ATE) can test the device. ... 12/29/05 - 20050289414 - Lossless recovery for computer systems with remotely dependent data recovery An architecture and implementation for losslessly restarting subsystems in a distributed file system is described. By partitioning functionality and logging appropriately across the kernel and user-level boundaries on a client, the user-level subsystem may be made losslessly restartable. Practical mechanisms for supporting state-based recovery in replicated state machines and like ... 12/15/05 - 20050278593 - Scan-test structure having increased effectiveness and related systems and methods An integrated circuit comprises an input node operable to receive test data. First circuitry configurable as a first delay circuit is coupled to the node, operable to generate a first test signal by delaying the test data a first delay time and operable to generate a second test signal by ... 12/08/05 - 20050273682 - Match circuit for performing pattern recognition in a performance counter A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”) and logic for activating ... 12/08/05 - 20050273681 - System and method for testing nodes in a network A method and system for testing nodes in a network, where the network includes a plurality of nodes and at least one bus for coupling the plurality of nodes. The system includes a control processor for generating test commands to be sent to at least one node of the plurality ... 12/01/05 - 20050268189 - Device testing using multiple test kernels In a device testing arrangement, a data set is selected from a set of multiple data sets, and a test kernel is selected from a set of multiple test kernels. The test kernel includes one or more instructions that utilize data. The test kernel is executed with at least some ... 11/24/05 - 20050262408 - Fast min* - or max* - circuit in ldpc (low density parity check) decoder Fast min*− (min-star-minus) or max*− (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and ... 11/24/05 - 20050262407 - High frequency divider state correction circuit with data path correction The present invention provides for state correction. A first flip flop coupled to a second flip flop. A state correction circuit coupled to the output of the second flip flop. A third flip flop is coupled to the output of the state correction circuit. A fourth flip flop is coupled ... 11/24/05 - 20050262406 - High frequency divider state correction circuit The present invention provides for state correction. A first value in a state circuit is received from a flip flop. The received value is transmitted to a second flip flop. The received value within the second flip flop is altered if an error condition arises. The received value is transmitted ... 11/17/05 - 20050257108 - Access method for embedded jtag tap controller instruction registers Disclosed is an integrated circuit chip structure that has a chip level test access port (TAP) controller and a plurality of embedded TAPs connected to the chip level TAP. Because the embedded TAPs have instruction register (IR) lengths that differ from the chip level TAP IR, and the embedded TAP ... 11/03/05 - 20050246601 - Method and apparatus to measure and display data dependent eye diagrams A method and apparatus to draw eye diagrams of multi-valued signals that remove non-data dependent effects is disclosed. An exemplary method includes collecting event counts at variable bit offsets, desired time offsets within one or more bit periods and desired voltage offsets within a voltage region of interest; removing non-data ... 11/03/05 - 20050246600 - Device for protection against error injection into an asynchronous logic block of an elementary logic module A logic circuit comprises a logic module comprising a functional logic block supplying a functional result, and a functional flip-flop receiving the functional result and supplying a synchronous result. A module for checking the functional logic block comprises a checking logic block executing the same logic function as the functional ... 11/03/05 - 20050246599 - System and method for testing input and output characterization on an integrated circuit device A system for testing input characteristics of an integrated circuit device includes an integrated circuit device. The integrated circuit device includes, an input pad, an output pad, an input register, and a data register. The input register receives an input value from the input pad and communicates the input value ... 11/03/05 - 20050246598 - Voltage/process evaluation in semiconductors An evaluation circuit comprises a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured ... 10/27/05 - 20050240844 - Integrated circuit burn-in methods and apparatus Improved methods for performing burn-in of electronic components, such as integrated circuits (ICs) with on-board thermal sense circuits, are used to obtain a higher bin split. According to an embodiment, a thermal set-point is loaded into each IC. While the ICs are maintained at a constant elevated temperature, the burn-in ... 10/27/05 - 20050240843 - Method, computer program and device for deleting data sets contained in a data list from a table system A method for deleting data sets contained in a data list from a table system comprises the following steps, said steps being carried out for all data sets of said data list: reading one data set; checking whether said read data set has a specified property; if said data set ... 10/27/05 - 20050240842 - Circuit and method for testing semiconductor device A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes ... 10/27/05 - 20050240841 - Cross-platform test environment automatic setup method and system A cross-platform test environment automatic setup method and system is proposed, which is designed for use on an information platform that is running on a particular kind of operating system, for the purpose of providing the information platform with a cross-platform test environment automatic setup capability that allows a particular ... 10/27/05 - 20050240840 - Method and system for on demand selective rerouting of logical circuit data in a data network A method and system are provided for on demand selective rerouting of logical circuit data in a data network. Upon a failed logical circuit being identified in the data network, one or more alternative or logical failover circuits for rerouting data from the identified failed logical circuit is displayed in ... 10/27/05 - 20050240839 - Critical area computation of composite fault mechanisms using voronoi diagrams Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes ... 10/20/05 - 20050235181 - Auto-recovery wafer testing apparatus and wafer testing method Auto-recovery wafer testing apparatus and wafer testing method are provided. The wafer testing apparatus includes a main system, a tester and a real-time accessing module. The main system controls the process of the wafer testing. The tester is electrically coupled to the main system for receiving commands from the main ... 10/20/05 - 20050235180 - Integrated module having a plurality of separate substrates The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a parallel manner, and having a ... 10/20/05 - 20050235179 - Device for protection against error injection into a synchronous flip-flop of an elementary logic module A logic circuit comprises a logic module comprising a functional synchronous flip-flop receiving a functional result comprising several bits in parallel, and supplying a synchronous result. A module for checking the integrity of the functional flip-flop comprises a first coding block receiving the functional result and supplying a first code, ... 10/13/05 - 20050229055 - Interface circuit for a single logic input pin of an electronic system An interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine responsive to said sequence of logic values to switch the ... 10/13/05 - 20050229054 - Integrated circuit An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In ... 10/13/05 - 20050229053 - Circuit and method for low frequency testing of high frequency signal waveforms A method of deducing properties of the shape of a waveform comprises (a) generating a signal based on a periodic pattern of logic levels; (b) measuring a DC level that is proportional to the average level of the signal and a DC level that is proportional to the average of ... 10/13/05 - 20050229052 - Method, system and program product for autonomous error recovery for memory devices An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second ... 09/29/05 - 20050216804 - Semiconductor device and test method therefor A multichip package comprises first and second integrated circuits comprising internal cells serving as test objects. The first integrated circuit comprises internal input terminals connected to external terminals for testing, a division multiplexing circuit connected to the internal input terminals, and a first scan control circuit for controlling a scan ... 09/29/05 - 20050216803 - Integrated circuit device An LSI according to the present invention has a scan chain which comprises a plurality of SFFs between a buffer connected to an external pin and an internal circuit. During test mode, a test signal is inputted to the internal circuit of the LSI using the scan chain. In this ... 09/29/05 - 20050216802 - Tap time division multiplexing with scan test An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a ... 09/29/05 - 20050216801 - Latch and phase synchronization circuit using same A latch is provided for rapidly stabilizing a latching operation. The latch comprises a first latch circuit for latching a first signal in response to a first portion of a second signal to generate a first latch signal, and a latch error compensator for compensating a latch error in the ... 09/22/05 - 20050210348 - Microcomputer and method of testing same A microcomputer includes a memory such as a flash memory; a logical circuit such as a CPU; a test ROM storing a test program for testing at least the logical circuit; and recording means capable of storing, as a flag, the result of testing at least one of the memory ... 09/22/05 - 20050210347 - Integrated circuit The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register connected thereto which is coupled to a ... 09/22/05 - 20050210346 - Closed loop dynamic power management Closed loop dynamic power management is accomplished via a pass/fail detector executing test code in a chip to verify operation of the chip, and a voltage regulator working in a regulation loop with the pass/fail detector to regulate power by setting Vdd to a minimum allowable value for the chip. ... 09/22/05 - 20050210345 - System and method for increasing the speed of serially inputting data into a jtag-compliant device A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made the active instruction, extending the capability of the test access protocol (TAP) controller such that the TAP controller can ... 09/15/05 - 20050204224 - Programmable driver for an i/o pin of an integrated circuit A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the ... 09/15/05 - 20050204223 - Bonding pads for testing of a semiconductor device A first integrated circuit chip is provided for packaging along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and the second integrated circuit chips, wherein the first integrated circuit ... 09/15/05 - 20050204222 - Apparatus and method for eliminating the tms connection in a jtag procedure In a JTAG procedure, the electrical coupling normally dedicated to the TMS information is eliminated. Instead, the TDI line signals are reformatted into control packets and data packets. The control packets include one field that provides the TMS information. The control packets result in either the SHIFT DR state or ... 09/15/05 - 20050204221 - Apparatus and method for exchanging non-jtag signals with a core processor during selected jtag modes In selected JTAG states, the data input and output terminals are not used for several clock cycles. By recognizing the appropriate selected JTAG states and providing circuits to permit the transfer of non-JTAG data during these selected states, a more efficient use of the terminals which provide an interface between ... 09/15/05 - 20050204220 - Random number test circuit, random number generation circuit, semiconductor integrated circuit, ic card and information terminal device A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a ... 09/15/05 - 20050204219 - Method and device for testing array substrate A method and a device for testing an array substrate for a liquid crystal display that allow time for testing to be reduced are provided. An array substrate is divided into two test blocks, and two scanning signal lines in total, one from each of the test blocks, are selected ... 09/15/05 - 20050204218 - Operation mode setting circuit According to the present invention, there is provided an operation mode setting circuit comprising: a plurality of latch circuits each of which receives one of at least two bits contained in an operation mode setting signal for setting an operation mode, and latches and outputs the bit in synchronism with ... 09/15/05 - 20050204217 - Identical core testing using dedicated compare and mask circuitry Today large system-on-chips (SOC) are designed using predefined circuit functions commonly referred to as cores. In some cases, multiple instances of the same core may be implemented within an SOC to achieve greater functional performance of the SOC. Having multiple cores of the same type in an SOC lends itself ... 09/15/05 - 20050204216 - Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149.1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected to a pair of master sources. A second interface is connected to a ... 09/01/05 - 20050193296 - On-chip test apparatus Testing of on-chip test structures is accomplished by employing a test apparatus that allows test data to be uploaded into selected data latches associated with respective ones of a plurality of test structures. Tests are performed by selectively providing a test data from the data latch to the associated test ... 09/01/05 - 20050193295 - Tester channel count reduction using observe logic and pattern generator Test logic supports the testing of an electronic circuit, where the number of ports of the electronic circuit exceeds the number of available tester IO channels. In some examples, the test logic utilizes observe logic in order to analyze the output ports that are masked so that the number of ... 08/04/05 - 20050172187 - Signal pin tester for ac defects in integrated circuits A test apparatus and a method for testing an integrated circuit's data storage device's input/output signal pins for alternating current (AC) defects, by providing an interface that will couple each respective individual test contact, in a subset of said contacts, to a select plurality of the data storage input/output signal ... 08/04/05 - 20050172186 - On-die reflectance arrangements Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.). ... 08/04/05 - 20050172185 - Integrated circuit comprising a test mode secured by initialization of the test mode An electronic circuit, having a test mode in application of the “internal scan path” technique, includes a plurality of configurable cells and a control circuit. The electronic circuit is adapted to working in a standard mode of operation or in a test mode during which the control circuit is active ... 08/04/05 - 20050172184 - Method of securing the test mode of an integrated circuit via intrusion detection An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so ... 08/04/05 - 20050172183 - Method and system for broadcasting data to multiple tap controllers A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the plurality of cores. The master ... 08/04/05 - 20050172182 - Optimal operational voltage identification for a processor design Systems, methods, and computer programs for testing a processor design are provided. One embodiment is a system comprising: means for searching a file that contains test results for a lot of wafers at two or more voltage levels; and means for determining an optimal operational voltage based on which of ... 08/04/05 - 20050172181 - System and method for production testing of high speed communications receivers A method for testing a semiconductor device with a multi-gigabit communications receiver includes combining a data output from a high-speed communications transmitter with a perturbation signal generated by automatic test equipment. The combined signal data signal including jitter and low voltage swings is input to the communications receiver port under ... 07/28/05 - 20050166107 - Selector circuit and semiconductor device A selector circuit precisely outputs a signal selected from a plurality of signals. A latch circuit unit generates an internal selection control signal for controlling a selection operation of a selector circuit unit. When the levels of first and second data input signals do not match each other, the selector ... 07/28/05 - 20050166106 - Tap sampling at double rate An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge. ... 07/28/05 - 20050166105 - Tap multiplexer An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer ... 07/28/05 - 20050166104 - Simultaneous ac logic self-test of multiple clock domains A technique is provided for simultaneous and/or selective self-testing of internal logic and asynchronous boundaries of an IC having a plurality of clock domains. A clock command is generated by an on product clock generator for each clock domain simultaneously; and an asynchronous receive clock driver provides a programmable delay ... 07/21/05 - 20050160335 - System and method for monitoring state information in a network Agents are instructed execute network tests during monitoring intervals. Results of the tests are stored. After expiration of a dampening window period the results are retrieved and evaluated. The evaluation is used to update an error state stored in a data structure in a database as required. Notification of detected ... 07/21/05 - 20050160334 - Apparatus for detecting a/d converter abnormality An apparatus for detecting an abnormality in an A/D converter has a voltage accumulating capacitor. The apparatus includes a storage circuit which receives analog signals whose range of signal operation voltage when normal is limited to be narrower than the range of input operation voltages, and stores in advance the ... 07/14/05 - 20050154946 - Programmable measurement mode for a serial point to point link A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the ... 07/14/05 - 20050154945 - Method and device for functionaly testing an analog to-digital converter and a corresponding analog-to-digital converter A method and device for function testing an analog-digital converter, the analog-digital converter performing a function for converting at least one analog signal into at least one digital signal using a first predetermined reference voltage, wherein the analog-digital converter is able to perform the function alternatively using at least one ... 07/07/05 - 20050149794 - Memory circuit having a controllable output drive A memory circuit having a controllable output drive includes a storage circuit configured for at least temporarily storing a logical state of the memory circuit, and a drive control circuit coupled to the storage circuit. The drive control circuit is configurable for selectively controlling the output drive of the memory ... 07/07/05 - 20050149793 - Integrated circuit having multiple modes of operation A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include processor circuitry and interface circuitry. The processor circuitry may include a plurality of processor cores. The interface circuitry may be capable of communicating in accordance a plurality ... 07/07/05 - 20050149792 - Semiconductor device and method for testing the same A semiconductor device capable that shortens test time with a simple circuit configuration and prevents enlargement of the circuit area for testing. The semiconductor device has a macro memory and a logic section mounted thereon. The macro memory includes an operation control circuit for executing a read/write operation of data ... 07/07/05 - 20050149791 - Digital signal receiving apparatus, an optical transmission apparatus therewith, and a discriminating point control method A digital signal receiving apparatus is disclosed. The digital signal receiving apparatus includes a main signal discriminating unit configured to discriminate a main signal of a received signal, a monitor signal discriminating unit configured to discriminate a monitor signal of the received signal, an error monitoring unit configured to monitor ... 07/07/05 - 20050149790 - Semiconductor integrated circuit verification method and test pattern preparation method In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), expected value comparison times (strobe times) of a test pattern are ... 07/07/05 - 20050149789 - Pseudo random verification of waveform fault coverage A verification of fault coverage tool for testing digital logic electronic components. In one embodiment, a method of testing a device under test (DUT) having an input and a plurality of redundant outputs is provided. The method comprises defining a logic test grid of test sample points that generally define ... 07/07/05 - 20050149788 - Methods of testing semiconductor memory devices in a variable cas latency environment and related semiconductor test devices Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test ... 07/07/05 - 20050149787 - Apparatus and method for testing megaco protocol Provided are an apparatus and method for testing call processing performance and conformance of a media gateway controller and a media gateway with respect to a media gateway control (MEGACO) protocol. The method includes generating a predetermined scenario regarding a test of call processing performance of a media gateway controller ... 07/07/05 - 20050149786 - Apparatus and method for determining threshold voltages in a flash memory unit In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store ... 07/07/05 - 20050149785 - Apparatus and method for testing a flash memory unit using stress voltages In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store ... 07/07/05 - 20050149784 - Testing apparatus and testing method A testing apparatus for testing an electronic device, includes a deterministic jitter applying means for applying deterministic jitter to a given input signal without any amplitude variation component occurring and supplying the input signal applied with the deterministic jitter to the electronic device, a jitter amount controlling means for controlling ... 07/07/05 - 20050149783 - Methods and apparatus for testing an ic In a first aspect, a first method is provided for testing an integrated circuit (IC). The first method includes the steps of (1) employing one of a plurality of input lines to receive a test signal for a processor; (2) employing one of a plurality of output lines to send ... 06/30/05 - 20050144545 - Simultaneous switch test mode The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabled, no SS ... 06/30/05 - 20050144544 - Mechanism for detection of attacks based on impersonation in a wireless network An impersonation detection system for a wireless node of a wireless communication network is described. The system comprises an intrusion detection module for correlating the original data frames transmitted by the wireless node with incoming data frames received over the air interface. The wireless node is connected to the intrusion ... 06/23/05 - 20050138507 - Semiconductor device and display device The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on ... 06/23/05 - 20050138506 - Apparatus for testing a memory module An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller ... 06/23/05 - 20050138505 - Test apparatus There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation ... 06/23/05 - 20050138504 - Test apparatus and testing method A test apparatus for testing electronic devices is provided which includes a plurality of signal sources to supply an output signal to test electronic devices according to an input signal, a loop circuit to make the output signal loop and to input the looped signal to each of the signal ... 06/23/05 - 20050138503 - Integrated circuit with jtag port, tap linking module, and off-chip tap interface port An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. ... 06/23/05 - 20050138502 - Test mode circuit of semiconductor device Provided is a test mode circuit of a semiconductor device comprising: a test mode control unit for generating a test mode control signal which is decoded in response to a plurality of address codes corresponding to kinds of test modes, respectively; a multi-level generating unit for generating multi levels; a ... 06/23/05 - 20050138501 - System and method for testing electronic devices on a microchip A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending ... 06/23/05 - 20050138500 - Functional test design for testability (dft) and test architecture for decreased tester channel resources According to one aspect of the present invention, multiple pins of a chip are connected to a single test channel of a tester. This allows an older tester with fewer test channels to be used with newer chips that have more pins than there are test channels. ... 06/23/05 - 20050138499 - System and method to test integrated circuits on a wafer A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on ... 06/23/05 - 20050138498 - Channel processing data without leading sync mark An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits ... ### FreshPatents.com Support - Terms & Conditions |