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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Memory Testing > Read-in With Read-out And Compare Read-in With Read-out And CompareRead-in With Read-out And Compare patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266278 - Method for at-speed testing of memory interface using scan A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data ... 08/16/07 - 20070192656 - Error detection device and method for error detection for a command decoder An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein the sequence of control signal words has at least one control signal word, having: a controller designed to ... 07/19/07 - 20070168784 - Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the ... 10/26/06 - 20060242497 - Circuit and method for test and repair A preferred exemplary embodiment of the current invention concerns memory testing and repair processes, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a ... 05/04/06 - 20060095817 - Buffer for testing a memory module and method thereof In a method, a test pattern and an associated input mode may be received where the input mode may indicate a manner of applying the test pattern. An output test pattern is applied to at least one of a plurality of memory interface pins in accordance with the input mode. ... 02/16/06 - 20060036918 - Method and apparatus to compare pointers associated with asynchronous clock domains A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are not synchronized. One or ... 12/29/05 - 20050289413 - Integrated semiconductor memory An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory has a combination circuit ... 12/08/05 - 20050273680 - Semiconductor device having buffer layer pattern and method of forming same A semiconductor device having a buffer layer pattern and a related method of manufacture are disclosed. The semiconductor device comprises at least two bit line patterns formed on a semiconductor substrate having a buried insulating interlayer. Each bit line pattern is formed of a bit line and a bit line ... ### FreshPatents.com Support |