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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Memory Testing Memory TestingMemory Testing patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266277 - Memory diagnostic method A storage device can reduce time for diagnosis and allows the diagnosis to be conducted on the entire area of a memory. The storage device includes a temporary memory that temporarily stores for a storage medium, data written to and/or read from a host system by the storage medium; a ... 11/15/07 - 20070266276 - Memory block testing A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less ... 11/08/07 - 20070260947 - Measuring apparatus, measuring method, testing apparatus, testing method, and electronic device There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a threshold voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal ... 11/08/07 - 20070260946 - Nonvolatile memory device comprising a programming and deletion checking option A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L) operations of the actual memory cells (5) the respective programming or deletion process is carried out on at least ... 11/01/07 - 20070255982 - Memory device testing system and method having real time redundancy repair analysis A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data ... 10/25/07 - 20070250746 - Testing cmos ternary cam with redundancy A method for testing an CMOS ternary content addressable memory (TCAM) device includes a match line test to identify stuck match lines, a pull down test to identify weak pull downs (from the match line to ground), and a row-by-row match test. During the row-by-row match test a failed cell ... 10/25/07 - 20070250745 - Method and system for testing a memory device A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address ... 10/25/07 - 20070250744 - Method and apparatus for testing the connectivity of a flash memory chip In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan ... 10/18/07 - 20070245181 - Memory system and method of writing into nonvolatile semiconductor memory A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number ... 10/18/07 - 20070245180 - Circuitry and method for an at-speed scan test An integrated circuit has a plurality of clock domains and a plurality of memory cells being configurable as operational memory cells or as scan test memory cells for testing the integrated circuit. A pulse generator of the integrated circuit generates pulses for triggering the memory cells when being configured as ... 10/04/07 - 20070234144 - Smart verify for multi-state memories A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number ... 10/04/07 - 20070234143 - Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices A semiconductor memory device includes a flash memory including a plurality of M-byte memory pages, and a buffer memory that includes a first M-byte buffer and a second M-byte buffer and that is configured to receive expected data used to test for failed bits in the flash memory. The semiconductor ... 10/04/07 - 20070234142 - Memory system, memory system controller, and a data processing method in a host apparatus A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured ... 10/04/07 - 20070234141 - Concept for testing an integrated circuit An integrated circuitry operable in a normal and test mode has a processing circuit, an output circuit associated with the processing circuit and a storage with a plurality of memory cells. The output circuit is formed to process in normal mode an output signal of the processing circuit and to ... 09/27/07 - 20070226553 - Multiple banks read and data compression for back end test Methods and apparatus that may be used to increase back-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the compression that may be achieved in back-end testing, particularly when only an indication of whether a device has passed or failed is ... 09/20/07 - 20070220379 - Memory device fail summary data reduction for improved redundancy analysis A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell ... 09/20/07 - 20070220378 - Method and apparatus for testing data steering logic for data storage having independently addressable subunits Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to ... 09/06/07 - 20070208969 - Testing apparatus and testing method A testing apparatus according to the present invention includes: a pattern generator for generating an address signal, a data signal and an expected value signal to be provided to a memory under test; an OR comparator for outputting fail data when an output signal outputted by the memory under test ... 09/06/07 - 20070208968 - At-speed multi-port memory array test method and apparatus A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array ... 09/06/07 - 20070208967 - Accessing sequential data in microcontrollers A system and method for executing a sequential data memory access through a serial access port is provided. The system may include a memory access controller to receive a block access command and successively access data elements in the block. In certain implementations, a test device, such as a JTAG ... 08/30/07 - 20070204190 - Test algorithm selection in memory built-in self test controller An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational ... 08/30/07 - 20070204189 - Method and system for testing a random access memory (ram) device having an internal cache A method for testing an internal bus of a random access memory (“RAM”) device, the RAM device having an internal cache coupled to a memory array by the internal bus, the method comprising: writing a value to an address in the RAM device, the value being stored in the internal ... 08/23/07 - 20070198880 - Semiconductor integrated circuit and testing method thereof There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information ... 07/19/07 - 20070168783 - Rom redundancy in rom embedded dram Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redundancy. ... 07/19/07 - 20070168782 - External storage device and memory access control method thereof A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by ... 07/19/07 - 20070168781 - Fully-buffered dual in-line memory module with fault correction A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding ... 07/19/07 - 20070168780 - Memory with test mode output Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus. ... 07/19/07 - 20070168779 - Testing of a cam A system and method for validating a memory device using a Gray Code is described. The system and method tests data segments of a memory storage location concurrently, where a data segment may be a nibble. Each data segment cycles through the possible Gray Code states. Once a data segment, ... 07/19/07 - 20070168778 - Apparatus and methods for testing memory devices Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test mode, all match lines are first reset/disabled. A write enable pulse signal enables a match line corresponding to a CAM word ... 07/19/07 - 20070168777 - Error detection and correction in a cam An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to ... 07/19/07 - 20070168776 - Systems and methods for improved memory scan testability Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells ... 07/19/07 - 20070168775 - Programmable memory test controller Providing a programmable test controller integrated along with a random access memory (RAM). The programmable test controller can be programmed to test desired memory locations. Due to such a feature, the same design of the test controller can be integrated into several implementations (varying by design, fabrication parameters, design rules, ... 07/12/07 - 20070162795 - Test apparatus and test method A test apparatus of the invention includes a pattern generator that generates an address signal and a test pattern signal to be supplied to a memory under test and an expectation signal to be output from the memory under test according to the address signal and the test pattern signal, ... 07/12/07 - 20070162794 - Semiconductor memory test device and method thereof A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol ... 07/12/07 - 20070162793 - Multiple embedded memories and testing components for the same A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using ... 07/12/07 - 20070162792 - Method for increasing the manufacturing yield of programmable logic devices A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is ... 06/28/07 - 20070150777 - Memory test circuit and method A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as ... 06/21/07 - 20070143649 - Test patterns to insure read signal integrity for high speed ddr dram A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arranged within a data ... 06/21/07 - 20070143648 - Memory timing model with back-annotating A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each ... 06/21/07 - 20070143647 - Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an ... 06/14/07 - 20070136628 - Testing apparatus and testing method There is provided a testing apparatus for testing a memory-under-test, having a pin electronics section for inputting/receiving signals to/from the memory-under-test, a pattern generating section for inputting a test pattern to the memory-under-test via the pin electronics section and a judging section for receiving an output signal of the memory-under-test ... 06/14/07 - 20070136627 - System and method for testing write strobe timing margins in memory devices Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal ... 06/14/07 - 20070136626 - Storage efficient memory system with integrated bist function A method and system is disclosed for conducting built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result module, the built-in-self-test is conducted for the circuit under test without testing the test ... 06/14/07 - 20070136625 - Test apparatus and test method There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data ... 06/07/07 - 20070130488 - Semiconductor device and data storage apparatus A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to ... 05/31/07 - 20070124629 - Embedded testing circuit for testing a dual port memory Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port (A) and a second port (B), said embedded testing circuit comprising an embedded address generation circuit for generating an internal address consisting of an internal row selection address (RSAint) and ... 05/31/07 - 20070124628 - Methods of memory bitmap verification for finished product Improved methods for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. A first method provides that EMMI is used to identify the physical location of a failing memory bit. A second ... 05/10/07 - 20070106923 - Integrated circuit and method for testing memory on the integrated circuit An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform ... 04/26/07 - 20070094555 - Component testing and recovery Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be ... 04/26/07 - 20070094554 - Chip specific test mode execution on a memory module A test mode for component-specific testing of a memory module. Data is written to and stored in each memory component of a memory module, which data indicates whether the memory component is to execute a particular test mode. Upon receiving a test mode command supplied in common to all of ... 04/19/07 - 20070088993 - Memory tester having master/slave configuration A memory testing system includes a tester interface. The tester interface is configured to couple a tester control driver to a master memory component and a slave memory component, the tester control driver configured for controlling the master memory component and the slave memory component. The tester interface is configured ... 04/12/07 - 20070083800 - System and method for varying test signal durations and assert times for testing memory devices A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in ... 04/05/07 - 20070079187 - System for testing memory modules using a rotating-type module mounting portion A system for testing memory modules having a rotating-type board mounting portion with a plurality of mounting surfaces positioned at different planes and connected around an axis to form a rotatable structure, at least one circuit board mounted on each mounting surface, an input/output portion, a rotational motor coupled to ... 04/05/07 - 20070079186 - Memory device and method of operating memory device A memory module includes a memory core configured to read and write data. A first input interface is configured to receive write or command data from a forward direction and to receive read data from the forward direction. A first output interface is configured to send read data in a ... 04/05/07 - 20070079185 - Memory scrubbing of expanded memory Embodiments of the invention include a memory device, such as a removable expanded memory card, having a host bus interface that allows a host to access a memory of the device. The memory device also includes memory scrubbing circuitry to read data stored at addresses in the memory and to ... 04/05/07 - 20070079184 - System and method for avoiding attempts to access a defective portion of memory According to one embodiment, a method comprises detecting a defect in a portion of memory. The method further comprises designating the portion of memory as defective, and avoiding attempts to access the portion of memory designated as defective. ... 03/22/07 - 20070067685 - Testing apparatus and testing method There is provided a testing apparatus including: a pattern generator that generates an address signal and a data signal to be supplied to a plurality of memories under test and an expectation signal; a plurality of logic comparators that generate fail data when an output signal output from the plurality ... 03/22/07 - 20070067684 - Non-volatile memory system with self test capability In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the ... 03/15/07 - 20070061639 - Semiconductor device test system with test interface means One aspect of the invention relates to a semiconductor device test system, interface means for use with a semiconductor device test method, and a semiconductor device test method, wherein, in a fist mode of an interface means, in reaction to test signals corresponding to a test standard, for example, a ... 03/15/07 - 20070061638 - Multi drive test system for data storage device Embodiments of the invention provide a data storage device test method and data storage device manufacture method which allow a tester to perform an operation test of plural data storage devices connected thereto in a shorter period of time. In one embodiment, an operation test of each of plural HDDs ... 03/15/07 - 20070061637 - Process for conducting high-speed bitmapping of memory cells during production The present invention is directed to a method of fast bitmapping defective memory arrays in semiconductor integrated circuit dice formed on a wafer. The method involves loading a wafer onto automated test equipment. Initial production testing is then performed on each die of the wafer to determine whether the memory ... 03/01/07 - 20070050689 - Storage system comprising logical circuit configured in accordance with information in memory on pld The storage system comprises a PLD which controls data transfer between another device and a media drive; and a processor. The PLD comprises a memory for storing information input from an information source located externally to the PLD; a circuit element group comprising a plurality of circuit elements; and a ... 02/22/07 - 20070043984 - Nonvolatile semiconductor memory device and signal processing system The nonvolatile semiconductor memory device includes: a first memory block having a first program level and a first read circuit; a second memory block having a second program level different from the first program level and a second read circuit of a scheme different from the first read circuit, the ... 02/22/07 - 20070043983 - Sample screening method for system soft error rate evaluation A sample screening method for system soft error rate evaluation. Memory cells of a memory device are written and read according to a first test condition to locate hard errors. The memory cells of the memory device are read according to a second test condition to locate functional errors. The ... 02/15/07 - 20070038907 - Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and ... 02/08/07 - 20070033452 - Method and circuit arrangement for detecting errors in a data record The method comprises providing a part-data record to be changed from a data record stored in a memory device, providing a change data record changing the part-data record to be changed and providing a check word associated with the data record. The check word is changed by a change transformation ... 02/08/07 - 20070033451 - Method for writing data blocks on a block addressable storage medium using defect management The present invention relates to a method for writing data blocks on a block addressable storage medium, preferably an optical storage medium, using defect management, comprising the steps: processing data to data blocks adapted to the storage medium by a host device; sending each data block from the host device ... 01/25/07 - 20070022335 - Methods and apparatus for interfacing between test system and memory Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least ... 01/25/07 - 20070022334 - Semiconductor device, test board for testing the same, and test system and method for testing the same Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and ... 01/25/07 - 20070022333 - Testing of interconnects associated with memory cards Various systems and method for testing data interconnects are provided. In one method, a test data value is transmitted from an interconnect test tool to a memory card included in a memory card bank through a first set of interconnects. A received data value received by the memory card is ... 01/11/07 - 20070011511 - Built-in self-test method and system A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the ... 01/11/07 - 20070011510 - Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories) A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register. ... 01/11/07 - 20070011509 - Bitmap cluster analysis of defects in integrated circuits A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When ... 01/11/07 - 20070011508 - Time controllable sensing scheme for sense amplifier in memory ic test A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is issued by ... 01/11/07 - 20070011507 - System and method for remote system support In some embodiments, the invention involves a system and method relating to out-of-band debugging of a platform. In at least one embodiment, the present invention enables a debugger to operate during any operational phase of the platform. Specifically, the debugger may operate during pre-boot, before memory initialization and through to ... 12/28/06 - 20060294441 - Logic analyzer data retrieving circuit and its retrieving method A logic analyzer data retrieving method used in a logic analyzer formed of a control unit (11), a memory unit (12), and a data retrieving circuit (13), is disclosed to include the step of driving the data retrieving circuit of the logic analyzer to receive a time delay default value ... 12/14/06 - 20060282720 - Method for the automatic provision of repair position data of fuse elements in integrated memory circuit Methods and systems for the determination of the function and of the position information of fuses from a schematic and/or a network list and a layout. A repair process is aided with this position information. ... 12/14/06 - 20060282719 - Unique addressable memory data path Instead of using point to point connections between the memory and the memory test controller, a unique address is assigned to each memory element. The memory elements and the single memory test controller are interconnected by a hierarchal datapath both for the memory addresses and for the resultant data being ... 12/14/06 - 20060282718 - Test mode for programming rate and precharge time for dram activate-precharge cycle A programmable activate-precharge cycle are provided for a DRAM device. Activate and precharge signals associated with the activate-precharge cycle are generated on the basis of the programmed rate and precharge time with respect to an internal clock of the DRAM device. The activate and precharge signals are coupled to wordlines ... 12/07/06 - 20060277451 - Magnetic disk apparatus, preventive maintenance detection method and program therefor The present invention has been made to obtain a magnetic disk apparatus and the like capable of using a patrol region in the magnetic disk to detect a location in need of maintenance in hardware equipment around the magnetic disk in a separate manner from the disk itself and thereby ... 11/30/06 - 20060271831 - Semiconductor memory device having a test control circuit A semiconductor memory device having a test control circuit includes a cell array, a BIST (built-in self test) circuit adapted and configured to perform a BIST operation on the cell array, a BISR (built-in self repair) circuit adapted and configured to perform a BISR operation on the cell array, and ... 11/09/06 - 20060253750 - Semiconductor integrated circuit and burn-in test method thereof To provide a semiconductor integrated circuit that includes a flash EEPROM on which an efficient burn-in test can be carried out and a burn-in test method thereof. By changing the level of a control signal C1 from the mode selecting unit 40, the operating mode of a functional unit 10 ... 11/09/06 - 20060253749 - Real-time memory verification in a high-availability system A computer system includes a look-up table implemented in a memory controller which includes a processor which manipulates data and look-up-table entries so as to make an unused and in-use memory available for testing in a manner which is alien to and aims to minimize impact to the operating system ... 11/02/06 - 20060248415 - Memory device having conditioning output data Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data. During a memory operation, the memory device transfers both the condition data and the memory data to the ... 11/02/06 - 20060248414 - Method and system for bitmap analysis system for high speed testing of memories A Bit Map Analysis System (BMAS) for high-speed memory testing. The BMAS reduces the amount of data transaction between the BIST and tester may be used in embedded memories, whether asynchronous or synchronous, static or dynamic, or volatile or non-volatile. The tester clock cycle is substantially reduced, resulting in reduced ... 11/02/06 - 20060248413 - Voltage monitoring test mode and test adapter A testing system has a processor, a module and at least one manufactured semiconductor device. The processor is configured to send and receive testing signals. The module is electrically coupled to the processor. The at least one manufactured semiconductor device is mounted on the module, and the semiconductor device has ... 10/26/06 - 20060242496 - Printer controller having tamper resistant shadow memory A printer controller is provided having an integrated circuit incorporating a processor and memory. The memory stores a set of data representing program code and/or an operating value for printer control. Each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells ... 10/26/06 - 20060242495 - Memory device having terminals for transferring multiple types of data Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information ... 10/26/06 - 20060242494 - Output data compression scheme using tri-state A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response ... 10/26/06 - 20060242493 - Network processor having cyclic redundancy check implemented in hardware A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation. ... 10/26/06 - 20060242492 - Method and apparatus for masking known fails during memory tests readouts Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that ... 10/26/06 - 20060242491 - Method and system for applying patches to a computer program concurrently with its execution The present invention relates to a method, a computer program product and a system of adding new static data variables and initialisation routines for these variables as part of a method of replacing a current version of a computer program with a replacement version of the program concurrently with the ... 10/26/06 - 20060242490 - Method and apparatus for testing a memory device The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a ... 10/26/06 - 20060242489 - Stored data reverification management system and method A system and method are provided for verifying data copies and reverifying the copies over the life span of media according to a verification policy. Characteristics of media and use of media are tracked to provide metrics which may be used to dynamically reevaluate and reassign verification policies to optimize ... 10/26/06 - 20060242488 - Flash memory device with reduced access time A flash memory device with a reduced access time. The flash memory device executes an error detection and correction operation while encoding or decoding transmission and reception signals with a host apparatus. The flash memory device utilizes a simplified design algorithm and reduces an access time. ... 10/19/06 - 20060236164 - Automatic test entry termination in a memory device A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, the test mode is ... 10/19/06 - 20060236163 - Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area A memory component and a method for the parallel testing of memory components are described herein. A fully functional memory area, which is classified herein as all good memory, and memory components including a restricted memory area, which are classified herein as partial good memory, are provided. Test data words ... 10/19/06 - 20060236162 - Method and system for performing system-level correction of memory errors One embodiment is a method of correcting errors in a memory subsystem in a computer system. The method comprises monitoring occurrence of correctable memory errors; responsive to the monitoring, determining whether a risk of occurrence of an uncorrectable memory error is less than a tolerable risk; and responsive to a ... 10/05/06 - 20060224933 - Mechanism for implementing redundancy to mask failing sram In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty columns of a memory, a redundancy configuration logic to generate one or more select signals based on the BIST data, ... 09/28/06 - 20060218453 - System and method for testing a memory for a memory failure exhibited by a failing memory A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence of the memory failure and ... 09/28/06 - 20060218452 - Area efficient bist system for memories A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory ... 09/21/06 - 20060212764 - Integrated circuit and method for testing memory on the integrated circuit An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also ... 09/14/06 - 20060206770 - Non-volatile semiconductor memory with large erase blocks storing cycle counts In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in ... 09/07/06 - 20060200714 - Test equipment for semiconductor A test equipment for semiconductor according to the present invention comprises a equipment main body and a memory cell provided in an outside of the equipment main body, wherein the equipment main body comprises a configurable device capable of making a hardware construction in a programmable manner and an interface ... 09/07/06 - 20060200713 - Method and apparatus for memory self testing A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence ... 09/07/06 - 20060200712 - System and method for testing memory In another embodiment, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical ... 08/24/06 - 20060190780 - High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a ... 08/24/06 - 20060190779 - Semiconductor integrated circuit for reducing number of contact pads to be probed in probe test A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer ... 08/24/06 - 20060190778 - Method for reducing sram test time by applying power-up state knowledge Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take ... 08/17/06 - 20060184846 - System and method for managing mirrored memory transactions and error recovery In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling ... 08/10/06 - 20060179371 - Data copy method and application processor for the same A data copy method includes designating data stored in a non-volatile memory device as data packages, reading at least one data package to store the read at least one data package in a temporary memory device, transferring the at least one data package stored in the temporary memory device to ... 08/10/06 - 20060179370 - Semiconductor memory device in which memory cells are tested using several different test data patterns and method thereof There is provided a memory device in which memory cells may be tested using several different test data patterns. The memory device may include a switch unit, a plurality of storage units, and a selector. The switch unit may transfer bits of data received in response to a mode control ... 08/10/06 - 20060179369 - Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for ... 08/10/06 - 20060179368 - Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of sram with redundancy A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix ... 08/03/06 - 20060174172 - Toggle memory burst A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in ... 07/27/06 - 20060168488 - Method and system for testing ram redundant integrated circuits System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die. ... 07/20/06 - 20060161825 - Non-volatile memory device supporting high-parallelism test at wafer level A non-volatile memory device includes a chip of semiconductor material. The chip includes a memory and control means for performing a programming operation, an erasing operation and a reading operation on the memory in response to corresponding external commands. The chip further includes testing means for performing at least one ... 07/20/06 - 20060161824 - System and method of testing a plurality of memory blocks of an integrated circuit in parallel A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width ... 07/13/06 - 20060156093 - Synchronous memory interface with test code input A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals provided on the address input connections and not the data input/output connections. The test mode can be entered using either commands or a combination of commands and an ... 07/13/06 - 20060156092 - Memory technology test apparatus A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data ... 07/13/06 - 20060156091 - Methods and apparatus for testing a memory In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit ... 07/13/06 - 20060156090 - Memory array manufacturing defect detection system and method The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and ... 07/13/06 - 20060156089 - Method and apparatus utilizing defect memories A method and apparatus utilizing defect memories is based on damaged section blocks corresponding high bit address division types. A switch set is used to reset an electrical connecting mode between high bit address input end and high bit address output end of the control chip such that high bit ... 07/13/06 - 20060156088 - Method and bist architecture for fast memory testing in platform-based integrated circuit The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input ... 06/22/06 - 20060136793 - Memory power models related to access information and methods thereof A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory device. ... 06/22/06 - 20060136792 - Random access memory having test circuit A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first ... 06/22/06 - 20060136791 - Test method, control circuit and system for reduced time combined write window and retention testing A method, test mode circuit and system for a combined write window and retention test for a memory device that is faster than techniques heretofore known. The combined write window and retention test procedure involves controlling time intervals during which wordlines are activated and deactivated and bitlines are grounded or ... 06/15/06 - 20060129899 - Monitoring of solid state memory devices in active memory system utilizing redundant devices Redundant capacity in a memory system is utilized to facilitate active monitoring of solid state memory devices in the memory system. All or part of the data stored in an active solid state memory device, and used in an active data processing system, may be copied to at least one ... 06/08/06 - 20060123284 - Method of determining defects in information storage medium, recording/reproducing apparatus using the same, and information storage medium A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a method comprises: seeking a defect entry whose state information indicates that a defect block or a replacement block has been reinitialized without certification from a ... 06/08/06 - 20060123283 - Information storage medium, recording/reproducing apparatus, and recording/reproducing method An information storage medium, a recording/reproducing apparatus and a recording/reproducing method are provided to increase data reproduction efficiency. The recording/reproducing apparatus includes: a write/read unit for recording data on an information storage medium and reading data from the medium; and a controller for controlling the write/read unit to record a ... 06/08/06 - 20060123282 - Service layer architecture for memory access system and method A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem ... 06/08/06 - 20060123281 - Method and timing harness for system level static timing analysis A method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a system design including a design under timing analysis, an external device, and an interface between the design under timing analysis and the external device; (b) generating ... 06/08/06 - 20060123280 - Test circuit and method for multilevel cell flash memory A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. ... 06/08/06 - 20060123279 - Apparatus, system, and method for identifying fixed memory address errors in source code at build time An apparatus, system, and method are provided for identifying fixed memory address errors in source code at build time. The present invention includes a substitution module that substitutes fixed memory address values for hardcoded memory address symbols. The fixed memory address values are substituted according to a mapping between fixed ... 06/01/06 - 20060117231 - Adaptive communication interface Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and ... 05/18/06 - 20060107136 - Smart verify for multi-state memories The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” ... 05/18/06 - 20060107135 - Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array A “row-diagonal” (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of two storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity ... 05/18/06 - 20060107134 - Test apparatus for semiconductor memory device A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to determine whether the semiconductor memory device is ... 05/18/06 - 20060107133 - Tampering-protected microprocessor system and operating procedure for same A tampering-protected microprocessor system includes a microprocessor, an internal write/read memory integrated with the microprocessor into a common module, and a second memory in which at least a portion of an operating program to be executed by the microprocessor is stored. At least one procedure of the operating program which ... 05/18/06 - 20060107132 - System and method for testing a memory for a memory failure exhibited by a failing memory A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence of the memory failure and ... 05/04/06 - 20060095816 - Test clocking scheme A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme ... 04/27/06 - 20060090108 - Method and apparatus for testing a memory device with compressed data using a single output A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test ... 04/27/06 - 20060090107 - Semiconductor device A semiconductor device includes a first memory block having a first address space, a second memory block having a second address space which is smaller than the first address space, and a test circuit which supplies a test address and a test control signal to the first memory block and ... 04/27/06 - 20060090106 - Generalized bist for multiport memories A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of ... 04/27/06 - 20060090105 - Built-in self test for read-only memory including a diagnostic mode A semiconductor circuit comprises a read-only memory (ROM), and a built-in self test (BIST) circuit coupled to the ROM. The BIST circuit is configured to output an entire contents of the ROM. ... 04/27/06 - 20060090104 - Adapting rcu for real-time operating system usage A system and method is provided to support immediate freeing of a designated element from memory. Following a process of designating an element for removal from a data-structure, conditional limitations are used to determine if immediate freeing of the element from memory is available. The conditional limitations include determining that ... 04/20/06 - 20060085705 - Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controller The invention relates to a memory circuit comprising a read only memory unit for providing a number of fixed programmed test data; comprising an initialization unit in order, in an initialization mode, to output the fixed programmed test data in a specific sequence to an output terminal. ... 04/20/06 - 20060085704 - Semi-conductor component, as well as a process for the reading of test data (b) Storing the test data in at least one useful data memory cell on the semi-conductor component (2a), and (c) Reading the test data from the at least one useful data memory cell. ... 04/20/06 - 20060085703 - Memory cell test circuit for use in semiconductor memory device and its method A memory cell test circuit for use in a semiconductor memory device having a plurality of banks connected to a plurality of global input/output lines, including: a plurality of bank switching units for transferring data outputted from the plurality of banks to the plurality of global input/output lines based on ... 04/20/06 - 20060085702 - Integrated circuit fuses having corresponding storage circuitry Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may ... 04/20/06 - 20060085701 - Method and apparatus for separating native, functional and test configurations of memory A method for allowing native, functional, and test configurations of a memory to be independent of one another includes steps as follows. A memory is first provided. The memory has a native configuration including k words and n data output pins, k and n being positive integers. Each of the ... 03/30/06 - 20060069966 - Method and system for testing memory using hash algorithm A method for testing a memory is described. The method includes the following steps. First, a test pattern is generated by a hash algorithm. Then, the test pattern is written into the memory. Next, the test pattern is read from the memory. Following that, a signature is generated by the ... 03/23/06 - 20060064611 - Method of testing memory module and memory module A method of testing an integrated circuit includes providing a bank access sequence received to a register in the integrated circuit, generating a test pattern sequence based on the bank access sequence, and performing a Built-In Self Test (BIST) operation on the integrated circuit based on the generated test pattern ... 03/16/06 - 20060059394 - Loop-back method for measuring the interface timing of semiconductor memory devices using the normal mode memory The invention relates to a method for testing a semiconductor memory device, the semiconductor memory device being able to be operated in a normal operating mode and a test mode. The method for testing includes communicating test input data to be used for a test to the semiconductor memory device; ... 03/09/06 - 20060053354 - Test method for determining the wire configuration for circuit carriers with components arranged thereon The invention relates to a test method for determining a wire configuration for a circuit carrier having at least one component arranged thereon, where internal lines in the component are connected to component connections in a prescribed order, and where the component connections are wired to connections on the circuit ... 03/09/06 - 20060053353 - Nonvolatile memory devices with test data buffers and methods for testing same A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control ... 03/02/06 - 20060048023 - Test method for nonvolatile memory A control terminal section CON and an address terminal section ADDR of a test apparatus are respectively connected to those of a flash memory. A first to an (n−1) -th input and output terminal of the test apparatus are connected to data terminals of the flash memory. Further, an n-th ... 03/02/06 - 20060048022 - Method for testing the serviceability of bit lines in a dram memory device DRAM memory device (1) comprising at least one array of memory cells (2, 3, 4, 5), each memory cell (12) being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (15); a ... 02/23/06 - 20060041799 - Test apparatus, phase adjusting method and memory controller An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result ... 02/23/06 - 20060041798 - Design techniques to increase testing efficiency Specific test logic may be added into a semiconductor logic or memory device, which does not change the normal operation of the device, but which allows under test mode the device to perform both parallel read-compare and parallel write operations of the blocks within the device, which provides significant reduction ... 02/16/06 - 20060036917 - Method for testing a memory device and memory device for carrying out the method The invention provides a memory device for data storage having a memory module (100) having at least one memory bank (101a-101n) in which data to be stored are stored and from which the stored data are read out, and a logic unit (106) for controlling a writing and a reading ... 02/16/06 - 20060036916 - Memory with test mode output Apparatus and methods of forming and operating the apparatus provide a means for a memory to generate a test mode signal to trigger a test in response to the memory detecting a predetermined command from a system bus. In an embodiment, a mode register in the memory includes an indicator ... 02/09/06 - 20060031726 - Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address ... 02/09/06 - 20060031725 - Algorithm pattern generator for testing a memory device and memory tester using the same Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component ... 01/19/06 - 20060015784 - System and method for write-enable bypass testing in an electronic circuit A system and method for write-enable bypass testing in an electronic circuit. According to one embodiment, the integrated circuit that includes a memory block having at least one input and at least one output. At least one input is associated with a block of input logic and at least one ... 01/12/06 - 20060010359 - Method for testing electronic circuit units and test apparatus The invention provides a test apparatus for testing an electronic circuit unit to be tested. The test apparatus comprises a read-only memory for buffer-storing a test data stream read from the circuit unit to be tested in a manner dependent on a clock signal. The test apparatus further comprises a ... 12/29/05 - 20050289412 - Parallel bit test circuit in semiconductor memory device and associated method An embodiment is a circuit including 2n-1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n-1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. ... 12/29/05 - 20050289411 - Checking of the atomicity of commands executed by a microprocessor A method and a system for checking the atomic character of at least one command executed by a microprocessor of an electronic component including at least one rewritable non-volatile memory, including: selecting a command including at least one updating of at least one piece of data in the non-volatile memory; ... 12/29/05 - 20050289410 - Internal signal test device and method thereof An internal signal test device tests a cycle of a specific internal signal by distinguishing a high level period and a low level period of the internal signal, at a wafer and package state by using an external test equipment. The internal signal test device comprises a refresh cycle generating ... 12/22/05 - 20050283689 - Error correction in rom embedded dram Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM). ... 12/22/05 - 20050283688 - Method and apparatus for testing a memory array A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array ... 12/15/05 - 20050278591 - System and method for testing a data storage device without revealing memory content such that individual bits of NEW_DATA are equal to CURRENT_DATA with selected bits inverted when the corresponding positions in DATA_SEED are high. NEW_DATA is written into the memory, read out and verified, so that all bit positions can be controlled and tested in both logic states, while NEW_DATA and CURRENT_DATA ... 12/08/05 - 20050273679 - Semi-conductor component test procedure, in particular for a system with several modules, each comprising a data buffer component, as well as a test module to be used in a corresponding procedure The invention relates to a semi-conductor component test procedure for a system with several memory component modules, each comprising at least one memory component with a buffer connected in series before it, whereby a test module is used for testing, which test module comprises a buffer, not however a memory ... 12/08/05 - 20050273678 - Test apparatus for testing an integrated circuit Test apparatus for testing an integrated circuit The invention relates to a test apparatus for testing an integrated circuit, particularly a DDR semiconductor memory, having at least one data connection for inputting at least one data signal, at least one DQS control connection for inputting at least one unaltered-frequency DQS ... 12/08/05 - 20050273677 - Circuit and method for storing a signal using a latch shared between operational and diagnostic paths A circuit 2 for storing a signal value includes an operational data path formed by an operational path latch 4 and a shared latch 6. A diagnostic data path is formed by a diagnostic path latch 12 and the shared latch 6. An operational clock signal CLK controls the operational ... 12/01/05 - 20050268185 - Method and apparatus for high speed testing of latch based random access memory A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock ... 11/24/05 - 20050262405 - Apparatus and method for reducing test resources in testing drams An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. ... 11/17/05 - 20050257107 - Parallel bit testing device and method A memory device includes a memory cell array to store data, a register to store test data, and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to the data, the test data, and ... 11/10/05 - 20050251713 - Multi-port memory device having serial i/o interface There is provided a multi-port memory device having a serial I/O interface, which is capable of providing an operation test without any collision with an internal command/address generation path through a limited external pin. The multi-port memory device includes a plurality of ports supporting a serial I/O interface, and the ... 10/27/05 - 20050240838 - Semiconductor memory device having code bit cell array A semiconductor memory device includes a data bit cell array in which a plurality of memory cells each to store a data bit is arranged, a test circuit which detects and analyzes a command that contains test pattern information, a syndrome counter which counts the number of error corrections which ... 10/13/05 - 20050229051 - Delay detecting apparatus of delay element in semiconductor device and method thereof A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and ... 10/13/05 - 20050229050 - Semiconductor device A semiconductor device comprises a first supply voltage pad arranged to apply a first supply voltage; and a second supply voltage pad arranged to apply a second supply voltage for execution of tests. A current detector is operative to detect a current caused from application of the second supply voltage ... 10/06/05 - 20050223303 - Memory channel self test A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory module, while further employing another buffer ... 09/29/05 - 20050216800 - Deterministic preventive recovery from a predicted failure in a distributed storage system A data storage subsystem in a distributed storage system having a plurality of predictive failure analyzing data storage devices. The subsystem furthermore has a circuit that is responsive to a predicted failure indication by a data storage device in relation to predetermined rules stored in memory for deterministically initiating a ... 09/29/05 - 20050216799 - Method for detecting resistive-open defects in semiconductor memories The present invention relates to a method for detecting delay faults in a semiconductor memory. In an example embodiment, address bits and data bits are generated according to a test pattern suitable for testing the semiconductor memory. The address bits and the data bits are validated and then provided to ... 09/29/05 - 20050216798 - Method and system for detecting potential races in multithreaded programs A dynamic race detection system and method overcomes drawbacks of previous lockset approaches, which may produce many false positives, particularly in the context of thread fork/join and asynchronous calls. For each shared memory location, a set of locks that are protecting the location and a set of concurrent thread segments ... 09/22/05 - 20050210344 - Non-volatile memory evaluating method and non-volatile memory The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to the non-volatile memory at lower temperatures than normal ... 09/01/05 - 20050193293 - Semiconductor device capable of performing test at actual operating frequency A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus. ... 09/01/05 - 20050193292 - Enhanced approach of m-array decoding and error correction A process and apparatus for determining the location of a captured array from a larger image is described. A non-repeating sequence may be folded into a non-repeating array in which the array is unique for every neighboring window of a given size. A portion of the array of the neighboring ... 08/25/05 - 20050188288 - System and method for accelerated information handling system memory testing Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, ... 08/25/05 - 20050188287 - Testing and repair methodology for memories having redundancy A method of testing and repairing an integrated circuit having a total number of fuses for effecting repair of the integrated circuit. The method including: testing a memory array with a set of tests and reserving a first number of the total number of fuses for use in repairing the ... 08/25/05 - 20050188286 - Method for determining integrity of memory A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are ... 08/18/05 - 20050182993 - Semiconductor integrated circuit device equipped with read sequencer and write sequencer A semiconductor integrated circuit device includes a semiconductor memory circuit device, a first sequencer, and a second sequencer. The semiconductor memory circuit device stores data. The first sequencer controls writing of data into the semiconductor memory circuit device. The second sequencer controls reading of data from the semiconductor memory circuit ... 08/04/05 - 20050172179 - System and method for configuring a solid-state storage device with error correction coding A system for configuring solid-state storage devices comprises a solid-state storage device and an error correction code (ECC) selection system. The ECC selection system is configured to automatically select a set of error correction code based on an error rate of the storage device. The ECC selection system is further ... 08/04/05 - 20050172178 - Cache-testable processor identification Systems, methods, and computer programs for performing cache yield analysis of a processor design are provided. One embodiment is a system for testing cache performance of a processor design. Briefly described, one such system comprises: means for searching a file that contains test results for a lot of wafers; and ... 07/28/05 - 20050166103 - System, method, and apparatus for firmware code-coverage in complex system on chip Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the ... 07/28/05 - 20050166102 - Cam expected address search testmode A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected address to determine whether the expected address is defective. The CAM can be tested by applying search data and the expected address to the CAM at ... 07/21/05 - 20050160333 - Embedded micro computer unit (mcu) for high-speed testing using a memory emulation module and a method of testing the same Provided are an embedded micro computer unit (MCU) using a memory emulation module and a method of testing the embedded MCU. The embedded MCU includes an internal memory that is connected to bus master devices for storing temporary data of the bus master devices and a test vector in a ... 07/21/05 - 20050160332 - Semiconductor integrated circuit An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the ... 07/14/05 - 20050154944 - Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus ... 07/14/05 - 20050154943 - Mechanism for adjacent-symbol error correction and detection According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors ... 07/07/05 - 20050149782 - Semiconductor memory repair methodology using quasi-non-volatile memory A device and method is provided for effecting soft repair of semiconductor memory embedded within an integrated circuit. The invention temporarily and in a non-volatile or quasi-non-volatile manner stores data within the structure of the semiconductor chip. This data respects chip performance at a first test point and may be ... 07/07/05 - 20050149781 - System and method for soft error handling Embodiments of the present invention relate to detecting and clearing a soft error in a cache. ... 07/07/05 - 20050149780 - System-in-package and method of testing thereof A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the ... 06/23/05 - 20050138497 - Apparatus and method for testing a flash memory unit In an integrated circuit having a processing core and at least one memory unit, each memory unit, in addition to the storage cells and addressing circuits, includes apparatus for testing the memory independently from the testing of the processing core. The test apparatus includes a local storage unit to store ... 06/23/05 - 20050138496 - Method and apparatus for test and repair of marginally functional sram cells A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one ... 06/23/05 - 20050138495 - Magnetic memory which compares compressed fault maps A magnetic memory which in some embodiments compares compressed fault maps is disclosed. In one embodiment, the magnetic memory may include at least two magnetic memory cells which are configured to store data. The magnetic memory includes a control system configured to periodically obtain parametric values from the magnetic memory ... 06/09/05 - 20050125712 - Manifold-distributed air flow over removable test boards in a memory-module burn-in system with heat chamber isolated by backplane Hot air blown past memory modules under test in a heat chamber is improved. Hot air entering the chamber from an inlet pipe is split by a manifold and deflectors. Holes in the manifold allow for a relatively even air distribution within the chamber, minimizing temperature variations. Return air is ... 06/02/05 - 20050120284 - Memory testing A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select ... 06/02/05 - 20050120283 - Cam test structures and methods therefor Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ... ### FreshPatents.com Support - Terms & Conditions |