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Error Detection/correction And Fault Detection/recovery > Pulse Or Data Error Handling > Skew Detection Correction Skew Detection CorrectionSkew Detection Correction patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/15/07 - 20070266275 - Clock recovery system with triggered phase error measurement A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock recovery system receives an input signal and recovers a clock signal from the input signal. The measurement module is coupled to ... 07/19/07 - 20070168767 - Flexible scan architecture A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other ... 07/19/07 - 20070168766 - Providing precise timing control between multiple standardized test instrumentation chassis Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. ... 06/21/07 - 20070143644 - Dynamic determination of signal quality in a digital system A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) ... 05/31/07 - 20070124624 - Impulse noise mitigation In a signal transmission medium such as an ac power line, impulse noise in the line may be dealt with by detecting impulse noise in the transmission medium, determining whether the impulse noise is periodic or complex, and, at least approximately, correlating the time at which periodic impulse noise occurs ... 05/17/07 - 20070113119 - High-speed transceiver tester incorporating jitter injection A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low-and high-frequency components. The phase-modulated signal is ... 04/26/07 - 20070094549 - Phase error determination method and digital phase-locked loop system In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In ... 04/19/07 - 20070088991 - Method and apparatus for verifying multi-channel data A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a predetermined data bit from the each of N data channels, and a deskew channel error detector detecting whether the deskew channel received by ... 04/19/07 - 20070088990 - System and method for reduction of rebuild time in raid systems through implementation of striped hot spare drives The present invention is a system for reducing rebuild time in a RAID (Redundant Array of Independent Disks) configuration. The system includes a plurality of RAID disk drives, a plurality of hot spare disk drives, and a controller communicatively coupled to the plurality of RAID disk drives and the plurality ... 04/05/07 - 20070079180 - Method and an apparatus for frequency measurement The frequency of the signal under test is measured by measuring the time of a prescribed phase of the signal under test, and calculating the slope of the approximate line related to above-mentioned prescribed phase and the above-mentioned measured time or the reciprocal of the above-mentioned slope as the above-mentioned ... 03/29/07 - 20070074084 - Method and apparatus for monitoring and compensating for skew on a high speed parallel bus Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a plurality of samples of the plurality of signals for each unit interval; and identifying a location of ... 01/04/07 - 20070006053 - Method and apparatus for synchronizing data channels using an alternating parity deskew channel The invention includes a method and apparatus for aligning a plurality of data channels using a deskew bitstream. The method includes receiving the deskew bitstream, identifying an aligned deskew frame by processing the deskew bitstream, identifying a data channel alignment position associated with each of the plurality of data channels ... 12/14/06 - 20060282711 - Recovering a hardware module from a malfunction The invention relates to a recovery of a hardware module of an electronic device from a malfunction state. The hardware module is connected via a signal line to a recovery component of the device, a state of the signal line being controlled by the hardware module. The recovery component monitors ... 11/16/06 - 20060259834 - Method and system for debug and test using replicated logic A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution ... 10/26/06 - 20060242474 - Programmable in-situ delay fault test clock generator A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse ... 10/26/06 - 20060242473 - Phase optimization for data communication between plesiochronous time domains A method and apparatus for optimizing data transfer between launch and capture domains driven by plesiochronous launch and capture clocks transmits a beacon of representational data from the launch domain to the capture domain and captures the beacon in the capture domain using the capture clock. The captured beacon is ... 10/19/06 - 20060236157 - Calibrating automatic test equipment Calibrating automatic test equipment (ATE) includes determining an offset between a reference timing event and a channel event, where the channel event is associated with a communication channel of the ATE, and adjusting signal transmission over the communication channel based on the offset. Determining the offset may include obtaining a ... 08/24/06 - 20060190776 - Method and device for generating and detecting a fingerprint functioning as a trigger marker in a multimedia signal This invention relates to a device and a method of relating one or more trigger actions with a multimedia signal and corresponding method and device for detecting one or more trigger actions in a multimedia signal. One fingerprint is generated on the basis of a segment of the multimedia signal ... 07/27/06 - 20060168487 - System pulse latch and shadow pulse latch coupled to output joining circuit In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal ... 07/13/06 - 20060156084 - Multiphase clock generation A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A third-phase clock signal is generated one ... 07/13/06 - 20060156083 - Method of compensating for a byte skew of pci express and pci express physical layer receiver for the same A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received ... 07/13/06 - 20060156082 - Signal dividing circuit and semiconductor device To provide a constitution capable of reducing production cost in a semiconductor device for display of a type integrally formed with a drive circuit with a digital signal as an input signal and a pixel matrix unit, a signal dividing circuit is formed on a substrate where drive circuits and ... 07/13/06 - 20060156081 - Semiconductor component test procedure, as well as a data buffer component A data buffer component and a semiconductor component test procedure for testing a memory module are provided. At least one memory component with a series-connected buffer is included. The procedure includes testing the memory module by using a pulse signal, which has been chronologically retarded or advanced by a predetermined ... 07/13/06 - 20060156080 - Method for the thermal testing of a thermal path to an integrated circuit According to one embodiment of the present invention, a method for detecting a defect in an integrated circuit using an optimized power pulse includes applying a first pulse of power to a first integrated circuit for an optimized pulse duration. The optimized pulse duration is determined as a function of ... 06/08/06 - 20060123275 - Apparatus and method for adapting a level sensitive device to produce edge-triggered behavior A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry. ... 06/08/06 - 20060123274 - Method and apparatus for detecting timing exception path and computer product A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all ... 03/23/06 - 20060064609 - Digital processor with pulse width modulation module having dynamically adjustable phase offset capability, high speed operation and simultaneous update of multiple pulse width modulation duty cycle registers A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) ... 02/23/06 - 20060041797 - Jitter applying circuit and test apparatus There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an oscillating signal corresponding to a given reference signal, a variable delay circuit for outputting said clock signal in which said oscillating ... 02/23/06 - 20060041796 - Method and apparatus for eliminating errors in a seek operation on a recording medium A method and apparatus for eliminating errors in a seek operation on a recording medium are provided. Given a target address on a recording medium, a reading device is moved to seek the target address, and it is determined whether or not a signal is read out at the location ... 02/16/06 - 20060036915 - Deskew circuit and disk array control device using the deskew circuit, and deskew method A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent before implementing a data transfer, ... 01/12/06 - 20060010358 - Method and apparatus for calibrating and/or deskewing communications channels A series of pulses may be driven down each drive channel, which creates a series of composite pulses at the output of the buffer. Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted until ... 12/29/05 - 20050289405 - Fast synchronization of a number of digital clocks The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and ... 11/10/05 - 20050251712 - Skew adjusing circuit and semiconductor integrated circuit An output signal of a flip flop at an output stage is supplied to delay gates connected in series thereto. A selector selects the output signal of the flip flop at the output stage or an output signal of one of the delay gates and supplies the selected signal to ... 11/10/05 - 20050251711 - Systems and methods for time corrected lightning detection A lightning detection system provides an estimated location of a lightning stroke. The system includes sensors, and an analyzer. Each sensor provides messages having sensor identification, an amplitude responsive to the lightning stroke, and a time of detecting the lightning stroke. The analyzer applies time corrections and amplitude corrections to ... 11/10/05 - 20050251710 - Testing of integrated circuit receivers A method for testing a data recovery circuit (DRC) includes disturbing a running variable in a closed control loop of the DRC, as the DRC is processing a received test signal. Data recovered by the DRC, while the DRC was affected by the disturbance, is evaluated. Other embodiments are also ... 11/03/05 - 20050246596 - Auto-calibration method for delay circuit An auto-calibration method is applied to a delay circuit, which includes a plurality of delay chains. One of the delay chains is previously designated as the delay path where data output from the delay circuit passes through. The accumulative number of errors is continuously detected and counted during a unit ... 10/20/05 - 20050235177 - Path delay test method From layout information which was generated from a net list of a semiconductor integrated circuit, extracted are a critical path to guaranteed operating frequency and physical information such as wiring congestion and via density, and on the basis of the physical information, a place to be easily broken down is ... 09/15/05 - 20050204208 - Digital data receiver for edge cellular standard A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first ... 07/28/05 - 20050166101 - Method for the synchronization of two digital data flows with identical content c) shifting the time periods of duration T assigned to the digital data streams S1 and S2 relative to each other by calculating a criterion of superposition of said trajectories having an optimum value representing the required synchronization; d) choosing the shift between the time periods corresponding to said optimum ... 07/21/05 - 20050160331 - Pica system timing measurement and calibration PICA probe system methods and apparatus are described, including methods and apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp. ... 07/07/05 - 20050149779 - Circuit for producing a variable frequency clock signal having a high frequency low jitter pulse component A system and method provides a pulse train clock signal having a portion appropriate for loading and loading a scan chain of a circuit under test, and a higher frequency portion with a sharp leading edge appropriate for inputting a test signal into the scan elements for transition fault testing. ... 07/07/05 - 20050149778 - on-chip timing characterizer An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of the programmable ... 07/07/05 - 20050149777 - Characterizing circuit performance by separating device and interconnect impact on signal delay An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. ... ### FreshPatents.com Support |