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Electrical Computers And Digital Processing Systems: Support > Clock Control Of Data Processing System, Component, Or Data Transmission Clock Control Of Data Processing System, Component, Or Data TransmissionClock Control Of Data Processing System, Component, Or Data Transmission patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070255976 - Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data ... 11/01/07 - 20070255975 - Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data ... 10/04/07 - 20070234100 - Method and apparatus for changing the clock frequency of a memory system One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the clock frequency to the new clock frequency. More ... 09/27/07 - 20070226531 - Clock generator and clock generating method using delay locked loop Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second ... 09/06/07 - 20070208965 - Method and apparatus for improving bus master performance A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored ... 08/30/07 - 20070204186 - Processor with flexible clock configuaration A network processor or other type of processor includes clock generation circuitry which generates one or more clock signals for each of a number of clock domains of the processor. The clock generation circuitry comprises at least one clock generator and at least one control register subject to software-based updating. ... 08/16/07 - 20070192651 - Low-speed dll employing a digital phase interpolator based upon a high-speed clock A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. ... 08/16/07 - 20070192650 - Multi-processing system distributing workload optimally during operation A multi-processing system includes: a selecting unit that selects a clock frequency for each processor chips based on lot-to-lot variation thereof; a calculating unit that calculates chip performance of the processor chips operating at the clock frequencies; a judging unit that judges whether a total of chip performance of the ... 07/26/07 - 20070174651 - Processor system, instruction sequence optimization device, and instruction sequence optimization program To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assignment controlling section outputs the instruction code to a CPU or ... 07/26/07 - 20070174650 - Efficiency optimization method for hardware devices with adjustable clock frequencies An efficiency optimization method for hardware devices with adjustable clock frequencies is provided. The work current of the hardware device is measured and used to obtain the corresponding work level from a conversion table. The obtained work level is compared with the currently executing work level to make adjustments for ... 07/12/07 - 20070162780 - Method for controlling an operating frequency of a processor during playback of a recorded video A method for controlling the operating frequency of a processor during video playback is disclosed. The method comprises extracting a pack of video data in which is embedded a plurality of data size information of a plurality of video data segments for playback. The plurality of data size information from ... 05/17/07 - 20070113117 - Hybrid parallel/serial bus interface A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A ... 04/12/07 - 20070083787 - Method and device for exchanging data between at least two stations connected via a bus system A method and a device for exchanging data in messages between at least two stations connected via a bus system, the messages containing the data being transmitted by the stations over the bus system and the messages being controlled over time by a first station in such a manner that ... 04/05/07 - 20070079167 - Clock domain crossing Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred ... 02/08/07 - 20070033429 - Instantaneously restartable clocks and their use such as in connecting clocked subsystems using clockless sequencing networks Disclosed are, inter alia, instantaneously restartable clocks and their use. For example, instantaneously restartable clocks can be used to receive data from another independently clocked subsystem in a manner that removes the possibility of metastability errors. A restartable clocking signal generator, relying on oscillating signals typically generated by a continuous ... 01/04/07 - 20070006012 - Engineering the di/dt curve In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also includes a clock source to provide a clock signal to said plurality of functional blocks. At least one gating device is used ... 12/21/06 - 20060288250 - Low-speed dll employing a digital phase interpolator based upon a high-speed clock A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs ... 12/14/06 - 20060282696 - Storage and access control method for storage Embodiments of the invention prevent a storage from being continuously used in a state in which the time of a built-in clock is different from the actual time because of replacement of a battery or intentional tampering of time. In one embodiment, a storage having a recording medium for storing ... 11/30/06 - 20060271807 - Semiconductor integrated circuit device, an electronic apparatus including the device, and a power consumption reduction method A semiconductor integrated circuit is disclosed that operates in synch with a clock signal supplied from an external source, and by a voltage supplied by a power supply. The circuit includes a detection means for detecting that at least one of a frequency of the clock signal and the supply ... 11/23/06 - 20060265623 - Mobile equipment with time control for drm schemes The present invention provides a mobile equipment for non stationary use. The mobile equipment includes a real time clock (RTC) integrated in the mobile equipment for generating a real time information, a system time generator integrated in the mobile equipment for generating a system time information by adding an offset ... 10/26/06 - 20060242449 - Clock control of a multiple clock domain data processor A processor clock control device operable to control a plurality of clock signals output to a processor,- said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test ... 10/12/06 - 20060230304 - Frequency control method and information processing apparatus According to one embodiment, a method of controlling an operating frequency of a control unit of an apparatus having the control unit for controlling processing operation, includes accepting designation of an upper limit value of the frequency, calculating a value of the frequency in accordance with a type of processing ... 10/12/06 - 20060230303 - Circuit, system and method for selectively turning off internal clock drivers The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that ... 10/05/06 - 20060224912 - Clock distribution for interconnect structures Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure ... 09/28/06 - 20060218429 - Method and system for configuring a timer The present invention facilitates access to timers in a computing device. In particular, a timer system facilitates configuring a hardware interrupt timer in a computing device, the timer being guaranteed to expire at a specific time in a non-real-time environment. A calling application passes parameters to a hardware independent application ... 09/14/06 - 20060206746 - Microcomputer A microcomputer includes a CPU, a program memory for storing a subroutine program, peripheral circuits, a clock circuit, and a voltage drop detection circuit. When the voltage drop detection circuit detects the voltage drop at the end of a power line, a frequency of a clock signal provided through the ... 09/14/06 - 20060206745 - Automatic resource assignment in devices having stacked modules A stacked module device and corresponding module and method are provided where at least some of the modules have access to resources. At least one of the at least some modules have assigned at least one of the resources and comprises assignment means which is adapted to assign at least ... 09/14/06 - 20060206744 - Low-power high-throughput streaming computations A method for optimizing voltage and frequency for pipelined architectures that offers better power efficiency. The invention provides methods for low-power high-throughput hardware implementations to stream computations by partitioning a computation into temporally distinct stages, assigning a clock frequency to each stage such that an overall computational throughput is met ... 09/14/06 - 20060206743 - Computer system having a clock controller for controlling an operating clock inputted into a no-wait-state microprocessor and method thereof The present invention discloses a computer system with a clock controller for controlling an operating clock inputted into a no-wait-state microprocessor. The computer system includes a data cache memory and a system memory. The clock controller blocks the operating clock from driving the no-wait-state microprocessor if data requested by the ... 08/24/06 - 20060190758 - Signals crossing multiple clock domains Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number of input/output (I/O) ports are provided to couple signals to and from the ASIC. The circuit includes means for moving ... 08/24/06 - 20060190757 - Monitoring multiple clock domains Methods, systems, and circuits are provided for monitoring multiple clock domains. One method for monitoring multiple clock domains includes pipelining different sets of signals from different clock domains on an application specific integrated circuit (ASIC) to a particular input/output (I/O) port on the ASIC using an associated clock from each ... 08/03/06 - 20060174153 - Clock control method and apparatus for a memory array A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When ... 07/27/06 - 20060168466 - Universal serial bus adaptive signal rate In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the Universal Serial Bus cable is calculated, and the speed of the Universal Serial ... 07/20/06 - 20060161799 - Method and device for setting the clock frequency of a processor In order to set the clock frequency of a processor it is proposed that a processor load value be determined, representing a measure for the instructions carried out by the processor during a unit of time, and the clock frequency of a clock signal of the processor be set depending ... 06/29/06 - 20060143491 - Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe ... 05/25/06 - 20060112295 - Information processing device using variable operation frequency An information processing apparatus and an information processing method for use therewith are provided so as to implement optimal signal processing without deterioration of performance when using variable operating frequencies. A frequency information operating section (12) of the apparatus adds a corresponding signal cycle to frequency information Inf about a ... 05/18/06 - 20060107083 - Controlling clock rates using configuration information Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked signal of received clock signals by determining a ... 05/11/06 - 20060101301 - Non-volatile memory device The operational information read out by the read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, ... 04/20/06 - 20060085662 - Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more ... 03/09/06 - 20060053329 - Data transfer control device, electronic equipment, and data transfer control method A data transfer control device including a buffer is provided which includes an EP2 area (a data storage area set to FIFO) and a CSW area (a randomly accessible status storage area), when data and a CSW are allocated as information to be transferred through one end point EP2. When ... 02/16/06 - 20060036888 - Reset in a system-on-chip circuit An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the ... 02/09/06 - 20060031705 - Single request data transfer regardless of size and alignment A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a ... 02/09/06 - 20060031704 - Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A specified number of clock cycles may then ... 02/02/06 - 20060026450 - Dynamic clock control circuit and method A variable clock control information generator receives vertical blank interval information corresponding to a vertical blank interval (VBI) during display rasterization. The vertical blank interval is a period of time in a video display signal that temporarily suspends transmission of video data as is known during display rasterization, to allow ... 12/22/05 - 20050283634 - Method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of the data. A value representative of at least the number of said buffers that are nearly empty of data as compared ... 12/22/05 - 20050283633 - Method and system for securing a device The present invention is directed to a method and system for securing a device (e.g. a security token). The method comprising the steps of: providing physical actuation mechanism (e.g. a switch) to the device; disabling some function(s) of the device (e.g. the communication channel with the host); upon actuating the ... 12/08/05 - 20050273641 - Comma detection An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code ... 12/01/05 - 20050268144 - Detecting a timeout of elements in an element processing system Provides methods, systems and apparatus for timer management of an element processing system wherein timer intervals related to elements to be processed can be handled in a time-efficient manner. An example method is a method for detecting a timeout of elements in an element processing system wherein a timer value, ... 12/01/05 - 20050268143 - Information processing system and method for timing adjustment An elapsed cycle number during the predetermined period of the inputted clock source is counted using the clock reference signal as a yardstick, a frequency of the clock source is computed based on an elapsed cycle number obtained by counting, control timing of various interfaces relating to the CPU is ... 12/01/05 - 20050268142 - Pipelined clock stretching circuitry and method for i2c logic system A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for ... 11/24/05 - 20050262376 - Method and apparatus for bussed communications Some embodiments of this invention relate to methods and apparatus for implementing bussed transactions between one or more components connected to a system bus. A clock generator circuit generates an independent clock signal for each component connected to the system bus. The clock generator circuit may use system signals, sideband ... 10/06/05 - 20050223262 - Pipeline module circuit structure with reduced power consumption and method of operating the same A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A ... 09/22/05 - 20050210310 - Method and apparatus for operating peripheral units on a bus A method and apparatus for operating peripheral units of a computer on a bus. The maximum number of peripheral units is ascertained and an optimal clock frequency, which corresponds to the number ascertained and at which the bus is operated, is determined. ... 09/22/05 - 20050210309 - Cpu frequency adjusting system and method A Central Processing Unit (CPU) frequency adjusting system has a multi-level architecture including an application level, a driver level, a hardware abstraction level, and a hardware platform. The application level includes a user interface (10) for generating a command signal to adjust a CPU frequency according to an input from ... 09/01/05 - 20050193224 - Computer clock management system and method A clock management system includes a user interface (101), a clock manager (102), a real-time clock (104), and a CPU clock (105). The user interface is used for obtaining a current time from the clock manager, and for providing a platform for users to set a current time to the ... 07/21/05 - 20050160303 - Method, apparatus, and program for minimizing invalid cache notification events in a distributed caching environment A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management system in the receiving device then uses this information to adjust event information ... 06/30/05 - 20050144498 - [method and apparatus for tuning over clock and tuning method for sub-stable state with high performance] A method and apparatus for tuning over clock is provided. At first, a first time out and a second time out are set up, wherein the first time out is greater than the second time out. Then, the system is restarted to transfer the system from an initial stable state ... 06/23/05 - 20050138459 - Method and apparatus for controlling amount of buffer data in a receiver of a data communication system, and method and apparatus for playing streaming data with adaptive clock synchronization unit A method and apparatus for controlling an amount of buffer data in a receiver of a data communication system, and a method and apparatus for playing back streaming data stored in a buffer, using an adaptive clock synchronization unit. The apparatus for controlling an amount of buffer data in a ... 06/23/05 - 20050138458 - System and method for signal timing A system includes a data path that provides a data signal at a first frequency corresponding to a first clock signal. A strobe generator generates a strobe signal at the first frequency. The strobe signal is synchronized with the data signal based on a second clock signal having a second ... ### FreshPatents.com Support |