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Electrical Computers And Digital Processing Systems: Support > Clock, Pulse, Or Timing Signal Generation Or Analysis > Correction For Skew, Phase, Or Rate Correction For Skew, Phase, Or RateCorrection For Skew, Phase, Or Rate patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/01/07 - 20070255974 - System for checking clock-signal correspondence A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between ... 08/16/07 - 20070192649 - Controlling an accumulation of timing errors in a synchronous system Apparatus (100) for communicating clock correction data between two or more clocked entities (102, 104) using a standardized clock correction unit or quanta. A source-native pre-scaler (302) can convert source-native clock correction values to scaled source-native clock correction values. The pre-scaler can perform this conversion by multiplying each source-native clock ... 07/19/07 - 20070168688 - Clock control hierarchy for integrated microprocessors and systems-on-a-chip A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units ... 06/14/07 - 20070136621 - Transmitter with skew reduction An integrated circuit device is described. The circuit device may include a group of signal nodes, including a first signal node and a second signal node, a transmitter coupled to the group of signal nodes, and a first clock circuit coupled to the transmitter. The transmitter may transmit a first ... 06/07/07 - 20070130486 - Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models A method of enabling CRPR in an ETM. In an exemplary embodiment, the method includes locating a plurality of clocks defined within a core. The method may also include determining if one of the plurality of clocks are clocking data both within the core and outside of the core. A ... 05/31/07 - 20070124623 - Circuit and method for aligning data transmitting timing of a plurality of lanes A circuit and a method for aligning data transmitting timing of a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count ... 03/22/07 - 20070067661 - Communicating client phase information in an io system A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data ... 03/15/07 - 20070061607 - Use of t4 timestamps to calculate clock offset and skew Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data ... 03/01/07 - 20070050658 - Skew adjusting circuit and method for parallel signals The skew adjusting circuit for parallel signals includes: a deskew signal generating circuit which generates a deskew signal by performing a predetermined logical operation and transmits the deskew signal to a receiving circuit; a skew detecting circuit which detects the skew by obtaining correlation between the deskew signal and the ... 01/18/07 - 20070016821 - Method and apparatus to change transmission line impedance For at least one disclosed embodiment, a die may be provided that includes a transmission line (or waveguide) and a signal-generating device to generate a pulse on the transmission line and to receive a pulse from the transmission line. A plurality of transistors may be provided along a length of ... 01/04/07 - 20070006011 - Nibble de-skew method, apparatus, and system De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits. ... 10/26/06 - 20060242448 - Circuit including a deskew circuit A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. ... 10/12/06 - 20060230302 - Circuit and method for generating programmable clock signals with minimum skew A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the ... 09/14/06 - 20060206742 - System and method for using a learning sequence to establish communications on a high- speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and ... 08/24/06 - 20060190756 - Clock recovery systems and methods for adjusting phase offset according to data frequency A clock recovery system includes a sampler that is configured to sample an input data signal in synchronization with a modulated clock signal to generate a sample of the input data signal. A phase comparator is configured to compute a position of a transition edge of the input data signal ... 08/17/06 - 20060184817 - Elastic interface de-skew mechanism A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock ... 08/03/06 - 20060174152 - Parallel path alignment method and apparatus A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presented on a negative edge of ... 06/15/06 - 20060129869 - Data de-skew method and system Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines. ... 05/04/06 - 20060095811 - Apparatus and method for graphics memory controlling hub (gmch) clocking support for dual television encoders An apparatus and method for graphics memory controlling hub (GMCH) clocking support for dual television encoders are described. In an embodiment, the apparatus is a GMCH that includes a digital video output (DVO) interface, a DVO clock input, and a reconfigured video graphics array (VGA) clock input. The DVO interface ... 03/16/06 - 20060059382 - Method of skew adjustment In a multi-service platform system (300), a method of skew adjustment can include providing an initiator VME module (302) coupled to a responder VME module (304) over a parallel multi-drop bus network (306). The initiator VME module communicates a calibration cycle (316) to the responder VME module during a calibration ... 03/09/06 - 20060053328 - Training pattern based de-skew mechanism and frame alignment Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment. ... 02/23/06 - 20060041773 - Signal processor and method for processing a signal A signal processor includes a reference clock generator configured to generate a reference clock as a synchronization reference for a signal processing. A counter is configured to count the reference clock. A frequency controller is configured to sample a count value of the counter by utilizing an input clock, to ... 02/09/06 - 20060031703 - Methods and systems to reduce data skew in fifos The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, ... 02/09/06 - 20060031702 - Time of day response In an implementation of time of day response, time logic executed by each processor element of a logical processor generates a logical time in response to a time of day request. The logical time is generated to approximate the actual time such that each processor element of the logical processor ... 02/02/06 - 20060026449 - Robust and scalable de-skew method A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a ... 01/26/06 - 20060020843 - Technique to create link determinism A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents. ... 09/22/05 - 20050210308 - Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of ... 06/30/05 - 20050144497 - System and method for reducing clock skew In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock ... ### FreshPatents.com Support |