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Electrical Computers And Digital Processing Systems: Support > Clock, Pulse, Or Timing Signal Generation Or Analysis

Clock, Pulse, Or Timing Signal Generation Or Analysis

Clock, Pulse, Or Timing Signal Generation Or Analysis patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

09/18/14 - 20140281655 - Transducer clock signal distribution
An array of ultrasonic transducers can be controlled to produce a steerable beam. Beam steering can be skewed by buffer delays in the distribution of a clock signal. The skew can be at least approximately linearized by distributing the clock signal in a diagonal fashion across an array of buffers...

06/26/14 - 20140181569 - Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices without a voltage controlled crystal oscillator
Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In...

06/19/14 - 20140173323 - Timing control circuit
A timing control circuit includes a single chip having a plurality of output ports; a chip selecting circuit having a plurality of control ports connected to the output ports and paths; a signal input circuit; a signal output circuit; and a switching circuit including a plurality of signal channels. The...

06/12/14 - 20140164816 - Distributed management of a shared clock source to a multi-core microprocessor
Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a...

05/22/14 - 20140143583 - Circuit for generating usb peripheral clock and method therefor
A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the...

05/08/14 - 20140129867 - Selective insertion of clock mismatch compensation symbols in signal transmissions
In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device...

04/03/14 - 20140095918 - Method and apparatus for maintaining secure time
An exemplary method of maintaining secure time in a computing device is disclosed in which one or more processors implements a Rich Execution Environment (REE), and a separate Trusted Execution Environment (TEE). The TEE maintains a real-time clock (RTC) that provides a RTC time to the REE. A RTC offset...

03/27/14 - 20140089718 - Clock domain boundary crossing using an asynchronous buffer
An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency...

03/27/14 - 20140089719 - Planning unambiguously across multiple time zones
A time slot of regular time length and capacity is defined in time local to a time zone. The slot is defined by a local time start timestamp and a local time end timestamp. In one aspect, upon determining that the local time end timestamp of the slot overlaps with...

03/20/14 - 20140082400 - Enhanced clock gating in retimed modules
Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first...

03/13/14 - 20140075236 - Memory interface circuits including calibration for cas latency compensation in a plurality of byte lanes
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined...

02/06/14 - 20140040653 - Synchronizing sensor data using timestamps and signal interpolation
A method of synchronizing sensor data using timestamps and interpolation. The method includes receiving sequences of time-stamped data indicative of physical events from each of a plurality of sensors; generating an interpolation filter according to desired sampling times; and interpolating the sequences of time-stamped data with the generated filter to...

01/09/14 - 20140013150 - Monitoring circuit with a window watchdog
A method of monitoring a processing circuit is disclosed. The processing circuit is operable, in a normal operation mode, to generate a sequence of trigger commands, with at least one trigger command of the sequence of trigger commands including time information. At least one window sequence with a closed window...

11/21/13 - 20130311815 - Providing adaptive frequency control for a processor
In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the...

11/14/13 - 20130305078 - System on chip (soc), method of operating the soc, and system having the soc
A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock...

11/07/13 - 20130297962 - Bridge device
A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal The inverter generates a first signal and a second signal at...

10/17/13 - 20130275798 - Semiconductor device, control method for the semiconductor device and information processing system including the same
The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output...

09/19/13 - 20130246833 - Clock generator and information processing apparatus
A clock generator includes a first clock generating unit configured to generate a first clock signal based on a system clock signal, a second clock generating unit configured to generate a second clock signal with a frequency higher than the frequency of the first clock signal based on the system...

09/05/13 - 20130232372 - Integrated circuit, voltage value acquisition method, and transmission and reception system
An integrated circuit includes a data signal reception unit that receives a data signal transmitted from a transmission circuit, a timing signal reception unit that receives a timing signal transmitted from the transmission circuit and indicating a reading timing of the data signal, a timing adjustment unit that adjusts an...

07/25/13 - 20130191677 - Regional clock gating and dithering
A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating...

06/27/13 - 20130166939 - Apparatus, system, and method for providing clock signal on demand
Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a...

06/27/13 - 20130166940 - Semiconductor device and method for operating the same
A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the...

06/13/13 - 20130151883 - Method and devices for controlling operations of a central processing unit
Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry...

06/06/13 - 20130145197 - Method and system to improve the operations of a registered memory module
A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory...

05/16/13 - 20130124905 - Sense amplifier and method for determining values of voltages on bit-line pair
A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal...

05/16/13 - 20130124906 - Signal collection system with frequency reduction unit and signal collection method
An exemplary signal collection system includes a signal transmitting module and a computer. The signal transmitting module outputs a high-speed signal with a high frequency. The signal collection system further includes a data collection module interconnecting the signal transmitting module and the computer. The data collection module includes a frequency...

05/16/13 - 20130124907 - Clock gating circuit and bus system
The present technology provides an excellent advantageous effect in terms of reducing power consumption of a bus system adapted to treat a transaction as a unit. Disclosed herein is a clock gating circuit including: a clock enable signal generation portion adapted to count the number of outstanding transactions in each...

05/02/13 - 20130111255 - Clock transfer circuit and semiconductor device including the same
A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the...

04/18/13 - 20130097452 - Computer apparatus and resetting method for real time clock thereof
A computer apparatus and a resetting method for a real time clock (RTC) of the computer apparatus are provided. The resetting method for the RTC includes: generating a judging result by determining whether the computer apparatus is in an S5 state and determining whether a plurality of pre-determined keys are...

04/11/13 - 20130091375 - Advanced array local clock buffer base block circuit
A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the...

03/28/13 - 20130080818 - Conversion of timestamps between multiple entities within a computing system
Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used...

02/28/13 - 20130055003 - Methods and apparatuses including a global timing generator and local control circuits
Apparatus and methods are disclosed, such as a global timing generator coupled to local control circuits. Each local control circuit can control programming and reading of a memory element in a tile of memory elements in an array responsive to a timing signal(s) from the global timing generator. Additional apparatus...

01/17/13 - 20130019120 - Method and system for reducing thermal load by forced power collapse
A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t0 to t1. A timer is set to trigger a forced power collapse (“FPC”) that removes all power to the processor from time...

11/22/12 - 20120297232 - Adjusting the clock frequency of a processing unit in real-time based on a frequency sensitivity value
A system, method, and medium for adjusting an input clock frequency of a processor in real-time based on one or more hardware metrics. First, the processor is characterized for a plurality of workloads. Next, the frequency sensitivity value of the processor for each of the workloads is calculated. Hardware metrics...

09/20/12 - 20120239962 - Method and a device for controlling a clock signal generator
A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and...

09/13/12 - 20120233488 - Adjustment of a processor frequency
A system comprises a processor, a connection to the processor, a monitoring component arranged to monitor the connection to the processor, a performance counter connected to the monitoring component and arranged to establish a ratio between processor idle time and processor busy time, and a policy component connected to the...

08/30/12 - 20120221882 - Reducing latency in serializer-deserializer links
A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates....

08/16/12 - 20120210157 - Interface clock management
The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock...

06/28/12 - 20120166858 - Apparatus and method for processing wirelessly communicated data and clock information within an electronic device
An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14) may include a first processor (18) that controls only wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12),...

06/07/12 - 20120144224 - Adjusting a device clock source to reduce wireless communication interference
Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it...

06/07/12 - 20120144225 - Verification
A circuit simulator includes at least one clock generator. The at least one clock generator is configured to generate at least one root clock signal for an associated clock domain part of the circuit under simulation. The circuit simulator also includes a clock modifier configured to generate at least one...

04/26/12 - 20120102353 - Data processing apparatus, data processing system, measurement system, data processing method, measurement method, electronic device and recording medium
Provided is a data processing system that processes input data, comprising a data generating apparatus that generates the input data and a data processing apparatus that processes the input data generated by the data generating apparatus. The data processing apparatus includes a time interpolation section that generates time interpolated data,...

04/05/12 - 20120084593 - Method and system for providing a current time value
A method for providing applications with a current time value includes receiving a trap for an application to access a time memory page, creating, in a memory map corresponding to the application, a mapping between an address space of the application and the time memory page in response to the...

02/16/12 - 20120042192 - Frequency reference correction for temperature-frequency hysteresis error
A method is disclosed for improving the effective frequency stability of a frequency reference source, wherein an algorithm utilizing parameters determined from frequency and temperature sensing measurements of the source or a similar source over a number of temperature excursions of different magnitude is used in conjunction with temperature history...

02/09/12 - 20120036389 - Precision oscillator for an asynchronous transmission system
A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART...

01/26/12 - 20120023358 - Host device, peripheral device, communication system, and communication method
In a communication system in which data is transmitted and received in synchronization with a clock signal, a peripheral device cannot transfer data to a host device when the host device stops outputting the clock signal and thus the peripheral device cannot promptly transmit an interrupt request to the host...

01/05/12 - 20120005517 - Synchronisation and timing method and apparatus
A method and system for synchronising a first device and at least one second device, each having a local oscillator and a microcontroller, and the second device being in data communication with the first device via a communication bus. The method comprises the first device transmitting a plurality of signals...

12/29/11 - 20110320852 - Clock circuit and reset circuit and method thereof
A clock circuit is suitable for use in a timing circuit which provides time information according to a reference clock. The clock circuit includes a clock detector to detect whether or not an interruption of the reference clock occurs. When the interruption of the reference clock occurs, a clock interruption...

12/29/11 - 20110320853 - Communication interface device and communication method
A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first...

11/03/11 - 20110271134 - Apparatus and methods employing variable clock gating hysteresis for a communications port
An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of...

10/20/11 - 20110258476 - Apparatus for detecting presence or absence of oscillation of clock signal
A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count...