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Clock, Pulse, Or Timing Signal Generation Or Analysis

Clock, Pulse, Or Timing Signal Generation Or Analysis patent applications listed include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.

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Electrical Computers And Digital Processing Systems: Support


Clock, Pulse, Or Timing Signal Generation Or Analysis



Semiconductor apparatus and memory system
11/20/14 - 20140344613 - A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common...

Synthetic time series data generation
10/30/14 - 20140325251 - According to an example, synthetic time series data generation may include receiving time series data for a plurality of users, and applying dimensionality reduction to transform the time series data from a high dimensional space n of the time series data to a low dimensional space m, where m<n. The...

Transducer clock signal distribution
09/18/14 - 20140281655 - An array of ultrasonic transducers can be controlled to produce a steerable beam. Beam steering can be skewed by buffer delays in the distribution of a clock signal. The skew can be at least approximately linearized by distributing the clock signal in a diagonal fashion across an array of buffers...

Systems and methods for synchronizing operations among a plurality of independently clocked digital data processing devices without a voltage controlled crystal oscillator
06/26/14 - 20140181569 - Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In...

Timing control circuit
06/19/14 - 20140173323 - A timing control circuit includes a single chip having a plurality of output ports; a chip selecting circuit having a plurality of control ports connected to the output ports and paths; a signal input circuit; a signal output circuit; and a switching circuit including a plurality of signal channels. The...

Distributed management of a shared clock source to a multi-core microprocessor
06/12/14 - 20140164816 - Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a...

Circuit for generating usb peripheral clock and method therefor
05/22/14 - 20140143583 - A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the...

Selective insertion of clock mismatch compensation symbols in signal transmissions
05/08/14 - 20140129867 - In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device...

Method and apparatus for maintaining secure time
04/03/14 - 20140095918 - An exemplary method of maintaining secure time in a computing device is disclosed in which one or more processors implements a Rich Execution Environment (REE), and a separate Trusted Execution Environment (TEE). The TEE maintains a real-time clock (RTC) that provides a RTC time to the REE. A RTC offset...

Clock domain boundary crossing using an asynchronous buffer
03/27/14 - 20140089718 - An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency...

Planning unambiguously across multiple time zones
03/27/14 - 20140089719 - A time slot of regular time length and capacity is defined in time local to a time zone. The slot is defined by a local time start timestamp and a local time end timestamp. In one aspect, upon determining that the local time end timestamp of the slot overlaps with...

Enhanced clock gating in retimed modules
03/20/14 - 20140082400 - Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first...

Memory interface circuits including calibration for cas latency compensation in a plurality of byte lanes
03/13/14 - 20140075236 - A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined...

Synchronizing sensor data using timestamps and signal interpolation
02/06/14 - 20140040653 - A method of synchronizing sensor data using timestamps and interpolation. The method includes receiving sequences of time-stamped data indicative of physical events from each of a plurality of sensors; generating an interpolation filter according to desired sampling times; and interpolating the sequences of time-stamped data with the generated filter to...

Monitoring circuit with a window watchdog
01/09/14 - 20140013150 - A method of monitoring a processing circuit is disclosed. The processing circuit is operable, in a normal operation mode, to generate a sequence of trigger commands, with at least one trigger command of the sequence of trigger commands including time information. At least one window sequence with a closed window...

Providing adaptive frequency control for a processor
11/21/13 - 20130311815 - In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the...

System on chip (soc), method of operating the soc, and system having the soc
11/14/13 - 20130305078 - A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock...

Bridge device
11/07/13 - 20130297962 - A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal The inverter generates a first signal and a second signal at...

Semiconductor device, control method for the semiconductor device and information processing system including the same
10/17/13 - 20130275798 - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output...

Clock generator and information processing apparatus
09/19/13 - 20130246833 - A clock generator includes a first clock generating unit configured to generate a first clock signal based on a system clock signal, a second clock generating unit configured to generate a second clock signal with a frequency higher than the frequency of the first clock signal based on the system...

Integrated circuit, voltage value acquisition method, and transmission and reception system
09/05/13 - 20130232372 - An integrated circuit includes a data signal reception unit that receives a data signal transmitted from a transmission circuit, a timing signal reception unit that receives a timing signal transmitted from the transmission circuit and indicating a reading timing of the data signal, a timing adjustment unit that adjusts an...

Regional clock gating and dithering
07/25/13 - 20130191677 - A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating...

Apparatus, system, and method for providing clock signal on demand
06/27/13 - 20130166939 - Described herein are apparatus, system, and method for providing clock signal on demand. The method comprises determining an indication of clock signal usage in multiple hardware logic units; generating an enable signal according to the indication; and gating or un-gating the clock signal for clock islands of at least a...

Semiconductor device and method for operating the same
06/27/13 - 20130166940 - A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the...

Method and devices for controlling operations of a central processing unit
06/13/13 - 20130151883 - Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry...

Method and system to improve the operations of a registered memory module
06/06/13 - 20130145197 - A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory...

Sense amplifier and method for determining values of voltages on bit-line pair
05/16/13 - 20130124905 - A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal...

Signal collection system with frequency reduction unit and signal collection method
05/16/13 - 20130124906 - An exemplary signal collection system includes a signal transmitting module and a computer. The signal transmitting module outputs a high-speed signal with a high frequency. The signal collection system further includes a data collection module interconnecting the signal transmitting module and the computer. The data collection module includes a frequency...

Clock gating circuit and bus system
05/16/13 - 20130124907 - The present technology provides an excellent advantageous effect in terms of reducing power consumption of a bus system adapted to treat a transaction as a unit. Disclosed herein is a clock gating circuit including: a clock enable signal generation portion adapted to count the number of outstanding transactions in each...

Clock transfer circuit and semiconductor device including the same
05/02/13 - 20130111255 - A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the...

Computer apparatus and resetting method for real time clock thereof
04/18/13 - 20130097452 - A computer apparatus and a resetting method for a real time clock (RTC) of the computer apparatus are provided. The resetting method for the RTC includes: generating a judging result by determining whether the computer apparatus is in an S5 state and determining whether a plurality of pre-determined keys are...

Advanced array local clock buffer base block circuit
04/11/13 - 20130091375 - A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the...

Conversion of timestamps between multiple entities within a computing system
03/28/13 - 20130080818 - Method is described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used...

Methods and apparatuses including a global timing generator and local control circuits
02/28/13 - 20130055003 - Apparatus and methods are disclosed, such as a global timing generator coupled to local control circuits. Each local control circuit can control programming and reading of a memory element in a tile of memory elements in an array responsive to a timing signal(s) from the global timing generator. Additional apparatus...

Method and system for reducing thermal load by forced power collapse
01/17/13 - 20130019120 - A system and method for reducing heat in a portable computing device includes clocking a processor such that it is provided with a full frequency over time t0 to t1. A timer is set to trigger a forced power collapse (“FPC”) that removes all power to the processor from time...

Adjusting the clock frequency of a processing unit in real-time based on a frequency sensitivity value
11/22/12 - 20120297232 - A system, method, and medium for adjusting an input clock frequency of a processor in real-time based on one or more hardware metrics. First, the processor is characterized for a plurality of workloads. Next, the frequency sensitivity value of the processor for each of the workloads is calculated. Hardware metrics...

Method and a device for controlling a clock signal generator
09/20/12 - 20120239962 - A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and...

Adjustment of a processor frequency
09/13/12 - 20120233488 - A system comprises a processor, a connection to the processor, a monitoring component arranged to monitor the connection to the processor, a performance counter connected to the monitoring component and arranged to establish a ratio between processor idle time and processor busy time, and a policy component connected to the...

Reducing latency in serializer-deserializer links
08/30/12 - 20120221882 - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates....

Interface clock management
08/16/12 - 20120210157 - The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock...

Apparatus and method for processing wirelessly communicated data and clock information within an electronic device
06/28/12 - 20120166858 - An electronic device (12) for processing information that includes data and clock information and that is wirelessly received from another electronic device (14) may include a first processor (18) that controls only wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12),...

Adjusting a device clock source to reduce wireless communication interference
06/07/12 - 20120144224 - Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it...

Verification
06/07/12 - 20120144225 - A circuit simulator includes at least one clock generator. The at least one clock generator is configured to generate at least one root clock signal for an associated clock domain part of the circuit under simulation. The circuit simulator also includes a clock modifier configured to generate at least one...

Data processing apparatus, data processing system, measurement system, data processing method, measurement method, electronic device and recording medium
04/26/12 - 20120102353 - Provided is a data processing system that processes input data, comprising a data generating apparatus that generates the input data and a data processing apparatus that processes the input data generated by the data generating apparatus. The data processing apparatus includes a time interpolation section that generates time interpolated data,...

Method and system for providing a current time value
04/05/12 - 20120084593 - A method for providing applications with a current time value includes receiving a trap for an application to access a time memory page, creating, in a memory map corresponding to the application, a mapping between an address space of the application and the time memory page in response to the...

Frequency reference correction for temperature-frequency hysteresis error
02/16/12 - 20120042192 - A method is disclosed for improving the effective frequency stability of a frequency reference source, wherein an algorithm utilizing parameters determined from frequency and temperature sensing measurements of the source or a similar source over a number of temperature excursions of different magnitude is used in conjunction with temperature history...

Precision oscillator for an asynchronous transmission system
02/09/12 - 20120036389 - A precision oscillator for an asynchronous transmission system. An integrated system on a chip with serial asynchronous communication capabilities includes processing circuitry for performing predefined digital processing functions on the chip and having an associated on chip free running clock circuit for generating a temperature compensated clock. An on-chip UART...

Host device, peripheral device, communication system, and communication method
01/26/12 - 20120023358 - In a communication system in which data is transmitted and received in synchronization with a clock signal, a peripheral device cannot transfer data to a host device when the host device stops outputting the clock signal and thus the peripheral device cannot promptly transmit an interrupt request to the host...

Synchronisation and timing method and apparatus
01/05/12 - 20120005517 - A method and system for synchronising a first device and at least one second device, each having a local oscillator and a microcontroller, and the second device being in data communication with the first device via a communication bus. The method comprises the first device transmitting a plurality of signals...

Clock circuit and reset circuit and method thereof
12/29/11 - 20110320852 - A clock circuit is suitable for use in a timing circuit which provides time information according to a reference clock. The clock circuit includes a clock detector to detect whether or not an interruption of the reference clock occurs. When the interruption of the reference clock occurs, a clock interruption...

Communication interface device and communication method
12/29/11 - 20110320853 - A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first...

Apparatus and methods employing variable clock gating hysteresis for a communications port
11/03/11 - 20110271134 - An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of...

Apparatus for detecting presence or absence of oscillation of clock signal
10/20/11 - 20110258476 - A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count...

Keeping time in multi-processor virtualization environments
10/13/11 - 20110252266 - A virtual machine receives a request for a current time. The virtual machine determines an approximation of the current time based on readings from one of a plurality of processors and compares the approximation to a virtual machine time stamp value. If the approximation is smaller than the virtual machine...

Mesochronous signaling system with clock-stopped low power mode
09/29/11 - 20110239031 - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal,...

Convolution operation circuit and object recognition apparatus
09/29/11 - 20110239032 - In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative...

Programmable drive strength in memory signaling
09/22/11 - 20110231692 - Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the...

Numerically controlled oscillator and oscillation method for generating function values using recurrence equation
09/22/11 - 20110231693 - Numerically controlled oscillators and oscillation methods for generating function values in respective clock cycles by using a recurrence equation are provided. The oscillation circuit generates, in each of the clock cycles, a current one of the function values by multiplying, using a multiplier having a latency of k clock cycles,...

Data processing device and mobile device
09/22/11 - 20110231694 - A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver...

Packaged circuit
09/01/11 - 20110214004 - A packaged circuit includes an internal circuit, an embedded clock generator, a plurality of multi-function pins and a control pad. The embedded clock generator is for generating an internal clock. The pins include a clock output pin and a clock input pin. The clock output pin outputs the internal clock...

Latency signal generator and method thereof
08/25/11 - 20110208988 - A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit...

Data processing unit and a method of processing data
08/11/11 - 20110197086 - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and...

Reducing latency in serializer-deserializer links
08/04/11 - 20110191619 - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates....

Multicore processor and onboard electronic control unit using same
08/04/11 - 20110191620 - A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality...

Systems, methods, software, and components using tamper-proof real-time clock
07/14/11 - 20110173480 - The write-access control line for an RTC is combined with a clear line for an RTC signature register, so that changes to the RTC will cause subsequent reads to return an invalidity flag....

Clock generator and usb module
06/09/11 - 20110138214 - A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at...

Clock signal generating device and electronic device
06/09/11 - 20110138215 - The clock signal generating device is provided with a second control unit that, when the target frequency changes, successively changes the voltage impressed on the clock signal generating unit with a preset change value and a preset interval in a preset time in place of the first control unit, causing...

Semiconductor memory device, method of adjusting the same and information processing system including the same
04/21/11 - 20110093735 - Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read...

Spi devices and method for transferring data between the spi devices
03/24/11 - 20110072297 - A method for transferring data between a serial peripheral interface (SPI) master device and an SPI slave device generates a first clock signal for the SPI master device and a second clock signal for the SPI slave device. Clock frequency of the first clock signal and the second clock signal...

Generating a random number in an existing system on chip
03/10/11 - 20110060935 - A system for generating a true random number and implemented within an existing System on Chip (SoC) is provided herein. The system includes one or more sub circuitry synchronous modules configured to operate in a specified nominal clock rate, wherein each sub circuitry synchronous modules yields expected deterministic results when...

Providing adaptive frequency control for a processor
02/24/11 - 20110047401 - In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the...