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Electrical Computers And Digital Processing Systems: Support > Clock, Pulse, Or Timing Signal Generation Or Analysis Clock, Pulse, Or Timing Signal Generation Or AnalysisClock, Pulse, Or Timing Signal Generation Or Analysis patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070260907 - Technique to modify a timer A technique to modify a timer. More particularly, at least one embodiment of the invention relates to a technique to modify a timer value without the timer advancing by a significant amount. ... 11/01/07 - 20070255972 - Microprocessor capable of dynamically increasing its performance in response to varying operating temperature A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency being the maximum frequency at which the microprocessor will reliably operate at ... 10/25/07 - 20070250735 - Semiconductor integrated circuit A microcontroller formed on a single chip semiconductor includes a central processing unit; an oscillator unit adapted to generate a system clock, and an electrical fuse unit including a control information for trimming a frequency of the oscillator unit. The central processing unit is operable to generate said control information ... 10/25/07 - 20070250734 - Hybrid computer security clock A clock object is provides, which includes a clock time and a monotonic time that are readable by the electronic device. The monotonic time is incremented every read of the monotonic time from the clock object. The clock object can also include an indication of a level of trust of ... 10/18/07 - 20070245166 - Timer with periodic channel service A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the ... 10/11/07 - 20070240012 - Memory interface circuitry with phase detection Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals ... 10/11/07 - 20070240011 - Fifo memory data pipelining system and method for increasing i²c bus speed An I2C system includes an I2C bus which includes an SCK (serial clock) conductor and an SDA (serial data) conductor, a master device coupled to the SCK conductor and the SDA conductor for sending and receiving data signals and serial clock signals. The master device includes a CPU, clock generation ... 10/11/07 - 20070240010 - Phase frequency detector with limited output pulse width and method thereof Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first ... 10/04/07 - 20070234098 - Self-timed clock-controlled wait states A peripheral device in a processor system which can generate system level wait states to temporarily stop the clock of a processor is disclosed. The system comprises at least one peripheral device, a wait-unknowledgeable processor, and a clock controller. The peripheral device generates a wait signal when the peripheral device ... 09/27/07 - 20070226530 - Media data synchronization in a wireless network A method of keeping global time in a wireless network, the method comprising the steps of: using a first 802.11 chip set to read a Time Synchronization Function (TSF) to provide an initial time base; using an interconnected clock control circuit to read the TSF time directly from the 802.11 ... 08/23/07 - 20070198869 - Timer apparatus, timer processing method, and electronic apparatus The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves efficient timer generation. The present invention includes a count setting unit (register) presetting a timer value that should be set at the time of completion of ... 08/09/07 - 20070186125 - Electronic circuit and method for operating an electronic circuit An electronic circuit is disclosed, having a primary circuit that processes at least one information signal with a predefinable frequency, and having a peripheral clock generator for supplying at least one secondary circuit with a peripheral clock signal. A frequency of the peripheral clock signal is chosen as a function ... 07/26/07 - 20070174649 - Switching circuit and method thereof for dynamically switching host clock signals A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second phase-locked loop generating a second host clock signal and an output switch unit coupled to the first PLL and the ... 07/26/07 - 20070174648 - Method and apparatus for dividing a digital signal by x.5 in an information handling system An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit ... 07/26/07 - 20070174647 - Coordinating data synchronous triggers on multiple devices System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common ... 07/19/07 - 20070168686 - Method and apparatus for over clocking in a digital processing system A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a clock signal at an initial frequency; increasing said frequency in a step-wise manner and determining the operation of said system each of a selected number ... 07/05/07 - 20070157050 - Process for providing submodel performance in a computer processing unit A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count ... 06/14/07 - 20070136620 - Clock distribution in multi-cell computing systems Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. ... 06/14/07 - 20070136619 - Jitter tolerant delay-locked loop circuit Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a ... 05/17/07 - 20070113116 - Method and apparatus for transferring multi-source/multi-sink control signals using a differential signaling technique A method and apparatus arc disclosed for transferring multi-source/multi-sink control signals using a differential signaling technique. An “active” state is transferred on a multi-source/multi-sink control signal network by inverting the previous voltage level, and an “inactive state” is transferred by maintaining the previous level. A change in the voltage level ... 05/17/07 - 20070113115 - Switching circuit for clock signals An exemplary switching circuit assembly for clock signals includes a chipset, a flip-flop, and a multiplexer. The multiplexer is connected between the chipset and the multiplexer. The chipset receives a reset signal and is reset by the reset signal. The flip-flop receives the reset signal and generates a control signal. ... 05/03/07 - 20070101177 - Synchronous type semiconductor device Disclosed is a synchronous semiconductor device including clock generation circuit that frequency divides a clock signal (PCLK) input from an input buffer and generates first and second internal clock signals having a predetermined phase difference from first and second frequency-divided clock signals of different phases, respectively, a first input circuit ... 04/12/07 - 20070083786 - Robust and scalable de-skew method for data path skew control A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a ... 04/05/07 - 20070079166 - Compensated-clock generating circuit and usb device having same A compensated-clock generating circuit that complies with USB specifications includes an oscillating circuit that generates clock pulses; a counting circuit that counts the number of clock pulses from the oscillating circuit based upon a regular prescribed signal in accordance with a USB downstream signal; and a frequency compensation value generating ... 04/05/07 - 20070079165 - Multi-stage clock selector A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages ... 03/29/07 - 20070074061 - Bus receiver and method of deskewing bus signals A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and ... 03/29/07 - 20070074060 - Dynamic adjusting circuit for basic clock signal of front-side bus and method thereof By adjusting a scale factor of a phase locked loop in computers for generating a basic clock signal of a front-side bus, the frequency of the basic clock signal is modulated when the central processing unit of computers operates. By a bridge unit of the present invention, a selecting signal ... 03/29/07 - 20070074059 - System and method for dynamic power management in a processor design A system and method for dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall ... 03/15/07 - 20070061606 - Method and apparatus for limiting processor clock frequency A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible ... 03/15/07 - 20070061605 - System and method for tod-clock steering A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes computing a TOD-clock offset value (d) to be added to a physical-clock ... 03/08/07 - 20070055904 - Dynamically changing pci clocks A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock signal from the peripheral device's own internal clock controller. ... 03/01/07 - 20070050657 - Optimum stable composite clock network An apparatus and method are disclosed or producing a network of composite clocks with optimized stability characteristics from individual clocks that are part of a network wherein not all clocks are in communication with each other. By communicating information among the clocks in the network, each clock can construct its ... 02/22/07 - 20070043966 - Dynamic clock change circuit A clock change circuit includes enabling a clock change frequency to be accepted while a system is active and clock frequencies are at a low period. The circuit includes generating an enabling signal representing a window of time in which a frequency change is accomplished. ... 02/15/07 - 20070038879 - Single wire serial interface A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ... 02/15/07 - 20070038878 - Generator of a signal with an adjustable waveform A generator of a signal including a memory in which instructions are stored, each instruction including a code portion and an argument portion; circuitry for successively reading instructions stored in the memory; decoding circuitry capable of receiving, for each read instruction, the code portion of the instruction and of providing ... 02/08/07 - 20070033428 - Network interface with double data rate and delay locked loop A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the ... 02/08/07 - 20070033427 - Power efficient cycle stealing Arrangements and methods to cycle steal and reduce power consumption in an integrated circuit are disclosed. Embodiments of the invention exploit the art of cycle stealing for increased system performance, while facilitating a more power efficient bypass mode when power conservation is desired over performance. One embodiment includes a network ... 01/25/07 - 20070022312 - Clock generation circuit A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input ... 01/18/07 - 20070016819 - Method and system for fast frequency switch for a power throttle in an integrated device The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor. ... 01/18/07 - 20070016818 - System and method for tracking engine cycles A system and method for detecting/calculating engine cycles, tracking engine cycles and correlating the engine cycles to parts to measure accumulated cycles associated with the parts. A system is disclosed that includes a parts tracking system for tracking serialized parts contained within the machine; an interface for importing cycles data ... 01/18/07 - 20070016817 - Multiple clock domain microprocessor A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain. ... 01/18/07 - 20070016816 - Method and system for a clock circuit Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a ... 01/11/07 - 20070011483 - Delay-lock loop and method adapting itself to operate over a wide frequency range A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate ... 01/11/07 - 20070011482 - Clock generator, radio receiver using the same, function system, and sensing system A clock generator having phase locked loops to receive reference signals from a shared reference signal source and generate clock signals differing in frequency, respectively, includes a phase comparator which generates a voltage signal in response to a phase difference between a phase of the reference signal and a phase ... 01/04/07 - 20070006010 - Synchronous signal generator A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic ... 12/28/06 - 20060294411 - Method and apparatus for source synchronous testing A method and apparatus for source synchronous testing have been disclosed. ... 12/28/06 - 20060294410 - Pvt drift compensation A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing ... 12/28/06 - 20060294409 - Frequency margin testing A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency ... 12/21/06 - 20060288249 - Demand-based dynamic clock control for transaction processors A variable speed data processor includes a clock generator generating a plurality of clocks at different clock rates. Clock select circuitry synchronously selects one of the clocks as an output clock signal to data processing circuitry, based on a data activity indication. Activity logic generates the data activity indication based ... 12/07/06 - 20060277428 - A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors A method for generating clocks and delaying execution of an instruction within a hardware accelerator. ... 11/30/06 - 20060271806 - Method for improving the data transfer in semi synchronous clock domains integrated circuits at any possible m/n clock ratio A method for data transfer between two semi-synchronous clock domains in a System on Chip (SoC) includes first and second integrated processors or circuits respectively operating at first and second clock frequencies The SoC includes a phase for detecting, for each frequency ratio between the first and second clock frequencies, ... 11/16/06 - 20060259807 - Method and apparatus for clock synchronization between a processor and external devices An external data signal serves as the basis for clocking a processor. In particular, a processor clock signal is generated from the external data signal which has a frequency that is an integer multiple of the frequency (data rate) of the external data signal. In this way, metastable conditions arising ... 11/02/06 - 20060248368 - Fast data access mode in a memory device A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access ... 10/26/06 - 20060242446 - Clock control circuit A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock ... 10/05/06 - 20060224911 - Digital clock switching means A digital clock switching circuit and method is disclosed and is operable to deadlock-free switch a digital clock source for an integrated circuit. The circuit includes a first finite state machine associated with a first clock source and a second finite state machine associated with a second clock source. The ... 10/05/06 - 20060224910 - Circuit and method for monitoring the status of a clock signal A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates ... 09/28/06 - 20060218428 - Systems and methods for operating within operating condition limits Systems and methods for operating within operating condition limits are disclosed. One embodiment of a system may comprise a margin detector that generates a specification value that is a function of a plurality of operating factors associated with a core circuit and compares the specification value with a predetermined threshold ... 09/21/06 - 20060212739 - Digital circuit to measure and/or correct duty cycles A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems ... 08/31/06 - 20060195714 - Clock control device, microprocessor, electronic device, clock control method, and clock control program The number of pulses of an operation clock to a microprocessor can be easily and instantaneously controlled and changed, in which a clock control device 2 supplies a clock of the same pulse number as the system clock 8, while a bus busy signal 10 that indicates a bus 4 ... 08/17/06 - 20060184816 - Pre-emptive power supply control system and method A device comprising an integrated circuit including at least one circuit block having an operating mode controlled in response to an enable signal or a clock signal. The circuit block receives a load current to power the circuit block, an amplitude of the load current being a function of the ... 08/17/06 - 20060184815 - System including an operating speed detection apparatus, an operating speed detection apparatus and method thereof A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock ... 08/17/06 - 20060184814 - Redundant oscillator distribution in a multi-processor server system The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first ... 08/10/06 - 20060179339 - Interface circuit that interconnects a media access controller and an optical line termination transceiver module A communication system includes an interface that allows a media access controller (MAC) and an optical line termination transceiver module (TM), which have incompatible interfaces, to be connected together. The interface detects a phase relationship required by the TM, and feeds the information back to a processor and memory which ... 08/03/06 - 20060174151 - Traffic analyzer and power state management thereof A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the ... 07/20/06 - 20060161798 - Network synchronization technique A network synchronization method allows reduced frequency fluctuations due to synchronization control in a network. Each node connected to the network has time information individually varying in a period of T. A time master node periodically notifies its own time information to time slave devices. Each time slave node prepares ... 07/13/06 - 20060156050 - System and method of determining the speed of digital application specific integrated circuits According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous ... 07/13/06 - 20060156049 - Digital clock dividing circuit Disclosed is a digital dividing circuit for dividing a timing signal. Memory elements are disposed in opposed pairs at opposed sides of a data loop. Each memory element is clocked to change the data bit it stores on each clock pulse. At least two opposed nodes along the data loop ... 07/06/06 - 20060149989 - Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first ... 06/29/06 - 20060143490 - Inter-device adaptable interfacing clock skewing Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed ... 06/22/06 - 20060136770 - Method and apparatus for on-demand power management A method for on-demand power management monitors a processing demand in a processing system operating at a first set of voltages and frequencies and generates a second set of voltages and frequencies in response to the processing demand. The method switches from the first set of voltages and frequencies to ... 06/15/06 - 20060129868 - Clock transferring apparatus and test device There is provided a clock transferring apparatus that outputs input data given in synchronization with a transmission clock in synchronization with an internal clock having a phase different from that of the transmission clock. The clock transferring apparatus includes: a comparison clock generating section that generates a comparison clock of ... 06/15/06 - 20060129867 - Overclock detection An overclock detector may define a plurality of detection periods based upon a reference clock signal. Further, the overclock detector may activate an overclock response in response to determining an operating clock signal generating too many cycles in each of a plurality of consecutive detection periods. ... 06/08/06 - 20060123265 - Semiconductor memory module A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a ... 06/01/06 - 20060117205 - Data processing device with cooling fan In the data processing device with cooling fan 3 for cooling down the processor 1 that performs data processing, the device includes: a working rate calculating section 4 for calculating the working rate of the processor 1; and a control section 5 for activating the cooling fan 3 when the ... 05/11/06 - 20060101300 - Phase-locked-loop power control during standby A clock generator for supplying one or more clock signals to integrated circuits within a processor-based system is disclosed. The clock generator includes one or more PLLs and one or more configuration registers. The clock is supplied power from two different voltage sources, such that, during a standby mode of ... 05/04/06 - 20060095810 - Microcomputer, method of controlling cache memory, and method of controlling clock A microcomputer that can increase the usage efficiency of a cache memory and increase the process speed is provided. In this microcomputer, a group of registers hold cache usage information that specifies whether the cache memory is to be used in execution of a process. When processes to be executed ... 05/04/06 - 20060095809 - Methods and systems for clock signal distribution and fault location detection in a multi-shelf modular computing system A method and system are described for distributing at least one clock signal between shelves in a multi-shelf modular computing system includes a clock signal generator for generating a first clock signal, an inter-shelf bus for carrying the first clock signal to a second shelf, and a first shelf manager ... 04/13/06 - 20060080566 - Low power clocking systems and methods A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of ... 03/16/06 - 20060059381 - System and method for configuring a microcontroller clock system A method is provided for configuring a microcontroller clock system that includes a main oscillator, a phase locked loop, and a backup oscillator. According to the method, the main oscillator and the backup oscillator are activated in reset mode. A clock signal is generated from the backup oscillator, and the ... 03/02/06 - 20060047991 - Real time clock architecture and/or method for a system on a chip (soc) application An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate ... 02/23/06 - 20060041772 - Timing generator, test apparatus and skew adjusting method There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first variable delay circuit that delays a ... 02/09/06 - 20060031701 - Cmos burst mode clock data recovery circuit using frequency tracking method Provided is a burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock. The circuit includes a bit-rate corrector generating an inversed signal at every half cycle of the clock when transition of input data is generated, the ... 02/09/06 - 20060031700 - Circuit and method for generating clock signals for clocking digital signal processor and memory A circuit is provided for generating clock signals for clocking a digital signal processor (DSP) and a memory, the circuit comprising of a clock generator for receiving a first clock, generating a DSP clock signal by dividing the first clock by X, and generating a memory clock signal based on ... 02/09/06 - 20060031699 - Asic clock floor planning method and structure A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks 110; positioning a temporary reference insertion point (TIP) 120; grouping the sinks together with structured clock buffers (SCBs) in a set of levels 140; and moving the SCBs to ... 12/08/05 - 20050273640 - Method and system for flexible clock gating control Distributing clock signals within an electronic device may comprise determining a status of at least one gate that controls flow of a clock signal to at least one device coupled to the gate. One or more of the gates may be controlled based on this determined status and it may ... 12/01/05 - 20050268141 - Method and apparatus for power management of graphics processors and subsystems thereof A graphics processing device implementing a set of techniques for power management, preferably at both a subsystem level and a device level, and preferably including peak: power management, a system including a graphics processing device that implements such a set of techniques for power management, and the power management methods ... 12/01/05 - 20050268140 - Network interface with double data rate and delay locked loop A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the ... 12/01/05 - 20050268139 - Main-board and control method thereof A main-board comprises a CPU, a chipset and a clock-rate control-signal generating module. The chipset has at least a phase-locked circuit, a CPU-bus circuit and a memory-bus circuit. The phase-locked circuit is electrically connected to the CPU-bus circuit and the memory-bus circuit. The CPU-bus circuit is electrically connected to the ... 11/24/05 - 20050262375 - System and method for efficient cabac clock A system and method that process data in a circuitry utilizing two clocks. The two clocks may be an offset version of one another. Utilizing two clocks to processes the data may consume fewer clock cycles than using only one clock. The circuitry may comprise registers and a memory, wherein ... 11/24/05 - 20050262374 - Information processing apparatus and media storage apparatus using the same An information processing apparatus switches a clock to reduce power consumption of an information processing unit. In order to reduce an overhead time in switching, the information processing apparatus includes an interrupt controller for generating a clock switch signal by accepting an interrupt to each information processing unit and a ... 11/10/05 - 20050251701 - Distributed control and monitoring system In a more efficient distributed control or monitoring arrangement there are devices in control, monitoring and/or vehicle systems that comprise locally deployed module units that carry out one or more functions, and one or more links connecting the units. The respective module unit is connected to a link via a ... 10/20/05 - 20050235176 - Intelligent frequency and voltage margining A system and method for voltage and frequency margining of a digital system such as a digital processing system. Various implementations of the present invention may be utilized to programmatically vary the voltage and or frequency utilized by one or more components within a processing system to effect changes in ... 10/20/05 - 20050235175 - Circuit for generating wait signal in semiconductor device The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or irregularly inputted, the circuit for generating the wait signal in the semiconductor device generates the wait signal suitable for a ... 09/29/05 - 20050216780 - Clock signal generator circuit for serial bus communication Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code ... 09/08/05 - 20050198550 - Timer systems and methods Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter. ... 08/25/05 - 20050188236 - System and method for providing clock signals A system comprising a clock control module, a first functional unit, and a second functional unit is provided. The clock control module is configured to provide a first clock signal having a first frequency to the first functional unit in response to receiving a start signal. The clock control module ... 07/28/05 - 20050166079 - Apparatus and method for adaptation of time synchronization of a plurality of multimedia streams A system and method for adaptation of time synchronization of a plurality of multimedia streams is presented. In one embodiment, multimedia data is captured, via a plurality of multimedia platforms. A first synchronization signal is received by each of the plurality of multimedia platforms. The first synchronization signal is used ... 07/07/05 - 20050149774 - System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and ... ### FreshPatents.com Support |