REGISTER now for FREE 
|
FREE patent keyword monitoring and additional FREE benefits. REGISTER now for FREE
|
|
|
Electrical Computers And Digital Processing Systems: Support > Synchronization Of Clock Or Timing Signals, Data, Or Pulses > Using Delay Using DelayUsing Delay patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.09/27/07 - 20070226529 - Memory controller and device with data strobe calibration A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled ... 09/20/07 - 20070220295 - Method and apparatus for providing symmetrical output data for a double data rate dram An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop ... 09/13/07 - 20070214378 - Apparatus for adjusting timing of memory signals An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, ... 09/13/07 - 20070214377 - Dynamic timing adjustment in a circuit device A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a ... 08/30/07 - 20070204184 - Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of ... 08/23/07 - 20070198868 - Memory system having delayed write timing A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the ... 07/05/07 - 20070157049 - Adjusting input output timing The frequency of a bus with at least three agents is limited by both setup and hold timings between any two agents coupled to the bus. To adjust for the setup condition, the bus lengths between any two agents can be short. To adjust for the hold condition, the bus ... 11/30/06 - 20060271805 - System for motion control, method of using the system for motion control, and computer readable instructions for use with the system for motion control A motion control system and method that includes a central controller configured to generate first and second demand control signals to be used to define actuation motion of respective first and second actuators. The central controller is in communication with first and second nodes by way of a data network, ... 11/09/06 - 20060253721 - Adjustable byte lane offset for memory module to reduce skew Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte ... 11/02/06 - 20060248367 - Count calibration for synchronous data transfer between clock domains Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data ... 07/06/06 - 20060149988 - Calculating apparatus having a plurality of stages A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it ... 07/06/06 - 20060149987 - Keep-out clock alignment cycle coherency protection In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been ... 06/29/06 - 20060143489 - System and method for power saving delay locked loop control The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon ... 06/22/06 - 20060136769 - Interface circuit for strobe-based systems Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components of a host system use the masked strobe signal to ... 06/15/06 - 20060129866 - Test validation of an integrated device Embodiments of a method and/or an apparatus to test a delay lock loop circuit, chipset, or memory controller or memory controller hub (MCH) are described. ... 06/15/06 - 20060129865 - Method and apparatus for data transfer A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system ... 06/01/06 - 20060117204 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 05/25/06 - 20060112294 - Method and apparatus to deskew data to clock for memory A description of deskewing data from the clock from a DRAM, such as, but not limited to a DDR3 DRAM is discussed. For example, the differential signals of a strobe and a clock signal are used to create a first and second loops that can be fed back to a ... 03/30/06 - 20060069940 - Measure controlled delay with duty cycle control The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a delayed input signal, a counter adapted to determine a difference between the input signal ... 02/23/06 - 20060041771 - Phase adjusted delay loop In an embodiment of the invention, a method for a phase adjusted delay loop, includes: determining a requested delay value for a code path; and executing a delay loop in the code path in order to obtain a loop delay value that is in phase with the requested delay value. ... 12/22/05 - 20050283632 - Delay control in semiconductor device In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a ... 11/24/05 - 20050262373 - Dll phase detection using advanced phase equal A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The ... 11/10/05 - 20050251700 - Dynamic voltage scaling system Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to ... 10/27/05 - 20050240791 - Interleaved delay line for phase locked and delay locked loops An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay ... 08/18/05 - 20050182988 - Adaptive clock skew in a variably loaded memory bus The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to ... 06/23/05 - 20050138457 - Synchronization devices having input/output delay model tuning elements A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the ... ### FreshPatents.com Support |