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Electrical Computers And Digital Processing Systems: Support > Synchronization Of Clock Or Timing Signals, Data, Or Pulses Synchronization Of Clock Or Timing Signals, Data, Or PulsesSynchronization Of Clock Or Timing Signals, Data, Or Pulses patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.11/08/07 - 20070260906 - Clock synchronization method and apparatus A clock synchronization apparatus; a network having master and slave clocks; and a method of synchronizing clocks are disclosed. ... 10/11/07 - 20070240009 - Semiconductor device A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a ... 10/11/07 - 20070240007 - Technique for providing service processor access to control and status registers of a module A technique for providing service processor (SP) access to registers, e.g., control and status registers (CSRs), located within hardware modules of a computer system, ensures access to the CSRs within a predetermine time period. The computer system includes a host module (HM) and a plurality of client modules (CMs). The ... 08/16/07 - 20070192648 - Data processing system It is an object to obtain a self-synchronization type block processing apparatus which does not need to optimize a clock path to be distributed to each block in a clock phase management at an upper level, and can suppress an increase in a circuit scale and can minimize an increase ... 08/09/07 - 20070186124 - Data handover unit for transferring data between different clock domains The invention provides a data handover unit for transferring data from a first clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a ... 07/05/07 - 20070157048 - Duty cycle rejecting 2:1 serializing mux for output data drivers A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. ... 06/21/07 - 20070143641 - System for clock synchronization for modules in an analytical device A system for synchronizing clock signals in an analytical device includes a first module including a timing command generator configured to generate a command signal, the command signal related to a master clock signal, and a second module including a command interpreter configured to generate a timing reference signal related ... 04/19/07 - 20070088968 - Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of ... 04/05/07 - 20070079164 - Frequency divider and an electronic device incorporating such a frequency divider The frequency divider for high-frequency clock signal comprises: a shift register (8) having cells (10-13) for storing each bit of an initial word, said cells being series connected in a loop (14), and said shift register being capable of shifting each bit of the initial word from the cell in ... 03/22/07 - 20070067660 - Asymmetrical io method and system An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to ... 03/08/07 - 20070055903 - Method for ensuring synchronous presentation of additional data with audio data A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment ... 03/01/07 - 20070050656 - Information processing apparatus and method of setting frequency of clock to be supplied from processor An information processing apparatus includes a processor, and a detector to detect the operation clock frequency set for a unit connected to a bus. The frequency of a clock to be supplied from the processor is set in accordance with the detected clock frequency. ... 01/04/07 - 20070006009 - Methods and apparatus for aligning data In a first aspect, a first method is provided for aligning data. The first method includes the steps of (1) transmitting identical reference data from first logic to second logic on each of a plurality of busses coupling the first logic to the second logic; (2) determining values indicative of ... 12/21/06 - 20060288248 - Information processing apparatus with adjustable system clock An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a ... 12/21/06 - 20060288247 - Synchronization of firmware signal updates to regular clock frequency The present invention provides a method and apparatus for improving the synchronization of timing signals in a system where firmware is being employed. In particular, the present invention enables the firmware to generate signals with a timing that is required by a hardware protocol. The resulting system is thus able ... 12/07/06 - 20060277427 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 12/07/06 - 20060277426 - Memory device, use thereof and method for synchronizing a data word The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output connected to a control input of the ... 11/23/06 - 20060265622 - Synchronization devices having input/output delay model tuning elements Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, tuning elements may be provided at various points in the signal path of the synchronization device. The ... 11/23/06 - 20060265621 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 11/23/06 - 20060265620 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 11/23/06 - 20060265619 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 11/23/06 - 20060265618 - Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay ... 11/16/06 - 20060259806 - Self-calibrating time code generator Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a phase difference between an absolute time reference signal and a compensated ... 11/16/06 - 20060259805 - Programmable phase generator for cross-clock communication where the clock frequency ratio is a rational number A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a ... 10/26/06 - 20060242445 - Method and apparatus for designing a pll A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior ... 10/26/06 - 20060242444 - Constraint-based conflict handling for synchronization The subject invention pertains to data synchronization across replicas. Disclosed are systems and methods of detecting and handling constraint-based conflicts that occur during a synchronization session. In accordance with one particular aspect of the invention, name-constraint violations can be detected. These violations can be resolved by generating a single merged ... 10/26/06 - 20060242443 - Synchronization move support systems and methods Disclosed are systems and methods pertaining to data synchronization and move handling support. In particular, a move log is maintained that identifies data that has moved in, out, and within a synchronization scope. Furthermore, the log comprises times associated with when data moves in and out of the synchronization scope. ... 10/26/06 - 20060242442 - Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to ... 10/19/06 - 20060236147 - Processor controlled interface Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment ... 10/19/06 - 20060236146 - Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, ... 09/28/06 - 20060218427 - Method and device for synchronizing the global time of a plurality of buses and a corresponding bus system A method, a device, and a bus system for synchronizing at least two buses having at least one bus user, a global time being determined in each bus, and the deviations in the global times of the buses being determined from the global times, the buses being connected via at ... 09/21/06 - 20060212738 - Distributed global clock for clusters of computers The present invention refers to a global clock system for clusters or networks of computers implemented entirely in hardware. The system uses a specifically designed hierarchical network to distribute clock pulses that are used to increment time counters in the cluster nodes. In addition, this network enables any node of ... 09/07/06 - 20060200694 - Controlling sequence of clock distribution to clock distribution domains An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls ... 08/31/06 - 20060195713 - Duty cycle distortion compensation for the data output of a memory device A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is ... 08/24/06 - 20060190755 - System-on-chip having adjustable voltage level and method for the same A system-on-chip may include a plurality of power domains each of which may have a different operating frequency and include a monitoring unit. A power supply may supply power to each of the power domains. A clock generator may output a reference clock to each of the monitoring units. A ... 08/24/06 - 20060190754 - A method for automatic recognition of handshake data exchange at clock-domain crossing in integrated circuit design A structural analysis tool automatically detects complex handshake mechanisms for controlling data transfers between clock-domain crossings. The structural analysis tool may also verify the correctness of the handshake mechanism. ... 07/20/06 - 20060161797 - Asynchronous wrapper for a globally asynchronous, locally synchronous (gals) circuit The invention concerns an asynchronous wrapper for a globally asynchronous, locally synchronous circuit. The asynchronous wrapper operates with a request signal-driven clock control, supplemented by a local clock unit in the absence of request signals. It has at least one input unit which is adapted to receive a request signal ... 06/22/06 - 20060136768 - Method and system for multi-program clock recovery and timestamp correction A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second ... 06/01/06 - 20060117203 - Maintaining synchronization of multiple data channels with a common clock signal Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock ... 06/01/06 - 20060117202 - Frequency and voltage scaling architecture A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others. ... 06/01/06 - 20060117201 - Variable pipeline circuit A variable pipeline comprises a first pipeline element configured to latch a first signal in response to a first edge of a clock signal to provide a second signal, a selection circuit configured to select the second signal and pass the second signal to provide a third signal, and a ... 05/25/06 - 20060112293 - Interface for compressed data transfer between host system and parallel data processing system An apparatus and method for interfacing a host system having a system data bus, clock signals, and control signals to a parallel data bus is described. Setting configuration bits allows the interface apparatus to be programmed to operate as a transmitter or a receiver with selectable device interface modes. When ... 05/04/06 - 20060095808 - Method and apparatus for using internal delays for adjusting setup and hold times in a memory device A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly within a the storage area of the memory device, so that the parasitic capacitance inherent within the address and control lines can be advantageously employed ... 04/27/06 - 20060090092 - Clock timing adjustment Apparatus and methods are provided for clock timing adjustment. One embodiment of a computing device, the device includes first processor, a memory in communication with the first processor. The device includes computer executable instructions stored in memory and executable on the first processor to identify a clock speed for a ... 04/13/06 - 20060080565 - Method and related apparatus for adjusting timing of memory signals A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then ... 04/13/06 - 20060080564 - Method and apparatus for storage device read phase auto-calibration The present invention provides a method and apparatus for performing read phase auto-calibration of a storage device. The method includes writing the data with at least one predetermined pattern into the storage device, reading the data according to a read phase of a plurality of read phases, comparing the predetermined ... 03/30/06 - 20060069939 - Device in a modularized system for effecting time-stamping of events/reference events A device for a modularized system with decentralized and function-executing modules comprising a module with associated clock that is arranged to effect time-stamping of events associated with the system and of reference events selected from among these. The module comprises a memory device for storing the module's time stamps relating ... 03/09/06 - 20060053327 - Method and system for a message processor switch for performing incremental redundancy in edge compliant terminals Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor ... 03/02/06 - 20060047990 - System and method for data storage and transfer between two clock domains In a memory hub system, several daisy-chained memory hubs are connected to a single memory controller. The memory hub transmitters and receivers operate in a high-speed clock domain, while the logic cores of the memory hubs operate in a low-speed clock domain. A clock domain interface advantageously provides data storage ... 02/09/06 - 20060031698 - Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of ... 02/09/06 - 20060031697 - Method and system for reducing the effects of simultaneously switching outputs A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, ... 02/09/06 - 20060031696 - Method and apparatus for determining time An apparatus (200) for determining time within a global navigation satellite receiver comprises a correlator (1), a combiner (35, 37), a comparator, and a processor. The correlator (1) comprises a means for determining a common data pattern between received signals of at least two satellites, and a means for calculating ... 01/26/06 - 20060020841 - Alternate multi-threaded pipeline An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within ... 01/26/06 - 20060020840 - Timing vector program mechanism Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed ... 01/26/06 - 20060020839 - Drift-tolerant sync pulse circuit in a sync pulse generator A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first ... 01/12/06 - 20060010334 - Information processing device, method, and program This invention relates to an information processing apparatus as well as to an information processing method and a program for use therewith, the apparatus being arranged to prevent a drop in its processing performance while minimizing power dissipation when a frequency-variable synchronizing clock signal CLK of the apparatus is lowered ... 12/29/05 - 20050289379 - System and method for producing precision timing signals Systems and methods are provided for providing precision timing signals. A first register bank, driven by a first clock signal, provides a first delay along a first signal path. A second register bank, driven by a second clock signal related to the first clock signal, provides a second delay along ... 12/08/05 - 20050273639 - Adaptive data processing scheme based on delay forecast The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and ... 12/01/05 - 20050268138 - Network interface using programmable delay and frequency doubler A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output ... 12/01/05 - 20050268137 - Method and apparatus for a shared i/o network interface controller A network interface controller is provided which is shareable by a plurality of operating system domains within their load-store architecture. The controller includes local resources for each of the plurality of operating system domains which allow them to communicate uniquely with the controller, and global resources which allow the controller ... 12/01/05 - 20050268136 - Timeout manager Embodiments include a timeout event management system that registers timeout events and checks for and corrects inaccuracies in timing caused by hibernation or system time changes. The timeout event management system may trigger an event after an intended delay time or at an intended expiration time. A handler program may ... 12/01/05 - 20050268135 - Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits ... 11/24/05 - 20050262372 - Microcomputer The present invention aims to be capable of properly measuring the cycle of an external signal even where a timer clock and a CPU clock are operated asynchronously. A timer circuit comprises a timer counter which counts a generation interval of an external signal in sync with the timer clock, ... 11/24/05 - 20050262371 - Systems and methods for the implementation of a peer-to-peer rule-based pull autonomous synchronization system The present invention relates to a synchronization system that utilizes a synchronization wizard (“PullSync”) residing on a first computer device to request and receive (or “pull”) data from a second computer device. The first computer device (the “syncer”) copies files from shared folders on the second computer device (the “syncee”) ... 11/10/05 - 20050251699 - Synchronous pipeline with normally transparent pipeline stages A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a ... 10/27/05 - 20050240790 - Clocking methodology for at-speed testing of scan circuits with synchronous clocks A clocking method for at-speed scan testing for delay defects in cross-domain paths of interacting synchronous clock domains in a scan circuit, each path originating from a source memory element in one of the domains and terminating at a destination memory element in another of the domains and comprises selectively ... 10/06/05 - 20050223261 - Communication clocking conversion techniques A plurality of groups of first flip-flops (group 40 of flip-flops A1-An−1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of ... 09/22/05 - 20050210306 - Method and apparatus for time synchronization in a network data processing system A method, apparatus, and computer implemented instructions for synchronizing time in a network data processing system. A request for time synchronization is received at a target data processing system. A current target time at the target data processing system is placed in a reply. The reply is sent to the ... 09/08/05 - 20050198549 - Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter ... 08/11/05 - 20050177758 - Method of and apparatus for measuring jitter and generating an eye diagram of a high speed data signal A sampling system is disclosed which measures high speed data signals by performing sampling events at intervals determined by a programmable DDS output frequency and a programmable counter. The reference frequency of the DDS is that of a clock signal that is synchronous with the data signal to be measured. ... 06/30/05 - 20050144496 - Method and system for synchronizing multimedia i/o with cpu clock According to one embodiment of the present invention, a novel method and system are disclosed. In one embodiment, an I/O device of a system receives or outputs a multimedia stream, the I/O device having a I/O clock and the system having a system clock. Samples from the multimedia stream are ... 06/23/05 - 20050138456 - Semiconductor memory device for reducing address access time An apparatus for controlling operations of a synchronous semiconductor memory device, wherein each operation is achieved by a plurality of internal instructions includes a reference clock block for receiving an external clock and outputting a plurality of delayed clock signals; a control block, in response to the plurality of delayed ... 06/23/05 - 20050138455 - Program clock synchronization in multimedia networks A method may include sampling a receive frequency at which information received over a communication link is played. The method may also include sampling a system frequency related to the communication link and computing a first value based on the sampled receive frequency and the sampled system frequency. A second ... 06/16/05 - 20050132245 - Data modem An improved data modem (IDM) and method includes a communication processor module, a mass storage module, a power converter module, and one or more DSP modules. The communication processor module utilizes commercial off-the-shelf components as well as electrically programmable logic devices (EPLD), which are programmed to provide a watchdog timer, ... 06/16/05 - 20050132244 - Byte alignment method and apparatus The method and apparatus correct for byte misalignment in a block of data. Switch means are set to perform a switching cycle depending on the amount of byte misalignment. Each word in the block is then transferred in accordance with the switching cycle, so that the bytes are aligned by ... 06/02/05 - 20050120258 - Synchronization method, computer system and program To implement an accurate synchronization by detecting a signal for time notice from an external reference clock without delay and acquiring the time of a system clock of comparison object at the present time without delay. A computer system comprises a time information inputting part 12 for detecting a signal ... 06/02/05 - 20050120257 - Packet processing system and method for a data transfer node with time-limited packet buffering in a central queue A method and system are provided for processing data packets at a data-transfer network node. The method and system include determining a length of time that a packet has been buffered at the node by associating a timer with each data packet received and buffered in the node's central queue. ... ### FreshPatents.com Support |