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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Processing Sequence Control (i.e., Microsequencing) Processing Sequence Control (i.e., Microsequencing)Processing Sequence Control (i.e., Microsequencing) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.07/06/06 - 20060149953 - Conditional execution per lane A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes ... 02/09/06 - 20060031663 - Synchronizing execution using a single-treaded scripting model Providing synchronization of data between application instances that execute script, and in preferred embodiments, without the use of synchronization primitives in the script and without the ability to reschedule events in at least one of the instances. Blocking code is provided in the application instances that is adapted for checking ... 01/19/06 - 20060015709 - Reconfigurable state machine architecture and related method of execution An architecture for a state machine (10) with a number of states of the machine, comprises a memory (14) having a set of addresses. The memory (14) is arranged to store at each of said addresses in the set the complete description of a respective one of said number of ... 01/05/06 - 20060004999 - Operation apparatus and operation apparatus control method An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising ... 01/05/06 - 20060004998 - Method and apparatus for speculative execution of uncontended lock instructions A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively ... 12/29/05 - 20050289331 - Instruction timing control within a data processing system A data processing system 2 is provided which is responsive to program instructions that operate in a variable timing mode to require a variable number of processing cycles to complete. The system is also operable in a fixed timing mode, which may be programmable using a bit (or several bits) ... 12/08/05 - 20050273583 - Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor One embodiment of the present invention provides a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued. During operation in a normal-execution mode, the processor issues instructions ... 09/08/05 - 20050198482 - Central processing unit having a micro-code engine A digital camera having a central processing unit with an embedded micro-code engine comprises a system memory capable of storing an instruction, at least one CPU execution unit electrically coupled with the system memory, and at least one micro-code engine electrically coupled with the CPU execution unit. The at least ... 06/02/05 - 20050120195 - Allocating memory A method includes allocating a memory entry in a memory device to instructions executed on a multithreaded engine included in a packet processor, a portion of the memory entry includes a unique identifier assigned to the instructions. ... ### FreshPatents.com Support |