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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Exeception Processing (e.g., Interrupts And Traps) Exeception Processing (e.g., Interrupts And Traps)Exeception Processing (e.g., Interrupts And Traps) patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/05/06 - 20060224873 - Acquiring instruction addresses associated with performance monitoring events Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include ... 07/27/06 - 20060168434 - Method and system of aligning execution point of duplicate copies of a user program by copying memory stores A method and system of aligning execution point of duplicate copies of a user program by copying memory stores. Some of the exemplary embodiments may be a method comprising aligning the execution point of duplicate copies of a user program executed in a first and second processor by copying only ... 07/06/06 - 20060149952 - Exception handling in a multiprocessor system In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as ... 01/26/06 - 20060020777 - Data processing apparatus In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master ... 01/05/06 - 20060004997 - Method and apparatus for computing A general purpose computing system comprises a novel apparatus and method for data processing. The computing system design of one application of the present invention includes an instruction pipe having a decompression circuit, a reprogrammable logic unit and a data bus. Instructions and data may be accessed via a shared ... 10/06/05 - 20050223205 - Early exception detection A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of ... 09/15/05 - 20050204121 - Prefetching exception vectors An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently ... 08/18/05 - 20050182920 - Apparatus and method for expedited exception handling using a dedicated port To expedite the response to an interrupt instruction, an interrupt identification component monitors the execution unit of the central processing unit. When an interrupt instruction is identified, the interrupt identification component forwards this information through a dedicated port to the exception handler, the exception handler storing the procedures that respond ... 08/04/05 - 20050172110 - Information processing apparatus A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means ... 08/04/05 - 20050172109 - Register pointer trap Trap flags and a pointer trap are associated with registers in a processor. Each trap flag indicates whether a corresponding register has been written with valid data. If not, the trap flag is set to indicate that the register corresponding to the trap flag contains invalid data. During instruction processing, ... 07/07/05 - 20050149711 - Method and system for firmware-based run time exception filtering A method and system for filtering and/or handling operating system (OS) runtime exceptions using firmware-based components. OS-based exception handling components and corresponding pointers, as applicable, are set up in a conventional manner during the OS load. The OS-based components are then physically or logically relocated (moved from a physical to ... ### FreshPatents.com Support |