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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > To Macro-instruction Routine To Macro-instruction RoutineTo Macro-instruction Routine patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/24/06 - 20060190711 - Method and apparatus for managing a return stack A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the ... 05/04/06 - 20060095752 - [method for return instruction identification and associated method for return target pointer prediction] A method and device for return instruction prediction in microprocessors and digital signal processors. The method and device uses a return target buffer, in which a return instruction address table serves to store addresses of return instructions, and a return target stack is used to store target pointers of return ... 02/02/06 - 20060026412 - Removing local ram size limitations when executing software code An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second ... 01/19/06 - 20060015708 - Microprocessor with branch target determination in decoded microinstruction code sequence In a microprocessor, customer code routines are decoded from ISA instructions into microinstructions and stored in a customer code store (CCS) for later, repeated execution. Branch target addresses in the ISA code, which use an ISA memory addressing format, are replaced with CCS branch target addresses in the decoded, stored ... 01/19/06 - 20060015707 - Microprocessor with customer code store A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into ... 11/17/05 - 20050257037 - Controlling execution of a block of program instructions within a computer processing system A data processing apparatus and method are disclosed. The data processing apparatus comprises: an instruction fetching circuit operable to fetch a sequence of program instructions from a sequence of memory locations; an instruction decoder responsive to program instructions within the sequence of program instructions fetched by the instruction fetching circuit ... 09/22/05 - 20050210226 - Function calling mechanism A data processing system 2 is provided which includes an instruction decoder 18 responsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler pointer in dependence upon a handler base address HBA and the index value field and then to branch to ... 07/14/05 - 20050154868 - Apparatus and method for processing a sequence of jump instructions An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or ... 06/30/05 - 20050144427 - Processor including branch prediction mechanism for far jump and far call instructions A method and apparatus are provided for processing far jump-call branch instructions to increase the efficiency of a processor pipeline. The processor includes a far jump-call target buffer which stores the default address/operand size corresponding to each of a plurality of previously executed far jump-call instructions. When a far jump-call ... 06/02/05 - 20050120194 - Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by ... ### FreshPatents.com Support |