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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Loop Execution Loop ExecutionLoop Execution patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.08/17/06 - 20060184779 - Pipeline controller for context-based operation reconfigurable instruction set processor An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated ... 07/27/06 - 20060168433 - Method and apparatus for efficient and flexible sequencing of data processing units extending vliw architecture A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based ... 07/20/06 - 20060161763 - Microcomputer and encoding system for instruction code and cpu A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral ... 05/18/06 - 20060107028 - Loop control circuit for a data processor A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at ... 05/11/06 - 20060101256 - Looping instructions for a single instruction, multiple data execution engine According to some embodiments, looping instructions are provided for a Single Instruction, Multiple Data (SIMD) execution engine. For example, when a first loop instruction is received at an execution engine information in an n-bit loop mask register may be copied to an n-bit wide, m-entry deep loop stack. ... 05/04/06 - 20060095751 - Method and system for providing zero overhead looping using carry chain masking A method and system for reducing overhead on a loop of a plurality of instructions is disclosed. The loop is performed a particular number of times. The method and system include a mask register and addition logic. The mask register provides a carry mask having a first value for the ... 04/06/06 - 20060075213 - Modular integration of an array processor within a system on chip A systolic array processor is integrated within a system on chip (SoC) in a format that is compatible with existing and emerging SoC technologies. The systolic array processor may be implemented as a co-processor to a general-purpose digital signal processor or as a functional unit of a very long instruction ... 02/02/06 - 20060026411 - Processor system and thread switching control method The present invention relates to a processor system. The processor system is made up of a multithread control unit for selectively making switching among said threads to be executed in an arithmetic unit, a loop predicting unit for predicting a loop of an instruction string on the basis of a ... 01/05/06 - 20060004996 - Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an ... 12/08/05 - 20050273582 - Processor instruction with repeated execution code The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing ... 11/24/05 - 20050262333 - System, method and device for counter array for a loop detector A loop detector with an array to store a counter of loop iterations, where the number of entries in the array may be for example smaller than the number of entries in the loop detector. Entries in the array may for example be associated with more than one entry in ... 11/10/05 - 20050251669 - Apparatus having a cache and a loop buffer Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core. ... 10/06/05 - 20050223204 - Data processing apparatus adopting pipeline processing system and data processing method used in the same A data processing apparatus adopting a pipeline processing system, includes an instruction memory which store instruction packets; and a processing unit configured to execute the instruction packets sequentially in a pipeline manner. The processing unit includes an instruction queue and a loop speed-up circuit. The instruction packets stored in the ... 08/25/05 - 20050188188 - Methods and apparatus for early loop bottom detection in digital signal processors Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offset and configured to decode instructions following the loop setup instruction, each ... 06/30/05 - 20050144426 - Processor with improved repeat string operations A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes a shadow ECX register operating in parallel with an architectural ... 06/23/05 - 20050138341 - Method and apparatus for a stew-based loop predictor A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of ... ### FreshPatents.com Support |