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Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors) > Processing Control > Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt) > Conditional Branching > Branch Prediction Branch PredictionBranch Prediction patent applications listed are from June 2005 to current and include Date, Patent Application Number, Patent Title, Patent Abstract summary and are linked to the corresponding patent application page.10/12/06 - 20060230259 - Instruction memory unit and method of operation An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of ... 10/05/06 - 20060224872 - System for speculative branch prediction optimization and method thereof A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative branch prediction efficiency may be represented by the average number of clocks per instruction (CPI), whereby an increase in the average CPI indicates that the processor ... 10/05/06 - 20060224871 - Wide branch target buffer A system comprising a pipeline in which a first plurality of instructions are processed, and a branch prediction module coupled to the pipeline, where the branch prediction module is adapted to predict the outcomes of at least some branch instructions in the first plurality of instructions and in a second ... 08/17/06 - 20060184778 - Systems and methods for branch target fencing Systems and methods for handling the event of a wrong branch prediction and an instruction rejection in a digital processor are disclosed. More particularly, hardware and software are disclosed for detecting a condition where a branch instruction was mispredicted and an instruction that preceded the branch instruction is rejected after ... 08/10/06 - 20060179292 - Microprocessor device and branch prediction method The invention relates to a microprocessor device and to a branch prediction method that determines which of a plurality of predetermined branch classes a respective branch instruction to be executed is assigned to, and determines whether the branch is likely to be taken or not, depending on the branch class ... 08/03/06 - 20060174097 - Generation of a computer program to test for correct operation of a data processing apparatus Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for ... 07/06/06 - 20060149950 - Data processing device with branch prediction mechanism Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a ... 07/06/06 - 20060149949 - Data processing device with branch prediction mechanism Phantom entries of entries in a branch history are completely detected using a flag identifying a phantom and a flag detecting the misalignment between the address of an instruction and an address where a branch has been predicted, which are provided for a queue executing branch instruction and controlling a ... 07/06/06 - 20060149948 - Branch predicting apparatus and branch predicting method A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return ... 07/06/06 - 20060149947 - Branch instruction prediction and skipping method using addresses of precedent instructions A method of predicting branch instructions and a method of skipping branch instructions for pipelines which need more than one cycle to predict branch direction and branch target addresses in microprocessors and digital signal processors are provided. The address of an instruction executed before the predicted branch is used as ... 05/04/06 - 20060095746 - Branch predictor, processor and branch prediction method A branch predictor configured to communicate information between first and second thread execution units includes a first branch prediction table configured to store branch prediction information of the first thread execution unit. A second branch prediction table is configured to store branch prediction information of the second thread execution unit. ... 04/27/06 - 20060090063 - Method for executing structured symbolic machine code on a microprocessor The invention describes a method for executing structured symbolic machine code on a microprocessor. Said structured symbolic machine code contains a set of one or more regions, where each of said regions contains symbolic machine code containing, in addition to the proper instructions, information about the symbolic variables, the symbolic ... 02/16/06 - 20060036837 - Prophet/critic hybrid predictor A hybrid prophet/critic predictor includes a first branch predictor to provide a first branch prediction for a branch under prediction (BUP) based on a branch history of the BUP and/or a program counter, and also includes a second branch predictor to provide a second branch prediction for the BUP based ... 02/02/06 - 20060026409 - Branch instruction control apparatus and control method The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when ... 02/02/06 - 20060026408 - Run-time updating of prediction hint instructions The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance data. Also, the invention provides an instruction cache that modifies hints and writes them back. As runtime hint updates are stored in ... 01/19/06 - 20060015706 - Tlb correlated branch predictor and method for use thereof Embodiments of the present invention relate to an apparatus and method to enable efficient branch prediction in super-scalar and other branching-enabled processors. In accordance with an embodiment of the present invention, a branch predictor may include a branch prediction circuit to predict a branch outcome in an executing instruction in ... 12/15/05 - 20050278517 - Systems and methods for performing branch prediction in a variable length instruction set microprocessor A method of performing branch prediction in a microprocessor using variable length instructions is provided. An instruction is fetched from memory based on a specified fetch address and a branch prediction is made based on the address. The prediction is selectively discarded if the look-up was based on a non-sequential ... 12/01/05 - 20050268076 - Variable group associativity branch target address cache delivering multiple target addresses per cache line A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different ... 12/01/05 - 20050268075 - Multiple branch predictions Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the instruction flow for a high bandwidth pipeline utilized in advanced performance environments. Branch predictions are concurrently generated for multiple branch-type instructions. The concurrently generated branch predictions are then supplied ... 11/24/05 - 20050262332 - Method and system for branch target prediction using path information A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed ... 11/17/05 - 20050257036 - State machine based filtering of non-dominant branches to use a modified gshare scheme Disclosed is a method and apparatus providing the ability to create a multi-level prediction algorithm where branch predictions beyond the first level of prediction are maintained at a secondary level because the prior level was unsuccessfully able to highly predict accurate the direction of the stated branch. A secondary level ... 10/06/05 - 20050223203 - Segmented branch predictor A branch prediction technique involving segmented branch history information, intermediate branch predictors, and a final branch prediction. More particularly, embodiments of the invention relate to segmenting a branch prediction into an intermediate prediction and a final prediction, which uses the intermediate prediction to generate a final branch prediction. ... 09/22/05 - 20050210225 - Hybrid branch prediction A hybrid branch predictor capable of performing static and dynamic branch prediction operates in a single pipeline stage. ... 08/25/05 - 20050188187 - Apparatus and method for controlling instructions at time of failure of branch prediction An apparatus includes a branch instruction prediction unit configured to make branch prediction, and a branch prediction control unit configured to control an instruction fetch control unit, an instruction buffer, an instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch ... 07/14/05 - 20050154867 - Autonomic method and apparatus for counting branch instructions to improve branch predictions A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch instructions that are executed in a processor to collect branch statistics. A set of branch statistics fields is allocated to associate with a branch ... 07/07/05 - 20050149709 - Prediction based indexed trace cache A system and method for compensating for branching instructions in trace caches is disclosed. A branch predictor uses the branching behavior of previous branching instructions to select between several traces beginning at the same linear instruction pointer (LIP) or instruction. The fetching mechanism of the processor selects the trace that ... 07/07/05 - 20050149708 - System, method and device for queuing branch predictions A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for example a segmented cache ... 07/07/05 - 20050149707 - Predicting instruction branches with a plurality of global predictors Systems and methods of processing branch instructions provide for a bimodal predictor and a plurality of global predictors. The bimodal predictor is coupled to a prediction selector, where the bimodal predictor generates a bimodal prediction for branch instructions. The plurality of global predictors is coupled to the prediction selector, where ... 06/16/05 - 20050132176 - Method for identifying basic blocks with conditional delay slot instructions A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the branch is mispredicted, the first tag is broadcast to pipeline stages that may have speculative ... 06/16/05 - 20050132175 - Speculative hybrid branch direction predictor An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTAC is accessed in parallel with ... 06/16/05 - 20050132174 - Predicting instruction branches with independent checking predictions Systems and methods of predicting instruction branches provide for independent checking predictions and dynamic next-line predictions. Next-line predictions may also have a latency that is a plurality of clock cycles, where the next line predictions include group predictions. Each group prediction includes a plurality of target addresses corresponding to their ... 06/09/05 - 20050125646 - Method and apparatus for branch prediction A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information ... 06/09/05 - 20050125645 - Method and apparatus for prediction for fork and join instructions in speculative execution A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a speculative thread would execute desirably. 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